CN212811354U - Mobile phone wireless charging transmitting system with constant-power constant-current working mode - Google Patents
Mobile phone wireless charging transmitting system with constant-power constant-current working mode Download PDFInfo
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- CN212811354U CN212811354U CN202020573153.6U CN202020573153U CN212811354U CN 212811354 U CN212811354 U CN 212811354U CN 202020573153 U CN202020573153 U CN 202020573153U CN 212811354 U CN212811354 U CN 212811354U
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Abstract
The utility model discloses a wireless transmitting system that charges of cell-phone with constant power constant current mode of operation belongs to electronic equipment's technical field. The structure of the device comprises a power management circuit (1), an energy emission circuit (3) and a singlechip (12), and is characterized by further comprising a voltage regulation circuit (2), a current detection amplification circuit (4), a signal shaping circuit (5), an output automatic control circuit (6), a voltage detection circuit (7), a second A/D conversion circuit (8), a first D/A conversion circuit (9), a first A/D conversion circuit (10) and a second D/A conversion circuit (11). The utility model discloses can the automatically regulated energy transmitting circuit's operating voltage, make transmitting system work at the best voltage all the time, and the system has characteristics such as safe and reliable, convenient to use.
Description
Technical Field
The utility model belongs to the technical field of electronic equipment. In particular to a mobile phone wireless charging transmitting system with a constant power and constant current working mode.
Background
After the electric power enters human life, the electric wire is almost ubiquitous as a medium for transmitting the electric energy, and brings great convenience to our life. However, the wired energy transmission mode is limited by space occupation and potential safety hazards brought by contact of electric equipment. The wireless energy transmission system has no direct electrical connection, can realize energy supply without space limitation of wireless equipment, and has the advantages of no plug-in link, no exposed conductor, no electric leakage and no electric shock hazard and the like. Undoubtedly, the charging manner of the mobile phone will gradually develop towards wireless charging.
The closest prior art to the present application is the chinese patent with application number 2018108887219, "an adaptive-reactance wireless energy transmission system", which rectifies 220V/50Hz mains supply into dc regulated power, then inverts the dc regulated power into 50kHz high frequency ac power by a high frequency inverter circuit, the transmitting coil (in inductive form) performs frequency-selective resonance in cooperation with a proper capacitor, converts the electric power into magnetic energy, and then receives the energy by the receiving coil in a magnetic coupling resonance manner to realize wireless charging.
However, the above patents also have certain disadvantages: the high-frequency inverter circuit at the core of the high-frequency inverter circuit adopts fixed voltage for power supply, the equivalent impedance reflected to a transmitting system by a receiving end is ever-changing, when the reflection impedance is reduced, the inverter current is increased, and therefore the system is threatened and even damaged, otherwise when the reflection impedance is increased, the inverter current is reduced, the charging power is too small, and the charging speed is slowed down. On the other hand, when the load disappears completely (such as being full or removing the charged device), the system does not automatically stop transmitting energy, and according to the mutual inductance coupling theory, the transmitting system can transmit energy at the maximum power instead, resulting in energy loss and system damage.
In summary, in order to further improve the safety and reliability of the transmitting system, the existing wireless charging technology needs to be improved.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is, to the shortcoming that prior art exists, provide a cell-phone wireless transmitting system that charges with constant power constant current mode of operation to the change of load, the security that improves the system when the adaptation charges.
The utility model discloses a specific technical scheme is:
a mobile phone wireless charging emission system with constant power and constant current working mode has a structure comprising a power management circuit 1, an energy emission circuit 3 and a singlechip 12, and is characterized in that the structure also comprises a voltage regulation circuit 2, a current detection amplification circuit 4, a signal shaping circuit 5, an output automatic control circuit 6, a voltage detection circuit 7, a second A/D conversion circuit 8, a first D/A conversion circuit 9, a first A/D conversion circuit 10 and a second D/A conversion circuit 11; the power management circuit 1 converts the +5V voltage input by the USB connecting line into different voltages required by the system, and provides required power for other modules in the system; the single chip microcomputer 12 is respectively connected with the output ends of the first A/D conversion circuit 10 and the second A/D conversion circuit 8 and the input ends of the first D/A conversion circuit 9, the second D/A conversion circuit 11 and the energy transmitting circuit 3, the output end of the second D/A conversion circuit 11 is connected with the input end of the voltage adjusting circuit 2, the output end of the voltage adjusting circuit 2 is connected with the input ends of the energy transmitting circuit 3, the voltage detecting circuit 7 and the output automatic control circuit 6, the output end of the energy transmitting circuit 3 is connected with the input end of the current detecting amplifying circuit 4, the output end of the current amplifying detecting circuit 4 is connected with the input end of the signal shaping circuit 5, the output end of the signal shaping circuit 5 is connected with the input end of the second A/D conversion circuit 8, the output end of the voltage detecting circuit 7 is connected with the input end of the first A/D conversion circuit 10, the output end of the first D/A conversion circuit 9 is connected with the input end of the output automatic control circuit 6, and the output end of the output automatic control circuit 6 is connected with the input end of the current detection amplifying circuit 4;
the structure of the power management circuit 1 is as follows: the A, B, G, S and S ends of a USB 3.1TYPE C interface J are grounded, the A and A ends are connected with a power supply VDD, the B and B ends are connected with one end of a resistor R, one end of the R, a pin 6 of a boost control chip U and the anode of an electrolytic capacitor C, the A and A ends are used as a first output end of a power supply management circuit 1 and are marked as a port P-out, the cathode of the electrolytic capacitor C is grounded, the other end of the resistor R is connected with one end of the R and the same-direction input end of an operational amplifier U2, the other end of the resistor R is grounded, the output end of the operational amplifier U2 is connected with the inverted input end of the operational amplifier U2 and is used as a second output end of the power supply management circuit 1 and is marked as a port P-out, the other end of the resistor R is connected with one end of the resistor R, one end of an inductor L and a pin 7 of the boost control chip, a pin 5 of a boost control chip U1 is connected with one end of an R3 and a slide wire end of a slide rheostat, the other end of a resistor R3 is connected with a pin 4 of the boost control chip and the ground, the other end of an inductor L1 is connected with a pin 1 of the boost control chip U1, a drain of a field-effect tube Q1 and an anode of a diode D1, a grid of the field-effect tube Q1 is connected with a pin 2 of the boost control chip U1, a source of the field-effect tube Q2 is connected with one end of a capacitor C2 and the ground, the other end of the capacitor C2 is connected with a pin 3 of the boost control chip U1, the other end of the slide rheostat is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a cathode of the diode D1 and serves as a third output;
the structure of the voltage regulating circuit 2 is as follows: one end of a resistor R8 and one end of a capacitor C3 are connected with a power supply VDD/2, the other end of the resistor R8 is connected with one end of a resistor R9 and the equidirectional input end of an operational amplifier U3B, the other end of a capacitor C3 is connected with one end of a resistor R7 and the inverting input end of an operational amplifier U3A, the other end of a resistor R7 is connected with the other end of a resistor R9 and the output end of the operational amplifier U3B, one end of a singlechip is connected with one end of a second D/A converter, the other end of the second D/A converter is connected with the equidirectional input end of the operational amplifier U3A, the output end of the operational amplifier U3A is connected with a gate of a field effect tube Q2, a drain of the field effect tube Q2 is used as a first input end of a voltage regulation circuit module and is recorded as a port HV-in and is connected with a port HV-out of the power management circuit module 1, a source of a field effect tube Q2 is connected with one end of an L356 and a cathode of a diode D2, the cathode of the electrolytic capacitor C4 is connected with the cathode of the diode and is grounded;
the structure of the energy transmitting circuit 3 is as follows: the singlechip is respectively connected with one ends of resistors R14, R15, R16 and R17, the other end of a resistor R14 is connected with a pin 1 of a low-level MOS tube driving chip U4, the other end of a resistor R15 is connected with a pin 4 of a low-level MOS tube driving chip U4, the other end of a resistor R16 is connected with a pin 1 of a low-level MOS tube driving chip U5, the other end of a resistor R17 is connected with a pin 4 of a low-level MOS tube driving chip U5, a pin 2 and a pin 3 of a low-level MOS tube driving chip U4 are grounded, a pin 2 and a pin 3 of a low-level MOS tube driving chip U5 are grounded, a pin 8 of the low-level MOS tube driving chip U4 is connected with one end of a resistor R18, one end of a resistor R19 and one end of a capacitor C5 and is connected with a power supply VDD, a pin 7 of the low-level MOS tube driving chip U4 is connected with the other end of the resistor R18 and a pin 2 of a high-level MOS tube driving chip U828653, a pin 5 of a low-level MOS tube driving chip U4 is connected with the other end of a capacitor C5 and is grounded, a pin 8 of a low-level MOS tube driving chip U5 is connected with one end of a resistor R20, one end of a resistor R21 and one end of a capacitor C7 and is grounded, a pin 7 of the low-level MOS tube driving chip U5 is connected with the other end of a resistor R20 and a pin 2 of a high-level MOS tube driving chip U7, a pin 6 of a low-level MOS tube driving chip U5 and the other end of a resistor R21 are connected with a pin 3 of a high-level MOS tube driving chip U7, a pin 5 of a low-level MOS tube driving chip U5 is connected with the other end of the capacitor C7 and is grounded, a pin 1 of the high-level MOS tube driving chip U6 is connected with one end of the capacitor C6 and is grounded, a pin 4 of the high-level MOS tube driving chip U6 is connected with the other end of the capacitor C6 and is grounded, a pin 1 of the high-level MOS tube driving chip U7 is connected with one end of the capacitor C5 and is grounded, an 8 pin of a high-order MOS tube driving chip U6 is connected with a cathode of a diode D3 and one end of a capacitor C9, the other end of the diode D3 is connected with one end of a resistor R22, the other end of a resistor R22 is connected with a power supply VDD, a 7 pin of the high-order MOS tube driving chip U6 is connected with one end of a capacitor R24, a 6 pin of the high-order MOS tube driving chip U6 is connected with the other end of the capacitor C9, one end of a resistor R25, a source of a field effect tube Q3, a drain of the field effect tube Q4 and one end of a capacitor C11, the other end of the resistor R24 is connected with the other end of a resistor R25 and a gate of the field effect tube Q3, a 5 pin of the high-order MOS tube driving chip U6 is connected with one end of the resistor R26 and a gate of the field effect tube Q26, the other end of the resistor R26 is connected with a cathode of the diode D26 and one end of the capacitor C26, and an anode of the resistor R26 are connected with one end of the diode, the other end of the resistor R23 is connected with a power supply VDD, a pin 7 of a high-order MOS tube driving chip U7 is connected with one end of a resistor R28, a pin 6 of the high-order MOS tube driving chip U7 is connected with the other end of a capacitor C10 and one end of a resistor R29, the source of a field-effect tube Q5, one end of an inductor L3 is connected with the drain of a field-effect tube Q6, a pin 5 of the high-order MOS tube driving chip U7 is connected with one end of a resistor R30, a pin 7 of the high-order MOS tube driving chip U7 is connected with one end of a resistor R28, the other end of the resistor R28 is connected with the other end of a resistor R29 and the gate of a field-effect tube Q5, the drain of the field-effect tube Q3 is connected with the drain of the field-effect tube Q5 and serves as a first input end of the energy emission circuit module 3, which is marked as a port ADV-in1, the output end of the voltage regulation circuit module 2 is connected with an output end ADV-out, the other end, The other end of the resistor R31 is connected with the source electrode of the field effect transistor Q6 and serves as a first output end of the energy transmitting circuit module 3, and is marked as a port SampV-out;
the current detection amplifying circuit 4 has the structure that: the source of the fet Q7 is grounded, the gate of the fet Q7 is used as the first input terminal of the current detection amplifying circuit module 4, which is denoted as port ctrl v-in, and is connected to the ctrl v-out port of the output automatic control circuit module 6, the drain of the fet Q7 is connected to the equidirectional input terminal of the operational amplifier U8B and one end of the resistor Rs, the inverting input terminal of the operational amplifier U8B is connected to one end of the resistor R35, one end of the sliding varistor W2 and one end of the resistor R34, the other end of the resistor R35 is connected to the power supply VDD/2, the output terminal of the operational amplifier U8B is connected to the other end of the resistor R34 and one end of the resistor R33, the other end of the resistor R33 is connected to the slider end of the sliding varistor W2, one end of the resistor R32 and the inverting input terminal of the operational amplifier U8A, the other end of the resistor Rs is connected to the non-phased input terminal of the operational amplifier U8, is recorded as: the sampV-in is connected with a sampV-out port of the energy transmitting circuit module 3, and the output end of the operational amplifier U8A is connected with the other end of the resistor R32 and serves as a first output end of the current detection amplifying circuit module 4, which is marked as AmpV-out;
the signal shaping circuit 5 has the following structure: one end of a resistor R36 serving as a first input end of the signal shaping circuit module 5 is recorded as a port AmpV-in, and is connected with an output port AmpV-out of the current detection amplifying circuit module 4, the other end of the resistor R36 is connected with one end of a capacitor C12, one end of a resistor R37 and one end of a resistor R38, the other end of the capacitor C12 is connected with a homodromous input end of an operational amplifier U9A and is connected with a power supply VDD/2, the other end of a resistor R37 is connected with one end of a capacitor C13 and an inverting input end of an operational amplifier U9A, the other end of the resistor R38 is connected with an output end of a capacitor C13, an output end of an operational amplifier U9A and a resistor R39, the other end of a resistor R39 is connected with one end of a resistor R41, one end of a resistor R40 and one end of a capacitor C14, the other end of a capacitor C14 and the non-inverting input end of an operational amplifier U9 are connected with a power supply VDD, the other end, the other input end of the resistor R41 is connected with the other end of the capacitor C15, the output end of the operational amplifier U9B and a second A/D conversion circuit, and the second conversion circuit is connected with the single chip microcomputer;
the structure of the output automatic control circuit 6 is as follows: the singlechip is connected with a first D/A conversion circuit, the first D/A conversion circuit is connected with an inverting input end of an operational amplifier U10A, one end of a resistor R42 is connected with a negative electrode of a voltage stabilizing diode D5 and a non-inverting input end of the operational amplifier U10A, an anode of a voltage stabilizing diode D5 is grounded, the other end of the resistor R42 is used as a first input end of an automatic control circuit module 6 and is marked as a port ADV-in2 and is connected with an ADV-out port of a voltage regulating circuit module 2, an output end of the operational amplifier U10A is connected with a base electrode of a triode Q8, a collector electrode of the triode Q8 is connected with a power supply VDD, an emitter electrode of a triode Q8 is connected with one end of a resistor R44, one end of a resistor R8 and an emitter electrode of a triode Q9, the other end of a resistor R44 is grounded, the other end of the resistor R43 is connected with one end of a capacitor C16 and an input end of an inverting Schmitt trigger U11A, the other end of the capacitor C16 is grounded, and an inverting trigger U, a pin 1 of a D trigger U12A is connected with a pin 2 and one end of a capacitor C17 and is grounded, a pin 4 of the D trigger U12A is connected with the other end of the capacitor C17, one end of the capacitor R45 and the anode of a diode D6, a pin 6 of the D trigger U12A is connected with the other end of a resistor R45 and the cathode of the diode, a pin 5 of the D trigger U12A is connected with a pin 11 of the D trigger U12B and serves as a first output end of the output automatic control circuit module 6, which is denoted by Ctrl-out, a pin 12 of the D trigger U12B is connected with one end and a pin 13 of a capacitor C18 and is grounded, a pin 10 of the D trigger U12B is connected with the other end of the capacitor C18 and one end of a resistor R46 and the anode of a diode D7, a pin 8 of the D trigger U12 is connected with the other end of the resistor R46 and the cathode of a diode D7, a pin 8 of the D trigger U12 is connected with the inverted base of the transistor U599 and the inverted transistor Q599 of the inverted transistor Q B, the collector of the triode Q9 is connected with a power supply VDD;
the voltage detection circuit 7 has the following structure: one end of a resistor R48 is connected with one end of a capacitor C19 and is grounded, the other end of a resistor R48 is connected with the other end of the capacitor C19, one end of a resistor R47 and the non-inverting input end of an operational amplifier U2B, the other end of a resistor R47 is used as the first input end of the voltage detection circuit module 7 and is recorded as a port ADV-in3 and is connected with an ADV-out port of the voltage regulation circuit module 2, the output end of the operational amplifier U2B is connected with the inverting input end and the first A/D conversion circuit, and the first A/D conversion circuit is connected with the single chip microcomputer.
In the output automatic control circuit 7, the value of the resistor R45 is 1M omega, the value of the resistor R46 is 100k omega, the value of the capacitor C17 is 1uF, and the value of the capacitor C18 is 100 nF.
Has the advantages that:
1. the utility model discloses can the automatically regulated energy transmitting circuit's operating voltage, make transmitting system work all the time at the best voltage, improved transmitting system's efficiency.
2. The utility model discloses can prevent that transmitting system from carrying out high-power energy transmission when empty load, make transmitting system can work safe and reliable ground.
3. The utility model discloses an output automatic control circuit self-starting when realizing having the load makes the system use more convenient.
4. The utility model discloses simultaneously gather energy transmitting circuit's voltage and electric current simultaneously through two way AD converting circuit, for the singlechip provides voltage, electric current data, can pass through single chip microcomputer control system work at constant current or constant power mode as required in the working process.
Drawings
Fig. 1 is a block diagram of the overall structure of the present invention.
Fig. 2 is a functional block diagram of a power management circuit.
Fig. 3 is a schematic circuit diagram of a voltage regulating circuit.
Fig. 4 is a schematic circuit diagram of an energy transmission circuit.
Fig. 5 is a schematic circuit diagram of the current detection amplifying circuit.
Fig. 6 is a schematic circuit diagram of a signal shaping circuit.
Fig. 7 is a schematic circuit diagram of an output automatic control circuit.
Fig. 8 is a schematic circuit diagram of the voltage detection circuit.
Detailed Description
The following description will further describe the embodiments of the present invention with reference to the accompanying drawings, wherein the parameters indicated in the drawings are the preferred parameters of the various elements in the embodiments.
EXAMPLE 1 the overall structure of the present invention
As shown in fig. 1, the utility model discloses a wireless charging emission system of cell-phone with constant power constant current mode of operation, its structure has power management circuit 1, voltage regulation circuit 2, energy transmitting circuit 3, current detection amplifier circuit 4, signal shaping circuit 5, output automatic control electricity 6, voltage detection circuit 7, second AD converting circuit 8, first DA converting circuit 9, first AD converting circuit 10, second DA converting circuit 11, singlechip 12; the power management circuit 1 converts the +5V voltage input by the USB connecting line into different voltages required by the system, and provides required power for other modules in the system; the single chip microcomputer 12 is respectively connected with the output ends of the first A/D conversion circuit 10 and the second A/D conversion circuit 8 and the input ends of the first D/A conversion circuit 9, the second D/A conversion circuit 11 and the energy transmitting circuit 3, the output end of the second D/A conversion circuit 11 is connected with the input end of the voltage adjusting circuit 2, the output end of the voltage adjusting circuit 2 is connected with the input ends of the energy transmitting circuit 3, the voltage detecting circuit 7 and the output automatic control circuit 6, the output end of the energy transmitting circuit 3 is connected with the input end of the current detecting amplifying circuit 4, the output end of the current amplifying detecting circuit 4 is connected with the input end of the signal shaping circuit 5, the output end of the signal shaping circuit 5 is connected with the input end of the second A/D conversion circuit 8, the output end of the voltage detecting circuit 7 is connected with the input end of the first A/D conversion circuit 10, the output end of the first D/a conversion circuit 9 is connected to the input end of the output automatic control circuit 6, and the output end of the output automatic control circuit 6 is connected to the input end of the current detection amplifying circuit 4.
The structure of the power management circuit 1 is shown in fig. 2: the A, B, G, S and S ends of a USB 3.1TYPE C interface J are grounded, the A and A ends are connected with a power supply VDD, the B and B ends are connected with one end of a resistor R, one end of the R, a pin 6 of a boost control chip U and the anode of an electrolytic capacitor C, the A and A ends are used as a first output end of a power supply management circuit 1 and are marked as a port P-out, the cathode of the electrolytic capacitor C is grounded, the other end of the resistor R is connected with one end of the R and the same-direction input end of an operational amplifier U2, the other end of the resistor R is grounded, the output end of the operational amplifier U2 is connected with the inverted input end of the operational amplifier U2 and is used as a second output end of the power supply management circuit 1 and is marked as a port P-out, the other end of the resistor R is connected with one end of the resistor R, one end of an inductor L and a pin 7 of the boost control chip, the 5 pin of the boost control chip U1 is connected with one end of the R3 and the slide wire end of the slide rheostat, the other end of the resistor R3 is connected with the 4 pin of the boost control chip and the ground, the other end of the inductor L1 is connected with the 1 pin of the boost control chip U1, the drain of the field effect transistor Q1 and the anode of the diode D1, the gate of the field effect transistor Q1 is connected with the 2 pin of the boost control chip U1, the source of the field effect transistor Q2 is connected with one end of the capacitor C2 and the ground, the other end of the capacitor C2 is connected with the 3 pin of the boost control chip U1, the other end of the slide rheostat is connected with one end of the resistor R4, and the other end of the resistor R4 is connected with the cathode of the diode D1 and serves as the third output end of.
The power management circuit 1 converts the +5V power of USB interface with the utility model discloses the required different voltages of each module: a 48V voltage for providing high power to the voltage regulating circuit, and is output through a port HV-out; the power supply is used for supplying power VDD (+5V) to each module and is output through a port P-out 1; and the power supply is used for supplying power VDD/2(+2.5V) to each module and is output through a port P-out 2.
The structure of the voltage regulating circuit 2 is shown in fig. 3: one end of a resistor R8 and one end of a capacitor C3 are connected with a power supply VDD/2, the other end of the resistor R8 is connected with one end of a resistor R9 and the equidirectional input end of an operational amplifier U3B, the other end of a capacitor C3 is connected with one end of a resistor R7 and the inverting input end of an operational amplifier U3A, the other end of a resistor R7 is connected with the other end of a resistor R9 and the output end of the operational amplifier U3B, one end of a singlechip is connected with one end of a second D/A converter, the other end of the second D/A converter is connected with the equidirectional input end of the operational amplifier U3A, the output end of the operational amplifier U3A is connected with a gate of a field effect tube Q2, a drain of the field effect tube Q2 is used as a first input end of a voltage regulation circuit module and is recorded as a port HV-in and is connected with a port HV-out of the power management circuit module 1, a source of a field effect tube Q2 is connected with one end of an L356 and a cathode of a diode D2, the cathode of the electrolytic capacitor C4 is connected to the cathode of the diode and to ground, denoted as port ADV-out.
The voltage regulating circuit 2 is controlled by the second D/a converting circuit 11, when in the constant current working mode, the single chip microcomputer 12 compares the digital signal (the signal is the working current of the energy transmitting circuit 3, actually reflects the size of the load) sampled by the second a/D converting circuit 8 with a preset reference current value to find a difference, the difference is converted into an analog signal by the second D/a converting circuit 11 and then input to the control end of the voltage regulating circuit 2, and the voltage regulating circuit 2 converts the 48V voltage provided by the power management module 1 into a voltage matched with the actual load according to the signal; in the constant power mode, the difference is that the single chip microcomputer multiplies the digital signal sampled by the second a/D conversion circuit 8 by the digital signal sampled by the first a/D conversion circuit 10 to obtain the transmission power, and then compares the power value with a preset power value to obtain the difference.
EXAMPLE 4 energy emitting Circuit
The structure of the energy transmitting circuit 3 is shown in fig. 4: the singlechip is respectively connected with one ends of resistors R14, R15, R16 and R17, the other end of a resistor R14 is connected with a pin 1 of a low-level MOS tube driving chip U4, the other end of a resistor R15 is connected with a pin 4 of a low-level MOS tube driving chip U4, the other end of a resistor R16 is connected with a pin 1 of a low-level MOS tube driving chip U5, the other end of a resistor R17 is connected with a pin 4 of a low-level MOS tube driving chip U5, a pin 2 and a pin 3 of a low-level MOS tube driving chip U4 are grounded, a pin 2 and a pin 3 of a low-level MOS tube driving chip U5 are grounded, a pin 8 of the low-level MOS tube driving chip U4 is connected with one end of a resistor R18, one end of a resistor R19 and one end of a capacitor C5 and is connected with a power supply VDD, a pin 7 of the low-level MOS tube driving chip U4 is connected with the other end of the resistor R18 and a pin 2 of a high-level MOS tube driving chip U828653, a pin 5 of a low-level MOS tube driving chip U4 is connected with the other end of a capacitor C5 and is grounded, a pin 8 of a low-level MOS tube driving chip U5 is connected with one end of a resistor R20, one end of a resistor R21 and one end of a capacitor C7 and is grounded, a pin 7 of the low-level MOS tube driving chip U5 is connected with the other end of a resistor R20 and a pin 2 of a high-level MOS tube driving chip U7, a pin 6 of a low-level MOS tube driving chip U5 and the other end of a resistor R21 are connected with a pin 3 of a high-level MOS tube driving chip U7, a pin 5 of a low-level MOS tube driving chip U5 is connected with the other end of the capacitor C7 and is grounded, a pin 1 of the high-level MOS tube driving chip U6 is connected with one end of the capacitor C6 and is grounded, a pin 4 of the high-level MOS tube driving chip U6 is connected with the other end of the capacitor C6 and is grounded, a pin 1 of the high-level MOS tube driving chip U7 is connected with one end of the capacitor C5 and is grounded, an 8 pin of a high-order MOS tube driving chip U6 is connected with a cathode of a diode D3 and one end of a capacitor C9, the other end of the diode D3 is connected with one end of a resistor R22, the other end of a resistor R22 is connected with a power supply VDD, a 7 pin of the high-order MOS tube driving chip U6 is connected with one end of a capacitor R24, a 6 pin of the high-order MOS tube driving chip U6 is connected with the other end of the capacitor C9, one end of a resistor R25, a source of a field effect tube Q3, a drain of the field effect tube Q4 and one end of a capacitor C11, the other end of the resistor R24 is connected with the other end of a resistor R25 and a gate of the field effect tube Q3, a 5 pin of the high-order MOS tube driving chip U6 is connected with one end of the resistor R26 and a gate of the field effect tube Q26, the other end of the resistor R26 is connected with a cathode of the diode D26 and one end of the capacitor C26, and an anode of the resistor R26 are connected with one end of the diode, the other end of the resistor R23 is connected with a power supply VDD, a pin 7 of a high-order MOS tube driving chip U7 is connected with one end of a resistor R28, a pin 6 of the high-order MOS tube driving chip U7 is connected with the other end of a capacitor C10 and one end of a resistor R29, the source of a field-effect tube Q5, one end of an inductor L3 is connected with the drain of a field-effect tube Q6, a pin 5 of the high-order MOS tube driving chip U7 is connected with one end of a resistor R30, a pin 7 of the high-order MOS tube driving chip U7 is connected with one end of a resistor R28, the other end of the resistor R28 is connected with the other end of a resistor R29 and the gate of a field-effect tube Q5, the drain of the field-effect tube Q3 is connected with the drain of the field-effect tube Q5 and serves as a first input end of the energy emission circuit module 3, which is marked as a port ADV-in1, the output end of the voltage regulation circuit module 2 is connected with an output end ADV-out, the other end, The other end of the resistor R31 is connected to the source of the fet Q6 and serves as the first output terminal of the energy transmitting circuit block 3, denoted as the port SampV-out.
The energy transmitting circuit 3 converts the voltage provided by the voltage regulating circuit into an oscillating sine wave current under the control of a PWM time sequence (50kHz) provided by the singlechip, the oscillating sine wave current flows through an inductor L3 (namely a transmitting coil), the transmitting coil converts the current into variable magnetic field energy for transmitting, and the variable magnetic field energy is received by a receiving coil at the receiving end of the mobile phone, so that the wireless charging of the mobile phone is realized. The optocoupler chips U4 and U5 are used for electrically isolating the singlechip from the power circuit so as to improve the stability of the circuit; the MOS tube driving chips U6 and U7 increase the PWM time sequence to the level capable of driving the MOS tubes, and are used for driving the MOS tube bridge formed by Q3, Q4, Q5 and Q6.
The structure of the current detection amplifying circuit 4 is shown in fig. 5: the source of the fet Q7 is grounded, the gate of the fet Q7 is used as the first input terminal of the current detection amplifying circuit module 4, which is denoted as port ctrl v-in, and is connected to the ctrl v-out port of the output automatic control circuit module 6, the drain of the fet Q7 is connected to the equidirectional input terminal of the operational amplifier U8B and one end of the resistor Rs, the inverting input terminal of the operational amplifier U8B is connected to one end of the resistor R35, one end of the sliding varistor W2 and one end of the resistor R34, the other end of the resistor R35 is connected to the power supply VDD/2, the output terminal of the operational amplifier U8B is connected to the other end of the resistor R34 and one end of the resistor R33, the other end of the resistor R33 is connected to the slider end of the sliding varistor W2, one end of the resistor R32 and the inverting input terminal of the operational amplifier U8A, the other end of the resistor Rs is connected to the non-phased input terminal of the operational amplifier U8, is recorded as: the SampV-in is connected with the SampV-out port of the energy transmitting circuit module 3, and the output end of the operational amplifier U8A is connected with the other end of the resistor R32 and serves as the first output end of the current detection amplifying circuit module 4, which is denoted as AmpV-out.
The current detection amplifying circuit 4 samples and amplifies the working current of the energy transmitting circuit through the sampling resistor Rs and inputs the amplified working current to the signal shaping circuit 5.
The structure of the signal shaping circuit 5 is shown in fig. 6: one end of a resistor R36 serving as a first input end of the signal shaping circuit module 5 is recorded as a port AmpV-in, and is connected with an output port AmpV-out of the current detection amplifying circuit module 4, the other end of the resistor R36 is connected with one end of a capacitor C12, one end of a resistor R37 and one end of a resistor R38, the other end of the capacitor C12 is connected with a homodromous input end of an operational amplifier U9A and is connected with a power supply VDD/2, the other end of a resistor R37 is connected with one end of a capacitor C13 and an inverting input end of an operational amplifier U9A, the other end of the resistor R38 is connected with an output end of a capacitor C13, an output end of an operational amplifier U9A and a resistor R39, the other end of a resistor R39 is connected with one end of a resistor R41, one end of a resistor R40 and one end of a capacitor C14, the other end of a capacitor C14 and the non-inverting input end of an operational amplifier U9 are connected with a power supply VDD, the other end, the other input end of the resistor R41 is connected with the other end of the capacitor C15, the output end of the operational amplifier U9B and a second A/D conversion circuit, and the second conversion circuit is connected with the single chip microcomputer.
The signal shaping circuit 5 shapes the ac signal detected by the current detection amplifying circuit 4 into a dc signal suitable for analog-to-digital conversion, and sends the dc signal to the second a/D conversion circuit 8.
The structure of the voltage detection circuit 7 is shown in fig. 8: one end of a resistor R48 is connected with one end of a capacitor C19 and is grounded, the other end of a resistor R48 is connected with the other end of the capacitor C19, one end of a resistor R47 and the non-inverting input end of an operational amplifier U2B, the other end of a resistor R47 is used as the first input end of the voltage detection circuit module 7 and is recorded as a port ADV-in3 and is connected with an ADV-out port of the voltage regulation circuit module 2, the output end of the operational amplifier U2B is connected with the inverting input end and the first A/D conversion circuit, and the first A/D conversion circuit is connected with the single chip microcomputer.
The voltage detection circuit 7 detects the actual working voltage of the energy emission circuit 3 in real time, converts the actual working voltage into a digital signal through the first a/D conversion circuit, and sends the digital signal to the single chip microcomputer 12, and the single chip microcomputer multiplies the digital signal by a current signal acquired by the second a/D conversion circuit to obtain the emission power of the energy emission circuit, and when the energy emission circuit works in the constant power mode, the power is used as a basis for adjustment (as described in embodiment 3).
The structure of the output automatic control circuit 6 is shown in fig. 7: the singlechip is connected with a first D/A conversion circuit, the first D/A conversion circuit is connected with an inverting input end of an operational amplifier U10A, one end of a resistor R42 is connected with a negative electrode of a voltage stabilizing diode D5 and a non-inverting input end of the operational amplifier U10A, an anode of a voltage stabilizing diode D5 is grounded, the other end of the resistor R42 is used as a first input end of an automatic control circuit module 6 and is marked as a port ADV-in2 and is connected with an ADV-out port of a voltage regulating circuit module 2, an output end of the operational amplifier U10A is connected with a base electrode of a triode Q8, a collector electrode of the triode Q8 is connected with a power supply VDD, an emitter electrode of a triode Q8 is connected with one end of a resistor R44, one end of a resistor R8 and an emitter electrode of a triode Q9, the other end of a resistor R44 is grounded, the other end of the resistor R43 is connected with one end of a capacitor C16 and an input end of an inverting Schmitt trigger U11A, the other end of the capacitor C16 is grounded, and an inverting trigger U, a pin 1 of a D trigger U12A is connected with a pin 2 and one end of a capacitor C17 and is grounded, a pin 4 of the D trigger U12A is connected with the other end of the capacitor C17, one end of the capacitor R45 and the anode of a diode D6, a pin 6 of the D trigger U12A is connected with the other end of a resistor R45 and the cathode of the diode, a pin 5 of the D trigger U12A is connected with a pin 11 of the D trigger U12B and serves as a first output end of the output automatic control circuit module 6, which is denoted by Ctrl-out, a pin 12 of the D trigger U12B is connected with one end and a pin 13 of a capacitor C18 and is grounded, a pin 10 of the D trigger U12B is connected with the other end of the capacitor C18 and one end of a resistor R46 and the anode of a diode D7, a pin 8 of the D trigger U12 is connected with the other end of the resistor R46 and the cathode of a diode D7, a pin 8 of the D trigger U12 is connected with the inverted base of the transistor U599 and the inverted transistor Q599 of the inverted transistor Q B, the collector of the transistor Q9 is connected to the power supply VDD.
As can be seen from the description of embodiment 3, when the load is gradually decreased, the voltage output by the voltage regulating circuit 2 is gradually decreased, so that when the load is completely disappeared (i.e. no handset is charged or the power is fully charged), the voltage regulating circuit 2 outputs a very small voltage, and therefore, when the voltage detected by the voltage detecting circuit is smaller than a certain preset value (provided by the first D/a converting circuit 9), it is determined that the system is in the idle state, the output automatic control circuit 6 controls the field-effect transistor Q7 in the current detecting amplifying circuit 4 to be turned off, and the turning off of the Q7 cuts off the oscillation loop in the energy transmitting circuit 3, so that the system stops transmitting energy, and enters the power-off state, and no energy is transmitted, thereby effectively reducing the energy loss. The automatic control circuit 8 also has an automatic start function, a delay inverting structure composed of a D flip-flop U12B, an inverter U11B and the like generates a trigger signal at a certain time interval during the system standby time, so that the system tries to power on and detect, if a load is detected, the normal emission state of the circuit is maintained, if the system is still idle after the power on attempt, the system is controlled to enter a power off state again, and the process is continuously repeated in the standby process. The duration of the power-on detection is determined by a resistor R46(100k) and a capacitor C18(100nF), and the sleep time between two attempts is determined by a resistor R45(1M) and a capacitor C17(1uF), because R45 is far greater than R46 and C17 is far greater than C18, the power consumption consumed by the system in the standby process is greatly reduced.
Claims (2)
1. A mobile phone wireless charging emission system with a constant-power constant-current working mode is structurally provided with a power management circuit (1), an energy emission circuit (3) and a single chip microcomputer (12), and is characterized in that the mobile phone wireless charging emission system is further structurally provided with a voltage regulation circuit (2), a current detection amplification circuit (4), a signal shaping circuit (5), an output automatic control circuit 6, a voltage detection circuit (7), a second A/D conversion circuit (8), a first D/A conversion circuit (9), a first A/D conversion circuit (10) and a second D/A conversion circuit (11); the power management circuit (1) converts +5V voltage input by the USB connecting line into different voltages required by the system, and provides required power for other modules in the system; the singlechip (12) is respectively connected with the output ends of the first A/D conversion circuit (10) and the second A/D conversion circuit (8) and the input ends of the first D/A conversion circuit (9), the second D/A conversion circuit (11) and the energy emission circuit (3), the output end of the second D/A conversion circuit (11) is connected with the input end of the voltage regulation circuit (2), the output end of the voltage regulation circuit (2) is connected with the input ends of the energy emission circuit (3), the voltage detection circuit (7) and the output automatic control circuit (6), the output end of the energy emission circuit (3) is connected with the input end of the current detection amplifying circuit (4), the output end of the current detection amplifying circuit (4) is connected with the input end of the signal shaping circuit (5), the output end of the signal shaping circuit (5) is connected with the input end of the second A/D conversion circuit (8), the output end of the voltage detection circuit (7) is connected with the input end of the first A/D conversion circuit (10), the output end of the first D/A conversion circuit (9) is connected with the input end of the output automatic control circuit (6), and the output end of the output automatic control circuit (6) is connected with the input end of the current detection amplifying circuit (4);
the structure of the power management circuit (1) is as follows: the A, B, G, S and S ends of a USB 3.1TYPE C interface J are grounded, the A and A ends are connected with a power supply VDD, the B and B ends are connected with one end of a resistor R, one end of the R, a pin 6 of a boost control chip U and the anode of an electrolytic capacitor C, the A and A ends are used as the first output end of a power supply management circuit (1) and are marked as a port P-out, the cathode of the electrolytic capacitor C is grounded, the other end of the resistor R is connected with one end of the R and the same-direction input end of an operational amplifier U2, the other end of the resistor R is grounded, the output end of the operational amplifier U2 is connected with the inverted input end of the operational amplifier U2 and is used as the second output end of the power supply management circuit (1) and is marked as a port P-out, the other end of the resistor R is connected with one end of the resistor R, one end of an inductor L and a pin 7 of a boost control chip, a pin 5 of a boost control chip U1 is connected with one end of an R3 and a slide wire end of a slide rheostat, the other end of a resistor R3 is connected with a pin 4 of the boost control chip and the ground, the other end of an inductor L1 is connected with a pin 1 of the boost control chip U1, a drain of a field-effect tube Q1 and an anode of a diode D1, a grid of the field-effect tube Q1 is connected with a pin 2 of the boost control chip U1, a source of the field-effect tube Q2 is connected with one end of a capacitor C2 and the ground, the other end of the capacitor C2 is connected with a pin 3 of the boost control chip U1, the other end of the slide rheostat is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a cathode of the diode D1 and serves as a third output;
the structure of the voltage regulating circuit (2) is as follows: one end of a resistor R8 and one end of a capacitor C3 are connected with a power supply VDD/2, the other end of a resistor R8 is connected with one end of a resistor R9 and the equidirectional input end of an operational amplifier U3B, the other end of a capacitor C3 is connected with one end of a resistor R7 and the inverting input end of an operational amplifier U3A, the other end of a resistor R7 is connected with the other end of a resistor R9 and the output end of the operational amplifier U3B, one end of a singlechip is connected with one end of a second D/A converter, the other end of the second D/A converter is connected with the equidirectional input end of the operational amplifier U3A, the output end of the operational amplifier U3A is connected with a gate of a field effect tube Q2, a drain of the field effect tube Q2 serves as a first input end of a voltage regulation circuit and is connected with a port HV-in and a port HV-out of a power supply management circuit (1), a source of a field effect tube Q2 is connected with one end of an inductor L356 and a cathode of a diode D2, the other, the cathode of the electrolytic capacitor C4 is connected with the cathode of the diode and is grounded;
the structure of the energy emission circuit (3) is as follows: the singlechip is respectively connected with one ends of resistors R14, R15, R16 and R17, the other end of a resistor R14 is connected with a pin 1 of a low-level MOS tube driving chip U4, the other end of a resistor R15 is connected with a pin 4 of a low-level MOS tube driving chip U4, the other end of a resistor R16 is connected with a pin 1 of a low-level MOS tube driving chip U5, the other end of a resistor R17 is connected with a pin 4 of a low-level MOS tube driving chip U5, a pin 2 and a pin 3 of a low-level MOS tube driving chip U4 are grounded, a pin 2 and a pin 3 of a low-level MOS tube driving chip U5 are grounded, a pin 8 of the low-level MOS tube driving chip U4 is connected with one end of a resistor R18, one end of a resistor R19 and one end of a capacitor C5 and is connected with a power supply VDD, a pin 7 of the low-level MOS tube driving chip U4 is connected with the other end of the resistor R18 and a pin 2 of a high-level MOS tube driving chip U828653, a pin 5 of a low-level MOS tube driving chip U4 is connected with the other end of a capacitor C5 and is grounded, a pin 8 of a low-level MOS tube driving chip U5 is connected with one end of a resistor R20, one end of a resistor R21 and one end of a capacitor C7 and is grounded, a pin 7 of the low-level MOS tube driving chip U5 is connected with the other end of a resistor R20 and a pin 2 of a high-level MOS tube driving chip U7, a pin 6 of a low-level MOS tube driving chip U5 and the other end of a resistor R21 are connected with a pin 3 of a high-level MOS tube driving chip U7, a pin 5 of a low-level MOS tube driving chip U5 is connected with the other end of the capacitor C7 and is grounded, a pin 1 of the high-level MOS tube driving chip U6 is connected with one end of the capacitor C6 and is grounded, a pin 4 of the high-level MOS tube driving chip U6 is connected with the other end of the capacitor C6 and is grounded, a pin 1 of the high-level MOS tube driving chip U7 is connected with one end of the capacitor C5 and is grounded, an 8 pin of a high-order MOS tube driving chip U6 is connected with a cathode of a diode D3 and one end of a capacitor C9, the other end of the diode D3 is connected with one end of a resistor R22, the other end of a resistor R22 is connected with a power supply VDD, a 7 pin of the high-order MOS tube driving chip U6 is connected with one end of a capacitor R24, a 6 pin of the high-order MOS tube driving chip U6 is connected with the other end of the capacitor C9, one end of a resistor R25, a source of a field effect tube Q3, a drain of the field effect tube Q4 and one end of a capacitor C11, the other end of the resistor R24 is connected with the other end of a resistor R25 and a gate of the field effect tube Q3, a 5 pin of the high-order MOS tube driving chip U6 is connected with one end of the resistor R26 and a gate of the field effect tube Q26, the other end of the resistor R26 is connected with a cathode of the diode D26 and one end of the capacitor C26, and an anode of the resistor R26 are connected with one end of the diode, the other end of the resistor R23 is connected with a power supply VDD, a pin 7 of a high-order MOS tube driving chip U7 is connected with one end of a resistor R28, a pin 6 of the high-order MOS tube driving chip U7 is connected with the other end of a capacitor C10 and one end of a resistor R29, the source of a field-effect tube Q5, one end of an inductor L3 is connected with the drain of a field-effect tube Q6, a pin 5 of the high-order MOS tube driving chip U7 is connected with one end of a resistor R30, a pin 7 of the high-order MOS tube driving chip U7 is connected with one end of a resistor R28, the other end of the resistor R28 is connected with the other end of a resistor R29 and the gate of a field-effect tube Q5, the drain of the field-effect tube Q3 is connected with the drain of the field-effect tube Q5 and serves as a first input end of an energy emission circuit (3), which is marked as a port ADV-1, the output end of a voltage regulation circuit (2) is connected with an output end ADV-out, the other end of a, The other end of the resistor R31 is connected with the source electrode of the field effect transistor Q6 and serves as a first output end of the energy transmitting circuit (3) and is marked as a port SampV-out;
the current detection amplifying circuit (4) is structurally characterized in that: the source of the field effect transistor Q7 is grounded, the gate of the field effect transistor Q7 is used as the first input end of the current detection amplifying circuit (4) and is marked as a port CtrlV-in and is connected with the CtrlV-out port of the output automatic control circuit (6), the drain of the field effect transistor Q7 is connected with the same-direction input end of the operational amplifier U8B and one end of a resistor Rs, the reverse-phase input end of the operational amplifier U8B is connected with one end of a resistor R35, one end of a sliding rheostat W2 and one end of a resistor R34, the other end of the resistor R35 is connected with a power supply VDD/2, the output end of the operational amplifier U8B is connected with the other end of a resistor R34 and one end of a resistor R33, the other end of the resistor R33 is connected with the slide terminal of the sliding rheostat W2, one end of the resistor R32 and the reverse-phase input end of the operational amplifier U8A, the other end of the resistor Rs 8A is connected, is recorded as: the SampV-in is connected with a SampV-out port of the energy transmitting circuit (3), and the output end of the operational amplifier U8A is connected with the other end of the resistor R32 and serves as a first output end of the current detection amplifying circuit (4) and is marked as AmpV-out;
the signal shaping circuit (5) has the structure that: one end of a resistor R36 serves as a first input end of the signal shaping circuit (5) and is recorded as a port AmpV-in, the resistor R36 is connected with an output port AmpV-out of the current detection amplifying circuit (4), the other end of the resistor R36 is connected with one end of a capacitor C12, one end of a resistor R37 and one end of a resistor R38, the other end of a capacitor C12 is connected with the same-direction input end of an operational amplifier U9A and is connected with a power supply VDD/2, the other end of a resistor R37 is connected with one end of a capacitor C13 and the inverting input end of an operational amplifier U9A, the other end of the resistor R38 is connected with the same-phase input end of a capacitor C13, the output end of an operational amplifier U9A and a resistor R39, the other end of a resistor R39 is connected with one end of a resistor R41, one end of a resistor R40 and one end of a capacitor C14, the other end of a capacitor C14 and the same-phase input end of an operational amplifier U9 are connected with the power, the other input end of the resistor R41 is connected with the other end of the capacitor C15, the output end of the operational amplifier U9B and a second A/D conversion circuit, and the second conversion circuit is connected with the single chip microcomputer;
the structure of the output automatic control circuit (6) is as follows: the single chip microcomputer is connected with a first D/A conversion circuit, the first D/A conversion circuit is connected with an inverting input end of an operational amplifier U10A, one end of a resistor R42 is connected with a negative electrode of a voltage stabilizing diode D5 and a non-inverting input end of the operational amplifier U10A, an anode of a voltage stabilizing diode D5 is grounded, the other end of the resistor R42 is used as a first input end of an automatic control circuit (6) and is marked as a port ADV-in2 to be connected with an ADV-out port of a voltage regulating circuit (2), an output end of the operational amplifier U10A is connected with a base electrode of a triode Q8, a collector electrode of the triode Q8 is connected with a power supply VDD, an emitter electrode of a triode Q8 is connected with one end of a resistor R44, one end of a resistor R8 and an emitter electrode of a triode Q9, the other end of a resistor R44 is grounded, the other end of the resistor R43 is connected with one end of a capacitor C16 and an input end of an inverting Schmitt trigger U11A, the other end of the capacitor C42 is grounded, and an output end of, a pin 1 of a D trigger U12A is connected with a pin 2 and one end of a capacitor C17 and is connected with the ground, a pin 4 of the D trigger U12A is connected with the other end of the capacitor C17, one end of the capacitor R45 and the anode of a diode D6, a pin 6 of the D trigger U12A is connected with the other end of a resistor R45 and the cathode of the diode, a pin 5 of the D trigger U12A is connected with a pin 11 of the D trigger U12B and serves as a first output end of an output automatic control circuit (6) which is denoted by Ctrl-out, a pin 12 of the D trigger U12B is connected with one end and a pin 13 of a capacitor C18 and is connected with the ground, a pin 10 of the D trigger U12B is connected with the other end of the capacitor C18 and one end of a resistor R46 and the anode of a diode D7, a pin 8 of the D trigger U12 is connected with a pin 8 of the resistor R46 and the cathode of a diode D7, a pin 8 of the D trigger U12 is connected with the inverted base of the triode 639, the inverted base of the inverted transistor Q599 of the D trigger U B, the collector of the triode Q9 is connected with a power supply VDD;
the voltage detection circuit (7) has the structure that: one end of a resistor R48 is connected with one end of a capacitor C19 and is grounded, the other end of a resistor R48 is connected with the other end of the capacitor C19, one end of a resistor R47 and the non-inverting input end of an operational amplifier U2B, the other end of a resistor R47 is used as the first input end of a voltage detection circuit (7) and is recorded as a port ADV-in3 and is connected with an ADV-out port of a voltage regulation circuit (2), the output end of the operational amplifier U2B is connected with the inverting input end and a first A/D conversion circuit, and the first A/D conversion circuit is connected with a single chip microcomputer.
2. The wireless charging and transmitting system of claim 1, wherein the output automatic control circuit (6) has a resistor R27 with a value of 1M Ω, a resistor R28 with a value of 100k Ω, a capacitor C11 with a value of 1uF, and a capacitor C12 with a value of 100 nF.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111371159A (en) * | 2020-04-16 | 2020-07-03 | 长春工程学院 | Mobile phone wireless charging transmitting system with constant-power constant-current working mode |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111371159A (en) * | 2020-04-16 | 2020-07-03 | 长春工程学院 | Mobile phone wireless charging transmitting system with constant-power constant-current working mode |
| CN111371159B (en) * | 2020-04-16 | 2024-05-03 | 长春工程学院 | Mobile phone wireless charging and transmitting system with constant power and constant current working mode |
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