CN212785315U

CN212785315U - Phase frequency detector

Info

Publication number: CN212785315U
Application number: CN202022237170.5U
Authority: CN
Inventors: 王玉军
Original assignee: Chengdu Tiger Microelectronics Research Institute Co ltd
Current assignee: Chengdu Tiger Microelectronics Research Institute Co ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2021-03-23
Anticipated expiration: 2030-10-10

Abstract

The utility model discloses a phase frequency detector, including source signal input Ref, feedback input Div, first signal output Up, second signal output Dn, delay assembly to and first NAND gate K1~ ninth NAND gate K9; the delay assembly comprises a plurality of inverters which are sequentially connected in series, wherein the input end of the first inverter is used as the input end of the whole delay assembly, and the output end of the last inverter is used as the output end of the whole delay assembly. The number of the phase inverters is even, and the output end of each phase inverter is connected with a grounded capacitor. The utility model discloses a set up delay assembly, can effectively avoid the adverse effect that the phase discrimination blind spot brought phase frequency detector.

Description

Phase frequency detector

Technical Field

The utility model relates to a phase-locked loop especially relates to a phase frequency detector for phase-locked loop.

Background

The Phase Frequency Detector (PFD) is a key component of the Phase-locked loop, and its main function is to detect the Phase difference and Frequency difference between the input signal and the feedback signal of the voltage-controlled oscillator and amplify them, and the performance of the PFD determines the precision and stability of the Phase-locked loop.

The circuit structure for implementing the phase detection function in the PLL includes various structures, such as an Analog Multiplier (Analog Multiplier), an exclusive or gate (XOR gate), a Flip-Flop (Flip-Flop), a Sample-and-Hold phase detector (Sample-and-Hold), and the like.

However, in the design of modern phase detectors, especially in large-scale communication and digital integrated circuits, more design goals are: the CMOS digital phase discriminator has the advantages of high speed, low power consumption, low noise, no dead zone and wide linear phase discrimination range. When small phase errors exist in the reference signal and the feedback signal, the width of the output pulse of the PFD is too narrow to open an input switching tube of a post-stage charge pump, so that the normal work of the phase-locked loop is influenced, and a phase error interval which cannot be identified by the phase detector is called as a phase detection dead zone of the phase detector.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art not enough, provide a phase frequency detector, through increasing delay assembly, can effectively avoid the adverse effect that the phase discrimination blind spot brought to phase frequency detector.

The purpose of the utility model is realized through the following technical scheme: a phase frequency detector comprises a source signal input end Ref, a feedback input end Div, a first signal output end Up, a second signal output end Dn, a delay assembly, a first NAND gate K1-a ninth NAND gate K9;

a first input end of the first nand gate K1 is connected with the source signal input end Ref, a second input end of the first nand gate K1 is connected with the output end of the second nand gate K2, and the output end of the first nand gate K1 is respectively connected with a first input end of the second nand gate K2, a first input end of the third nand gate K3 and a first input end of the ninth nand gate K9;

a second input end of the second nand gate K2 is connected to an output end of the third nand gate K3, a third input end of the second nand gate K2 is connected to an output end of the delay assembly, and an output end of the second nand gate K2 is further connected to the first signal output end Up;

a second input end of the third nand gate K3 is connected with an output end of the fourth nand gate K4, and output ends of the third nand gate K3 are further connected to a first input end of the fourth nand gate K4 and a second input end of the ninth nand gate K9, respectively; a second input of the fourth nand gate K4 is connected to the output of the delay element;

a first input end of the fifth NAND gate K5 is connected to the output end of the delay assembly, a second input end of the fifth NAND gate K5 is connected to the output end of the sixth NAND gate K6, and an output end of the fifth NAND gate K5 is connected with a first input end of the sixth NAND gate K6; a second input end of the sixth nand gate K6 is connected to the output end of the eighth nand gate K8, and output ends of the sixth nand gate K6 are further connected to a third input end of the ninth nand gate K9 and a second input end of the seventh nand gate K7, respectively;

a first input end of the seventh nand gate K7 is connected to the output end of the delay element, a third input end of the seventh nand gate K7 is connected to the output end of the eighth nand gate K8, and an output end of the seventh nand gate K7 is connected to the first input end and the second signal output end Dn of the eighth nand gate K8 respectively; a second input end of the eighth nand gate K8 is connected to the feedback input Div, and an output end of the eighth nand gate K8 is further connected to a fourth input end of the ninth nand gate K9; the output end of the ninth nand gate K9 is connected with the input end of the delay assembly.

Preferably, the delay assembly comprises a plurality of inverters connected in series in sequence, wherein an input end of a first inverter is used as an input end of the whole delay assembly, and an output end of a last inverter is used as an output end of the whole delay assembly. The number of inverters is even. The output end of each phase inverter is connected with a grounded capacitor.

The utility model has the advantages that: the utility model discloses an increase delay assembly, can effectively avoid the adverse effect that the phase discrimination blind spot brought the phase frequency detector.

Drawings

FIG. 1 is a schematic diagram of the present invention;

fig. 2 is a schematic diagram of a conventional phase frequency detector.

Detailed Description

The technical solution of the present invention is described in further detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following description.

As shown in fig. 1, a phase frequency detector includes a source signal input Ref, a feedback input Div, a first signal output Up, a second signal output Dn, a delay element, and first to ninth nand gates K1 to K9;

In an embodiment of the present application, the delay component includes a plurality of inverters connected in series in sequence, wherein an input terminal of a first inverter serves as an input terminal of the entire delay component, and an output terminal of a last inverter serves as an output terminal of the entire delay component. The number of inverters is even. The output end of each phase inverter is connected with a grounded capacitor.

As shown in fig. 2, the PFD generally consists of digital logic gates, and an and gate and two resettable D flip-flops form a tri-state phase detector. The flip-flops adopt an edge triggering mode, and when the outputs of the two flip-flops are both at a high level, the feedback signals reset the states of the flip-flops through the AND gates. The flip-flop input D is connected to the high level and the clock signal CLK is connected to the reference clock and the feedback clock, respectively. The circuit structure has a phase discrimination dead zone, and can obviously influence the loop characteristics of a phase-locked loop system, such as reference stray, locking time and the like. When small phase errors exist in the reference signal and the feedback signal, the width of the output pulse of the PFD is too narrow to open an input switch tube of a post-stage charge pump, and a phase error interval which cannot be identified by the phase detector is called as a phase detection dead zone of the phase detector. It is mainly determined by the transmission delay of the output signal and the setting signal. And if the rising delay of the output signal of the phase detector is t and the state reversal threshold voltage of the logic gate is VDD/2, the AND gate can clear the state of the trigger within t/2 time after the rising edge of the output signal arrives. When there is a large phase difference between the reference signal and the feedback signal, the output UP signal has enough time to maintain a logic high level. When the phase between the signals is reduced to a certain degree and the UP signal does not reach a logic high level, the DW rising signal reaches an AND gate, and a trigger is cleared in advance, so that the UP signal cannot be started.

In the present application, the two outputs, Up and Dn, are used to control the charge and discharge of the loop capacitance by the Charge Pump (CP). When the Up signal is high, the CP starts to charge the loop capacitor, which causes the voltage control terminal of the VCO to increase, and the VCO frequency increases accordingly. Similarly, when the Dn signal is high, the VCO frequency is tuned downward. When both Up and Dn are low, the CP output is in a high impedance state. It can be seen that when the phase difference is within ± 2 pi, the PFD operates as a phase detector; and when the phase difference is greater than +/-2 pi, the PFD works as a phase frequency detector, and meanwhile, some phase inverters are added at the reset end of the phase frequency detector to serve as delay components, so that adverse effects of a phase detection dead zone on the phase frequency detector are avoided.

Finally, it should be noted that the above is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A phase frequency detector, characterized by: the circuit comprises a source signal input end Ref, a feedback input end Div, a first signal output end Up, a second signal output end Dn, a delay assembly, and first to ninth NAND gates K1 to K9;

2. A phase frequency detector as claimed in claim 1, wherein: the delay assembly comprises a plurality of inverters which are sequentially connected in series, wherein the input end of the first inverter is used as the input end of the whole delay assembly, and the output end of the last inverter is used as the output end of the whole delay assembly.

3. A phase frequency detector as claimed in claim 2, wherein: the number of inverters is even.

4. A phase frequency detector as claimed in claim 2, wherein: the output end of each phase inverter is connected with a grounded capacitor.