CN212784189U

CN212784189U - Combined VCSEL chip

Info

Publication number: CN212784189U
Application number: CN202021218919.5U
Authority: CN
Inventors: 郭铭浩; 林珊珊; 王立; 李念宜
Original assignee: Ningbo Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co.,Ltd.
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2021-03-23
Anticipated expiration: 2030-06-28

Abstract

The application relates to a combined VCSEL chip, which comprises a first VCSEL chip, a first VCSEL chip and a second VCSEL chip, wherein the first VCSEL chip and the second VCSEL chip are arranged in a back-to-back mode, so that the laser emitting direction of the first VCSEL chip is opposite to that of the second VCSEL chip, and the first VCSEL chip and the second VCSEL chip share a negative electrode conducting layer. Thus, the combined VCSEL chip integrates different types of VCSEL chips at the structural level so as to have the advantages of different types of VCSEL chips and have relatively small thickness dimension.

Description

Combined VCSEL chip

Technical Field

The application relates to the field of VCSELs, in particular to a combined VCSEL chip.

Background

With the development of VCSEL (Vertical-Cavity Surface-Emitting Laser) technology, VCSEL chips adapted to different application scenarios, such as TOF VCSEL chips, structured light VCSEL chips, etc., are gradually emerging from the market.

Different types of chips have different characteristics, and particularly, the conventional structured light chip has the advantages of high light transmittance and low energy consumption, is easily influenced by the external environment, is only suitable for short-distance application scenes, and cannot normally work under the condition of low environment; the conventional TOF VCSEL chip has the advantages of small environmental influence and the like, but the measurement accuracy is poor, the power consumption is high, particularly, the TOF VCSEL chip with high power can generate large heat in the working process, and the performance of the chip can be greatly influenced under the condition of insufficient heat dissipation.

In practical applications, there are cases where a plurality of VCSEL chips are applied to a terminal device at the same time, for example, different types of VCSEL chips are placed on different sides of a smart phone to serve as a front VCSEL chip of a front camera module and a rear VCSEL chip of a rear camera module.

Accordingly, how to combine the advantages of different types of VCSEL chips and solve the respective defects of different types of VCSEL chips has become a very important technical problem.

Disclosure of Invention

The present application provides a combined VCSEL chip, wherein the combined VCSEL chip integrates different types of VCSEL chips at a structural level to have advantages of different types of VCSEL chips and have a relatively small thickness dimension.

Another advantage of the present application is to provide a combined VCSEL chip having an integrated, compact, unitary structure.

Another advantage of the present application is to provide a combined VCSEL chip, wherein the combined VCSEL chip can selectively activate different types of VCSEL chips based on different application scenarios to improve application scenario compatibility.

Another advantage of the present application is to provide a combined VCSEL chip, wherein each VCSEL chip in the combined VCSEL chip can be illuminated in different zones by configuring a negative conductive layer, so as to solve a heat dissipation problem of a high power chip thereof.

To achieve at least one of the above technical advantages, there is provided a combined VCSEL chip, including:

a first VCSEL chip including a plurality of first VCSEL units arranged in a first array; and

the second VCSEL chip comprises a plurality of second VCSEL units which are arranged in a second array mode, wherein the first VCSEL chip and the second VCSEL chip are arranged in a back-to-back mode, the laser emitting direction of the first VCSEL chip is opposite to the laser emitting direction of the second VCSEL chip, and the first VCSEL chip and the second VCSEL chip share a negative electrode conducting layer.

In an assembled VCSEL chip according to the present application, the negative conductive layer includes a first electrically conductive pattern electrically connected to a first subset of the plurality of first VCSEL units and a second electrically conductive pattern electrically connected to a third subset of the plurality of second VCSEL units; and the second electrically conductive pattern is electrically connected to a second subset of the plurality of first VCSEL units and to a fourth subset of the plurality of second VCSEL units.

In a combined VCSEL chip according to the present application, there are no first VCSEL units in common in the first subset and the second subset, and there are no second VCSEL units in common in the third subset and the fourth subset.

In a combined VCSEL chip according to the present application, the first subset comprises all of the first VCSEL units in the second subset, and the third subset comprises all of the second VCSEL units in the fourth subset.

In the assembled VCSEL chip according to the present application, the negative conductive layer further includes a third electrical conduction pattern electrically connected to a fifth subset of the plurality of first VCSEL units and to a seventh subset of the plurality of second VCSEL units.

In the assembled VCSEL chip according to the present application, each of the first VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having an opening, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer, wherein the first VCSEL chip has an isolation trench formed between each two of the first VCSEL units, respectively, and each isolation trench extends upward from the substrate, penetrates through the substrate and the N-type doped DBR, and is abutted to a bottom of the positive conductive layer, so that the first VCSEL units in the first VCSEL chip are electrically isolated from each other.

In the assembled VCSEL chip according to the present application, each of the second VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having an opening, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer, wherein the second VCSEL chip has an isolation trench formed between each two of the second VCSEL units, respectively, and each of the isolation trenches extends upward from the substrate, penetrates through the substrate and the N-type doped DBR, and is abutted to a bottom of the positive conductive layer, so that the second VCSEL units in the second VCSEL chip are electrically isolated from each other.

In a combined VCSEL chip according to the present application, each of the first VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having an opening, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer, and the first VCSEL chip further includes an isolation medium doped between each two of the first VCSEL units, the isolation medium extending between the substrate of the first VCSEL unit and the N-type doped DBR such that the first VCSEL units in the first VCSEL chip are electrically isolated from each other.

In the assembled VCSEL chip according to the present application, each of the second VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having an opening, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer, and the second VCSEL chip further includes an isolation medium doped between each two of the second VCSEL units, the isolation medium extending between the substrate of the second VCSEL unit and the N-type doped DBR such that the second VCSEL units in the second VCSEL chip are electrically isolated from each other.

In the combined VCSEL chip according to the present application, the first VCSEL chip and the second VCSEL chip are the same type of VCSEL chip and have different powers.

In a combined VCSEL chip according to the present application, the oxide aperture of the first VCSEL unit and the second VCSEL unit ranges from 1nm to 100um, preferably from 7.5um to 50 um.

In a combined VCSEL chip according to the present application, the first VCSEL chip and the second VCSEL chip are selected from a TOF VCSEL chip and a speckle structured light VCSEL.

In a combined VCSEL chip according to the present application, the first VCSEL chip and the second VCSEL chip are different types of VCSEL chips, wherein the first VCSEL chip is selected from the group consisting of a TOF VCSEL chip and a structured light VCSEL chip, and the second VCSEL chip is selected from the group consisting of a TOF VCSEL chip and a structured light VCSEL chip.

Further advantages and advantages of the present application will become apparent from an understanding of the ensuing description and drawings.

These and other advantages, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the claims.

Drawings

Fig. 1 illustrates a conventional schematic diagram of two VCSEL chips applied to a terminal device.

Fig. 2 illustrates another schematic diagram of a conventional application of two VCSEL chips to a terminal device.

Figure 3 illustrates a cross-sectional schematic view of a combined VCSEL chip according to an embodiment of the present application.

Figure 4 illustrates a schematic diagram of individual VCSEL units in the combined VCSEL chip, according to an embodiment of the present application.

Figure 5 illustrates a top view of the combined VCSEL chip according to an embodiment of the present application.

Figure 6 illustrates a schematic bottom view of the combined VCSEL chip according to an embodiment of the present application.

Figure 7 illustrates a cross-sectional schematic view of a combined VCSEL chip, according to another embodiment of the present application.

Figure 8 illustrates a top view of the combined VCSEL chip according to another embodiment of the present application.

Figure 9 illustrates a bottom view of the combined VCSEL chip according to another embodiment of the present application.

Figure 10 illustrates a cross-sectional schematic diagram of a modified implementation of the combined VCSEL chip, according to another embodiment of the present application.

Detailed Description

The following description is presented to disclose the application and to enable any person skilled in the art to practice the application. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The underlying principles of the application, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the application.

It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or components must be in a particular orientation, constructed and operated in a particular orientation, and thus the above terms are not to be considered limiting of the present application.

It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.

Summary of the application

As described above, in practical applications, a plurality of VCSEL chips are adopted in a terminal device, for example, in a smart phone, different types of VCSEL chips are placed on different sides of the smart phone to serve as a front VCSEL chip of a front camera module and a rear VCSEL chip of a rear camera module. Therefore, how to combine the advantages of different types of VCSEL chips and solve the respective defects of different types of VCSEL chips has become a very important technical problem.

The existing multiple VCSEL chip combinations are generally of two types: "front and back light emission" and: "same side light extraction", wherein front and back light extraction means that two VCSEL chips are arranged back to back so that the laser emission directions of the two VCSEL chips are opposite, as shown in fig. 1 and 2. Fig. 1 illustrates a conventional schematic diagram of two VCSEL chips applied to a terminal device. As shown in fig. 1, in this solution, two VCSEL chips are placed in a staggered manner and back to back, and although this solution can integrate the advantages of two VCSEL chips to a certain extent, this solution occupies an excessively large area, i.e., occupies a large volume of the terminal device, and is not in line with the current trend of miniaturization and thinning of the terminal device. Fig. 2 illustrates another schematic diagram of a conventional application of two VCSEL chips to a terminal device. As shown in fig. 2, in this solution, two VCSEL chips are aligned and arranged back to back, and although this solution can integrate the advantages of two VCSEL chips to a certain extent, the thickness dimension of this solution is still large, i.e. the occupied volume of the terminal device is still large, which is not in line with the current trend of miniaturization and thinning of the terminal device.

Accordingly, the expression "the light is emitted from the same side" means that the light emitting surfaces of the two VCSEL chips are disposed on the same plane, and obviously, the occupied area of the scheme is large, which is not consistent with the development trend of miniaturization and thinning of the current terminal device.

Moreover, through the existing technical schemes of 'light outgoing from the same side' and 'light outgoing from the front and the back', the following can be found: in existing combined VCSEL chip applications, there is no structural association between the VCSEL chips, i.e. in existing combined VCSEL chip applications, the VCSEL chips are only placed at different locations of the terminal equipment, but they are still essentially operated and controlled individually.

Also, as the power of the VCSEL chip increases, the heat dissipation problem of the VCSEL chip becomes more serious, i.e., the thermal sensitivity problem becomes more serious, and the current solution to the thermal sensitivity characteristic is mainly to change the thermal sensitivity characteristic of the VCSEL chip itself by adjusting the design of the bottom layer of the VCSEL chip, but due to the characteristic performance of the semiconductor itself, the thermal sensitivity characteristic is difficult to be substantially optimized or eliminated, i.e., the solution intelligently improves the thermal sensitivity characteristic within a certain range.

In view of the above technical problems, the basic idea of the present application is to realize integration among multiple VCSEL chips on a structural level, so that the finally formed combined VCSEL chips have the advantages of different types of VCSEL chips and have a relatively small thickness dimension.

Based on this, the present application provides a combined VCSEL chip, which includes a first VCSEL chip including a plurality of first VCSEL units arranged in a first array; and a second VCSEL chip including a plurality of second VCSEL units arranged in a second array, wherein the first VCSEL chip and the second VCSEL chip are oppositely disposed so that a laser emission direction of the first VCSEL chip is opposite to a laser emission direction of the second VCSEL chip, and the first VCSEL chip and the second VCSEL chip share a negative conductive layer. Thus, the combined VCSEL chip integrates different types of VCSEL chips at the structural level so as to have the advantages of different types of VCSEL chips and have relatively small thickness dimension.

Having described the general principles of the present application, various non-limiting embodiments of the present application will now be described with reference to the accompanying drawings.

Example 1

The inventor of the application researches the consistency of chips with different models in a structural level and provides a technical scheme for integrating the chips with different models in the structural level, so that the combined chip has multiple advantages of VCSEL chips with different types, and the combined chip has an integrated compact structure, particularly has relatively small thickness and size through optimization in the structural level, and meets the development trend of thinning of current terminal equipment. Here, in the embodiment of the present application, the different types of chips include chips of the same type but with different parameters and chips of different types, where the chips of the same type but with different parameters, for example, TOF VCSEL chips with different powers, speckle structure optical chips with different powers, and the like; different models of chips, for example, TOF VCSEL chips and speckle structured photonic chips.

The combined chip of the embodiments of the present application is described below by taking as an example that the combined chip integrates a first VCSEL chip and a second VCSEL chip, where the first VCSEL chip and the second VCSEL chip are different types of chips.

Fig. 3 illustrates a schematic diagram of a combined VCSEL chip according to an embodiment of the present application, and as shown in fig. 3, the combined chip includes a first VCSEL chip 10 and a second VCSEL chip 20, wherein the first VCSEL chip 10 and the second VCSEL chip 20 are disposed opposite to each other, so that a laser emission direction of the first VCSEL chip 10 is opposite to a laser emission direction of the second VCSEL chip 20. The first VCSEL chip 10 comprises a plurality of first VCSEL units 11 arranged in a first array and the second VCSEL chip 20 comprises a plurality of second VCSEL units 21 arranged in a second array. In particular, the first VCSEL chip 10 and the second VCSEL chip 20 share a negative conductive layer 30, in such a way that different types of VCSEL chips are integrated on a structural level.

It should be noted that in the present application, the first VCSEL chip 10 and the second VCSEL chip 20 are VCSEL chips emitting light from the front, that is, the light emitting surfaces of the first VCSEL chip 10 and the second VCSEL chip 20 are formed on the front, and the negative conductive layer 30 forms the back of the VCSEL chips 10 and 20.

In order to explain the light extraction principle of the first VCSEL chip 10 and the second VCSEL chip 20, the structures of the first VCSEL unit 11 and the second VCSEL unit 21 are explained. Fig. 4 illustrates a schematic diagram of VCSEL units in the combined VCSEL chip according to the embodiment of the present application, and as shown in fig. 4, the first and second VCSEL units 11, 21 (the first VCSEL unit 11 and the second VCSEL unit are identical in structure) include, from bottom to top, a negative electrode 09, a substrate 01, a buffer layer 02, an N-type doped DBR 03, an active region 04, a confinement layer 05, a P-type doped DBR06, an ohmic contact layer 07, and a positive electrode 08, wherein the active region 04 is sandwiched between the P-type doped DBR06 and the N-type doped DBR 03 to form a resonant cavity. It should be understood that the negative electrodes of the VCSEL units are connected to each other to form the negative conductive layer 30 of the first VCSEL chip 10 and the negative conductive layer 30 of the second VCSEL chip 20; the positive electrodes of the VCSEL units are connected to each other, forming a positive conductive layer 40 of the first VCSEL chip 10 and a positive conductive layer 40 of the second VCSEL chip 20.

In the working process, the VCSEL unit can realize laser excitation only by meeting the following two conditions: (1) particle number inversion process: under the condition that population inversion exists in the active region 04 to enable gain provided by a laser medium to exceed loss sufficiently, when current is injected through the negative electrode 09 and the positive electrode 08, light intensity continuously increases, electrons at the bottom of a conduction band in a high energy state transition to a conduction band in a low energy band, and light with specific wavelength is reflected back and forth between the P-type doped DBR06 and the N-type doped DBR 03, and the amplification process is repeated continuously, so that laser is formed; (2) a resonant cavity: the cavity resonator is mainly used for generating light in the active region 04, and forms multiple optical energy feedbacks to provide a cavity when the light is reflected back and forth between the P-type doped DBR06 and the N-type doped DBR 03, so that the stimulated radiation obtains multiple feedbacks therein to form laser oscillation. After being turned on, the laser light projected by the VCSEL unit generates a set of interference fringes in space.

It should be noted that in the embodiments of the present application, the selection of the materials of the layers of the

VCSEL units

11, 21 is not limited to the present application, for example, the substrate 01 may include, but is not limited to, a silicon substrate, a sapphire substrate, a potassium arsenide substrate, etc.; materials of the P-type doped DBR06 and the N-type doped DBR 03 include, but are not limited to: InGaAsP/InP, AlGaInAs/AlInAs, AlGaAsSb/AlAsSb, GaAs/AlGaAs, Si/MgO, and Si/Al2O3, etc.

It should be understood that, according to the normal structure configuration, the first VCSEL chip 10 and the second VCSEL chip 20 respectively have their respective negative conductive layers 30, however, in the present embodiment, since the first VCSEL chip 10 and the second VCSEL chip 20 are disposed in a back-to-back manner, that is, the negative conductive layers 30 of the first VCSEL chip 10 and the second VCSEL chip 20 are overlapped, the negative conductive layers 30 of the first VCSEL chip 10 and the second VCSEL chip 20 can be integrally shared on the structure level, that is, in the present embodiment, the combined VCSEL chip only includes one common negative conductive layer 30. It should be understood that, in this way, the thickness dimension of the combined chip can be reduced, and since the first VCSEL chip 10 and the second VCSEL chip 20 are stacked in the combined chip, the occupation area of the combined chip in the horizontal direction is relatively small, that is, both the dimension of the combined chip in the horizontal direction and the dimension of the combined chip in the thickness direction can be optimized compared to the prior art.

Figure 5 illustrates a top view of the combined VCSEL chip according to an embodiment of the present application. Figure 6 illustrates a schematic bottom view of the combined VCSEL chip according to an embodiment of the present application. As shown in fig. 5, in this example, the first VCSEL chip 10 is implemented as a TOF VCSEL chip comprising a plurality of first VCSEL units 11 arranged in a regular array; as shown in fig. 6, in this example, the second VCSEL chip 20 is implemented as a structured light VCSEL chip comprising a plurality of second VCSEL units 21 arranged in an array in a specific coding manner. That is, in this example, the first VCSEL chip 10 and the second VCSEL chip 20 are different types of VCSEL chips, so the combined chip can selectively activate the first VCSEL chip 10 and/or the second VCSEL chip 20 based on the requirements of different application scenarios, for example, in an application scenario requiring higher measurement accuracy, the second VCSEL chip 20 can be activated and the first VCSEL chip 10 can be deactivated; when the measuring distance is long, the first VCSEL chip 10 can be turned on and the second VCSEL chip 20 can be turned off.

It is worth mentioning that in this example, the first VCSEL chip 10 and the second VCSEL chip 20 may also be implemented as VCSEL chips of the same type but with different parameters (e.g. different powers), which is not limited by the present application.

During the fabrication process, the epitaxial structures of the first VCSEL chip 10 and the second VCSEL chip 20 (the epitaxial structures, including the substrate 01, the buffer layer 02, the N-type doped DBR 03, the active region 04, the confinement layer 05, the P-type doped DBR06, and the ohmic contact layer 07 as described above) may be formed by a MOCVD process (Metal-organic Chemical vapor deposition process) or other Metal growth processes; then, the epitaxial structure is processed by photolithography or other etching processes to form the mesa structures of the first VCSEL chip 10 and the second VCSEL chip 20; then, forming a positive electrode conductive layer 40 on the mesa structure by an evaporation process to obtain the first VCSEL chip 10 and the second VCSEL chip 20 without the negative electrode conductive layer 30; then, the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30 are disposed to face away from each other, and then the negative conductive layer 30 is formed between the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30 through a metal growth process to integrate the first VCSEL chip 10 and the second VCSEL chip 20 at a structural level through the negative conductive layer 30.

It should be noted that, as those skilled in the art will know, in the VCSEL field, there are also VCSEL chips with back light emission (i.e. light emission surface is formed on the back of the VCSEL chips), accordingly, based on the inventive concept of the present application, the first VCSEL chip 10 and the second VCSEL chip 20 with back light emission can be similarly arranged in a back-to-back manner, so that the laser emission direction of the first VCSEL chip 10 is opposite to the laser emission direction of the second VCSEL chip 20, and, on the structural level, the first VCSEL chip 10 and the second VCSEL chip 20 share the positive conductive layer 40, that is, the first VCSEL chip 10 and the second VCSEL chip 20 are integrated on the structural level through the shared positive conductive layer 40.

In summary, the combined VCSEL chip according to the embodiments of the present application is illustrated, which integrates different types of VCSEL chips at a structural level to have the advantages of different types of VCSEL chips and have a relatively small thickness dimension.

Example 2

As shown in fig. 7, a combined VCSEL chip based on another embodiment of the present application is illustrated, wherein the combined VCSEL chip illustrated in embodiment 2 is further optimized on a structural level compared to embodiment 1 to solve the technical problem of heat dissipation of the high-power VCSEL chip.

As shown in fig. 7, in the embodiment of the present application, the first VCSEL chip 10 and the second VCSEL chip 20 still share the negative conductive layer 30 at the structural level. In order to solve the problem of heat dissipation, an electric connection scheme of 'subarea lighting' is adopted. Specifically, as shown in fig. 7 to 9, in the present embodiment, the negative conductive layer 30 includes a first electrical conduction pattern 31 and a second electrical conduction pattern 32, and the first electrical conduction pattern 31 is electrically connected to a first subset of the plurality of first VCSEL units 11 and to a third subset of the plurality of second VCSEL units 21; and, the second electrically conductive pattern 32 is electrically connected to the second subset of the plurality of first VCSEL units 11 and to the fourth subset of the plurality of second VCSEL units 21.

In particular, the first subset and the second subset, and the third subset and the fourth subset, have two relationships: the first VCSEL unit 11 is not common in the first subset and the second subset, and the second VCSEL unit 21 is not common in the third subset and the fourth subset; alternatively, the first subset comprises all of the first VCSEL units 11 in the second subset, and the third subset comprises all of the second VCSEL units 21 in the fourth subset. I.e. either there is no intersection between the first subset and the second subset and no intersection between the third subset and the fourth subset, or the first subset comprises the second subset in its entirety and the third subset comprises the fourth subset in its entirety.

Of course, in other examples of the present application, the negative conductive layer 30 may further include more electrical conduction patterns to divide the first VCSEL chip 10 and the second VCSEL chip 20 into more regions, for example, the negative conductive layer 30 may further include a third electrical conduction pattern 33, and the third electrical conduction pattern 33 is electrically connected to a fifth subset of the plurality of first VCSEL units 11 and to a seventh subset of the plurality of second VCSEL units 21.

It should be understood that the first VCSEL chip 10 and the second VCSEL chip 20 can be divided into different regions by the negative conductive layer 30, that is, the first VCSEL chip 10 and the second VCSEL chip 20 can be lighted in different regions, so that the combined VCSEL chip can selectively adjust the number of VCSEL units actually operating in the first VCSEL chip 10 and the second VCSEL chip 20 based on the requirements of the actual application scenario, so as to reduce power consumption and solve the problem of heat dissipation.

It should be understood that, since the negative conductive layer 30 is formed on the back of the first VCSEL chip 10 and the second VCSEL chip 20, no matter how complicated the wiring and routing structure of the negative conductive layer 30 is, the normal light emission of the first VCSEL chip 10 and the second VCSEL chip 20 is not affected.

Also, for the technical purpose of "zone lighting", the plurality of first VCSEL units 11 in the first VCSEL chip 10 and the plurality of second VCSEL units 21 in the second VCSEL chip 20 should be electrically isolated from each other. As shown in fig. 7, in this example, the first VCSEL chip 10 has an isolation trench 100 respectively formed between every two first VCSEL units 11, and each isolation trench 100 respectively extends upward from the substrate 01 and penetrates through the substrate 01 and the N-type doped DBR 03 and abuts against the bottom of the positive conductive layer 40, so as to electrically isolate the first VCSEL units 11 in the first VCSEL chip 10 from each other; accordingly, the second VCSEL chip 20 has an isolation trench 100 respectively formed between every two second VCSEL units 21, and each isolation trench 100 extends upward from the substrate 01 and penetrates through the substrate 01 and the N-type doped DBR 03 and abuts against the bottom of the positive conductive layer 40, so as to electrically isolate the second VCSEL units 21 in the second VCSEL chip 20 from each other.

In the preparation process, the combined chip may be prepared by a preparation process, which first includes preparing the first VCSEL chip 10 and the second VCSEL chip 20 excluding the negative conductive layer 30, the process including: firstly, forming an epitaxial structure, wherein the epitaxial structure sequentially comprises a substrate 01, an N-type doped DBR 03, an active region 04, a limiting layer 05, a P-type doped DBR06 and an ohmic contact layer 07 from bottom to top; note that a plurality of mesa structures are formed on the epitaxial structure by an etching process, each of the mesa structures including, from bottom to top, the active region 04, the confinement layer 05, the P-type doped DBR06, and the ohmic contact layer 07, wherein the ohmic contact layer 07 includes a top electrical contact region formed on an upper surface thereof; then, oxidizing the confinement layer 05 of each of the mesa structures by an oxidation process so that the confinement layer 05 has an opening with a specific aperture; next, depositing a dielectric insulating layer on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate, the bottom region of the mesa structure, and the other regions of the ohmic contact layer 07 except the top electrical contact region; then, a positive electrode conductive layer 40 is formed on the upper surface of the ohmic contact layer 07; then, the substrate 01 and the N-type doped DBR 03 are etched to form an isolation trench 100 between each two mesa structures, so as to form a plurality of VCSEL units separately through the isolation trench 100, wherein the isolation trench 100 extends upward from the substrate 01 and penetrates through the substrate 01 and the N-type doped DBR 03 and abuts against the bottom of the positive conductive layer 40.

After the first VCSEL chip 10 and the second VCSEL chip 20 not including the negative conductive layer 30 are formed, the negative conductive layer 30 is further formed between the first VCSEL chip 10 and the second VCSEL chip 20 to integrate the first VCSEL chip 10 and the second VCSEL chip 20 on a structural layer through the negative conductive layer 30.

Of course, in other examples of the present application, the electrical isolation between the plurality of first VCSEL units 11 in the first VCSEL chip 10 and the plurality of second VCSEL units 21 in the second VCSEL chip 20 can be implemented in other manners. Figure 10 illustrates a cross-sectional schematic diagram of a modified implementation of the combined VCSEL chip, according to another embodiment of the present application. As shown in fig. 10, in this modified embodiment, the first VCSEL chip 10 further includes an isolation medium doped between each two first VCSEL units 11, the isolation medium extends between the substrate of the first VCSEL units 11 and the N-type doped DBR, so that the first VCSEL units 11 in the first VCSEL chip 10 are electrically isolated from each other; the second VCSEL chip 20 further includes an isolation medium 100A doped between each two of the second VCSEL units 21, wherein the isolation medium 100A extends between the substrate of the second VCSEL units 21 and the N-type doped DBR, so as to electrically isolate the second VCSEL units 21 in the second VCSEL chip 20 from each other. In particular, the isolation medium 100A is selected from any one or combination of high-energy implantation doping of H, He, C, O and N, energy MeV level and dosage 10^11-15。

In the preparation process, the combined chip may be prepared by a preparation process, which first includes preparing the first VCSEL chip 10 and the second VCSEL chip 20 excluding the negative conductive layer 30, the process including: firstly, an epitaxial structure is formed, and the epitaxial structure sequentially comprises a substrate 01, an N-type doped DBR 03, an active region 04, a limiting layer 05, a P-type doped DBR06 and an ohmic contact layer 07 from bottom to top; then, forming a plurality of mesa structures on the epitaxial structure through an etching process, each of the mesa structures including, from bottom to top, the active region 04, the confinement layer 05, the P-type doped DBR06, and the ohmic contact layer 07, wherein the ohmic contact layer 07 includes a top electrical contact region formed on an upper surface thereof; then, oxidizing the limiting layer 05 of each mesa structure through an oxidation process so that the limiting layer 05 has an opening with a specific aperture; then, an isolation medium 100A is implanted between every two of the mesa structures, wherein the isolation medium 100A is formed on the substrate 01 and the N-type doped DBR 03 in a doped manner; then, depositing a dielectric insulating layer on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate 01, the bottom region of the mesa structure, and the other regions of the ohmic contact layer 07 except the top electrical contact region; next, a positive conductive layer 40 is formed on the upper surface of the ohmic contact layer 07, wherein the positive conductive layer 40 is electrically connected to the top electrical contact regions of all the mesa structures.

Also, in the embodiment of the present application, the first VCSEL chip 10 and the second VCSEL chip 20 are also different types of chips, which include different types of chips and different types of chips, for example, the first VCSEL chip 10 and the second VCSEL chip 20 are the same type of VCSEL chips and have different powers, or the first VCSEL chip 10 is a TOF VCSEL chip and the second VCSEL chip 20 is a structured light VCSEL chip.

In summary, the combined VCSEL chip according to the embodiments of the present application is illustrated, which integrates different types of VCSEL chips at a structural level to have advantages of different types of VCSEL chips and have a relatively small thickness dimension.

The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.

The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".

It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for the purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.

Claims

1. A combined VCSEL chip, comprising:

2. The assembled VCSEL chip of claim 1, wherein the negative conductive layer comprises a first electrically conductive pattern and a second electrically conductive pattern, the first electrically conductive pattern being electrically connected to a first subset of the plurality of first VCSEL units and to a third subset of the plurality of second VCSEL units; and the second electrically conductive pattern is electrically connected to a second subset of the plurality of first VCSEL units and to a fourth subset of the plurality of second VCSEL units.

3. The combined VCSEL chip of claim 2, wherein the first VCSEL unit is not common in the first subset and the second subset, and the second VCSEL unit is not common in the third subset and the fourth subset.

4. The assembled VCSEL chip of claim 2, wherein the first subset comprises all of the first VCSEL cells in the second subset, and the third subset comprises all of the second VCSEL cells in the fourth subset.

5. The assembled VCSEL chip of claim 3 or 4, wherein the negative conductive layer further comprises a third electrically conductive pattern electrically connected to a fifth subset of the plurality of first VCSEL units and to a seventh subset of the plurality of second VCSEL units.

6. The assembled VCSEL chip of claim 1, wherein each of the first VCSEL units comprises, from bottom to top, a substrate, an N-doped DBR, an active region, a confinement layer having an opening, a P-doped DBR, an ohmic contact layer, and a positive conductive layer, wherein the first VCSEL chip has an isolation trench formed between each two of the first VCSEL units, each isolation trench extending upward from the substrate, penetrating the substrate and the N-doped DBR, and abutting a bottom of the positive conductive layer, such that the first VCSEL units in the first VCSEL chip are electrically isolated from each other.

7. The assembled VCSEL chip of claim 1, wherein each of the second VCSEL units comprises, from bottom to top, a substrate, an N-doped DBR, an active region, a confinement layer having an opening, a P-doped DBR, an ohmic contact layer, and a positive conductive layer, wherein the second VCSEL chip has an isolation trench formed between each of the second VCSEL units, each isolation trench extending upward from the substrate and through the substrate and the N-doped DBR and reaching a bottom of the positive conductive layer, respectively, such that the second VCSEL units in the second VCSEL chip are electrically isolated from each other.

8. The assembled VCSEL chip of claim 1, wherein each of the first VCSEL units comprises, from bottom to top, a substrate, an N-doped DBR, an active region, a confinement layer having an opening, a P-doped DBR, an ohmic contact layer, and a positive conductive layer, the first VCSEL chip further comprising an isolation medium doped between each two of the first VCSEL units, the isolation medium extending between the substrate of the first VCSEL units and the N-doped DBR such that the first VCSEL units in the first VCSEL chip are electrically isolated from each other.

9. The assembled VCSEL chip of claim 1, wherein each of the second VCSEL units comprises, from bottom to top, a substrate, an N-doped DBR, an active region, a confinement layer having an opening, a P-doped DBR, an ohmic contact layer, and a positive conductive layer, the second VCSEL chip further comprising an isolation medium doped between each two of the second VCSEL units, the isolation medium extending between the substrate and the N-doped DBR of the second VCSEL units to electrically isolate the second VCSEL units in the second VCSEL chip from each other.

10. The assembled VCSEL chip of claim 1, wherein the first VCSEL chip and the second VCSEL chip are the same type of VCSEL chip and have different powers.

11. The assembled VCSEL chip of claim 10, wherein the first VCSEL chip and the second VCSEL chip are selected from the group consisting of a TOF VCSEL chip, an encoded structure light VCSEL chip, and a speckle structure light VCSEL chip.

12. The assembled VCSEL chip of claim 1, wherein the first VCSEL chip and the second VCSEL chip are different types of VCSEL chips, wherein the first VCSEL chip is selected from the group consisting of a TOF VCSEL chip, a coded structure light VCSEL chip, and a speckle structure light VCSEL chip, and wherein the second VCSEL chip is selected from the group consisting of a TOF VCSEL chip, a coded structure light VCSEL chip, and a speckle structure light VCSEL chip.