CN212781608U - Display substrate, liquid crystal display panel and display device - Google Patents
Display substrate, liquid crystal display panel and display device Download PDFInfo
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- CN212781608U CN212781608U CN202021829249.0U CN202021829249U CN212781608U CN 212781608 U CN212781608 U CN 212781608U CN 202021829249 U CN202021829249 U CN 202021829249U CN 212781608 U CN212781608 U CN 212781608U
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Abstract
The utility model provides a display substrate, liquid crystal display panel and display device to improve prior art's liquid crystal display panel, when adopting bow-shaped data line to drive, can have marginal pixel and the inside pixel luminance of display area to have the problem of difference. The display substrate is provided with a display area and a non-display area surrounding the display area, and comprises: the pixel structure comprises a substrate, a plurality of sub-pixels, grid lines and arched data lines, wherein the sub-pixels are arranged on one side of the substrate in an array mode, the grid lines are arranged between adjacent sub-pixel rows, and the data lines extend along a first direction in a main body direction; the data line at the edge of the display area comprises a convex part bent to the non-display area; the grid line layer is provided with a compensation part, and the orthographic projection of the compensation part on the substrate is overlapped with the orthographic projection of the projection part on the substrate to form a compensation capacitor.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a display substrate, liquid crystal display panel and display device.
Background
Flat panel displays (F1at panel 1 Disp1ay, FPD) have become the mainstream products in the market, and the types of flat panel displays are increasing, such as Liquid crystal displays (Liquid crystal displays 1 Disp1ay, LCD), Organic Light Emitting Diode (OLED) displays, plasma Display panels (P1asma Disp1ay panel 1, PDP), and Field Emission Displays (FED).
When the liquid crystal display panel in the prior art is driven by adopting the arc-shaped data lines, the problem that the brightness of the edge pixels is different from that of the pixels in the display area exists.
SUMMERY OF THE UTILITY MODEL
The utility model provides a display substrate, liquid crystal display panel and display device to improve prior art's liquid crystal display panel, when adopting bow-shaped data line to drive, can have marginal pixel and the inside pixel luminance of display area to have the problem of difference.
An embodiment of the utility model provides a display substrate has the display area and surrounds the non-display area of display area, display substrate includes: the pixel structure comprises a substrate, a plurality of sub-pixels, grid lines and arched data lines, wherein the sub-pixels are arranged on one side of the substrate in an array mode, the grid lines are arranged between adjacent sub-pixel rows, and the data lines extend along a first direction in a main body direction;
the data line at the edge of the display area comprises a convex part bent to the non-display area; the grid line layer is provided with a compensation part, and the orthographic projection of the compensation part on the substrate is overlapped with the orthographic projection of the projection part on the substrate to form a compensation capacitor.
In one possible implementation, a gate line group is arranged between every two adjacent sub-pixel rows, and the gate line group comprises a first gate line and a second gate line which are sequentially arranged along the first direction;
for any sub-pixel row, the compensation section includes: a first compensation section and a second compensation section; the first compensation part is connected to the first grid line between the current sub-pixel row and the next sub-pixel row and extends towards one side of the projection part; the second compensation part is connected to the second gate line between the current sub-pixel row and the previous sub-pixel row and extends towards one side of the protrusion part.
In one possible embodiment, the area of the first compensation portion is equal to the area of the gate electrode connected to the first gate line in the display region;
the area of the second compensation part is equal to the area of the grid electrode connected with the second grid line in the display area.
In one possible embodiment, the first compensation part has the same shape as a gate electrode to which the first gate line is connected in the display region;
the shape of the second compensation part is the same as that of a gate electrode connected with the second gate line in the display region.
In one possible embodiment, a width of the first compensation portion in a direction perpendicular to the first direction is larger than a width of the data line in the direction perpendicular to the first direction;
the width of the second compensation portion in the direction perpendicular to the first direction is larger than the width of the data line in the direction perpendicular to the first direction.
In one possible embodiment, each of the arcuate data lines includes a plurality of sequentially connected arcuate portions, each of the arcuate portions includes a first portion located between two adjacent sub-pixels in the current sub-pixel row, a second portion located between two adjacent sub-pixels in the next sub-pixel row, and a third portion located between the current sub-pixel row and the next sub-pixel row and connecting the first portion and the second portion across two sub-pixels;
both sides of the first sub-part of the data line in the display area are respectively electrically connected with the sub-pixels through transistors, and both sides of the second sub-part of the data line in the display area are respectively electrically connected with the sub-pixels through transistors; the data lines at the edge of the display area are only positioned at two sides of the first part of the display area or the second part of the display area are respectively connected with the sub-pixels through transistors.
In one possible embodiment, the two sub-pixels electrically connected to the first sub-portion are respectively electrically connected to different gate line groups; the two sub-pixels electrically connected to the second sub-portion are electrically connected to different gate line groups respectively.
In a possible implementation manner, each sub-pixel row comprises a plurality of first sub-pixel groups, second sub-pixel groups and third sub-pixel groups which are circularly and sequentially arranged; the first sub-pixel group, the second sub-pixel group and the third sub-pixel group are provided with a first color sub-pixel, a second color sub-pixel and a third color sub-pixel which are sequentially arranged;
the data lines in the display area comprise a plurality of data line groups which are circularly arranged, and each data line group comprises a first type of data line, a second type of data line and a third type of data line;
the first sub-pixel group of the first sub-pixel row is electrically connected with the first color sub-pixel of the first sub-pixel group and the second color sub-pixel of the second sub-pixel group through a transistor, and the second sub-pixel group of the first sub-pixel row is electrically connected with the first color sub-pixel of the second sub-pixel group through a transistor;
the first sub-pixel group of the second sub-pixel row is electrically connected with the first sub-pixel group of the first sub-pixel group and the second sub-pixel group of the second sub-pixel row through a transistor;
the first sub-pixel in the third sub-pixel group of the current sub-pixel row is electrically connected with the first color sub-pixel and the second color sub-pixel through a transistor, and the second sub-pixel in the second sub-pixel group of the next sub-pixel row is electrically connected with the second color sub-pixel and the third color sub-pixel through a transistor.
In one possible embodiment, the third color sub-pixel electrically connected to the first sub-portion of the first type data line is electrically connected to the first gate line between the current sub-pixel row and the next sub-pixel row, the first color sub-pixel electrically connected with the first sub-part of the first type data line is electrically connected with the second grid line between the current sub-pixel row and the previous sub-pixel row through the transistor, the first color sub-pixel electrically connected with the second division part in the first type data line is electrically connected with the second grid line between the current sub-pixel row and the next sub-pixel row through the transistor, the second color sub-pixel electrically connected with the second part in the first type data line is electrically connected with the first grid line between the next sub-pixel row and the next sub-pixel row through the transistor;
the second color sub-pixel electrically connected with the first part in the second type data line is electrically connected with the first grid line between the current sub-pixel row and the next sub-pixel row through the transistor, the third color sub-pixel electrically connected with the first part in the second type data line is electrically connected with the second grid line between the current sub-pixel row and the previous sub-pixel row through the transistor, the third color sub-pixel electrically connected with the second part in the second type data line is electrically connected with the first grid line between the next sub-pixel row and the next sub-pixel row through the transistor, and the first color sub-pixel electrically connected with the second part in the second type data line is electrically connected with the second grid line between the current sub-pixel row and the next sub-pixel row through the transistor;
the first color sub-pixel electrically connected with the first division part in the third type data line is electrically connected with the second grid line between the current sub-pixel row and the previous sub-pixel row through the transistor, the second color sub-pixel electrically connected with the first division part in the third type data line is electrically connected with the first grid line between the current sub-pixel row and the next sub-pixel row through the transistor, the second color sub-pixel electrically connected with the second division part in the third type data line is electrically connected with the first grid line between the next sub-pixel row and the next sub-pixel row through the transistor, and the third color sub-pixel electrically connected with the second division part in the third type data line is electrically connected with the second grid line between the current sub-pixel row and the next sub-pixel row through the transistor.
In a possible implementation manner, the display substrate further includes a touch signal line, and the touch signal line is in an arc shape and is located at a gap between two rows of sub-pixels between two adjacent data lines.
In a possible implementation manner, an orthographic projection of the compensation part on the substrate base plate and an orthographic projection of the touch signal line on the substrate base plate do not overlap.
The utility model also provides a liquid crystal display panel, include if the utility model provides a display substrate.
The utility model also provides a display device, include if the utility model provides a liquid crystal display panel.
The embodiment of the application has the following beneficial effects: the display substrate provided by the embodiment of the application, for the protruding portion of the data line bent to the non-display area, the compensation portion capable of overlapping with the protruding portion is arranged on the layer where the gate line is located, so that the protruding portion of the data line located in the non-display area and the compensation portion can form a compensation capacitor, thereby avoiding the problem that the display substrate in the prior art is different in brightness due to the fact that when the display substrate is driven by the zigzag data line, the data line is bent to the non-display area partially, but the non-display area is not provided with the sub-pixel, and the part of the data line bent to the non-display area is not electrically connected with the transistor, compared with the data line which is entirely located in the display area in the direction perpendicular to the first direction, the number of the transistors connected by the data line at the edge is reduced, the formed overlapping capacitor is lower, when the pixels in the same row are charged, the signal delay amount which can be generated is different, and the charging, the display substrate provided by the embodiment of the application can solve the problems that the pixel at the edge position is insufficiently charged due to the fact that part of the data line is located in the non-display area, and the pixel brightness of the pixel at the edge is different from that of the pixel in the display area; moreover, the main reason for the difference between the overlap capacitance (Cdg) at the edge of the display area and the overlap capacitance (Cdg) inside the display area is that the transistor is not disposed at the edge portion, that is, the overlap capacitance generated by the gate and the data line of the transistor is lacked.
Drawings
Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present invention;
FIG. 2 is a schematic view of a portion of the film layer on the left side of FIG. 1at the position having the convex portion E;
FIG. 3 is a schematic view of a portion of the enlarged film layer at the position having the convex portion E on the right side of FIG. 1;
fig. 4 is a schematic structural diagram of a data line provided in an embodiment of the present invention;
fig. 5 is a schematic connection diagram between different structures of a display substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display substrate including a touch signal line 4 according to an embodiment of the present invention;
FIG. 7 is a schematic view of the left side of FIG. 6 with a partially enlarged film layer at the location of the bulge E;
FIG. 8 is a schematic view of the right side of FIG. 6 with a partially enlarged film layer at the location of the bulge E;
fig. 9 is a schematic diagram illustrating a distribution of brightness and darkness of a driving architecture in a frame according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of known functions and known components have been omitted from the present disclosure.
Referring to fig. 1, fig. 2 and fig. 3, wherein fig. 2 is a schematic view of a partial film layer of fig. 1 having a protrusion position on the left side, and fig. 3 is a schematic view of a partial film layer of fig. 1 having a protrusion position on the right side, embodiments of the present invention provide a display substrate having a display area AA and a non-display area BB surrounding the display area AA, the display substrate including: the liquid crystal display panel comprises a substrate, a plurality of sub-pixels 1 arranged in an array manner and positioned on one side of the substrate, a grid line 2 positioned between adjacent sub-pixel rows, and a data line 3 which extends along a first direction OO' in a main body direction and is in an arc shape;
the data line 3 at the edge of the display area AA includes a protrusion E bent to the non-display area BB; the layer where the grid line 2 is located is provided with a compensation part F, and the orthographic projection of the compensation part F on the substrate is overlapped with the orthographic projection of the bulge E on the substrate to form a compensation capacitor. Specifically, for example, the display substrate is a regular rectangle as shown in fig. 1, the Data line 3 at the edge of the display area AA may be the leftmost Data line 3 (i.e. the first Data line Data1) in fig. 1, or may be the rightmost Data line 3 (i.e. the seventh Data line Data7) in fig. 1, and since the Data line 3 is an arc, in a direction perpendicular to the first direction OO', there is a protrusion E bent to the non-display area BB, then, as shown in fig. 2 (fig. 2 is a schematic view of a partial film layer at the position of the protruding portion E on the left side of fig. 1, and two figures on the right side of fig. 2 are respectively schematic views of an enlarged structure at the position of two dashed boxes on the left side of fig. 2), for the leftmost data line 3, a compensation portion F may be disposed on the layer of the gate line 2, so that the convex portion E of the data line 3 bent to the non-display area BB overlaps with the compensation portion F to form a compensation capacitor; as shown in fig. 3 (fig. 3 is a schematic view of a partial film layer at the position of the protruding portion E on the right side of fig. 1, and two diagrams on the right side of fig. 3 are respectively schematic views of an enlarged structure at the positions of two dashed boxes in the left side of fig. 3), the data line 3 on the rightmost side may have a compensation portion F on the layer of the gate line 2, so that the protruding portion E of the data line 3 bent to the non-display area BB overlaps with the compensation portion F to form a compensation capacitor. It should be noted that fig. 1 is a schematic illustration only by taking the display substrate having 4 rows and 12 columns of sub-pixels, 8 gate lines, and 7 data lines as an example, in a specific implementation, the display substrate may have other numbers of rows and columns of sub-pixels, and other numbers of gate lines and other numbers of data lines, which is not limited by the present invention.
The display substrate provided by the embodiment of the application, for the protruding portion of the data line bent to the non-display area, the compensation portion capable of overlapping with the protruding portion is arranged on the layer where the gate line is located, so that the protruding portion of the data line located in the non-display area and the compensation portion can form a compensation capacitor, thereby avoiding the problem that the display substrate in the prior art is different in brightness due to the fact that when the display substrate is driven by the zigzag data line, the data line is bent to the non-display area partially, but the non-display area is not provided with the sub-pixel, and the part of the data line bent to the non-display area is not electrically connected with the transistor, compared with the data line which is entirely located in the display area in the direction perpendicular to the first direction, the number of the transistors connected by the data line at the edge is reduced, the formed overlapping capacitor is lower, when the pixels in the same row are charged, the signal delay amount which can be generated is different, and the charging, the display substrate provided by the embodiment of the application can solve the problems that the pixel at the edge position is insufficiently charged due to the fact that part of the data line is located in the non-display area, and the pixel brightness of the pixel at the edge is different from that of the pixel in the display area; in addition, because the display area edge lacks the overlap capacitance generated by the grid electrode of the transistor and the data line, in the embodiment of the application, the compensation part is arranged on the layer where the grid line is positioned, but the compensation part is arranged on other film layers, so that the more accurate compensation of the difference of the overlap capacitance at the display area edge and in the display can be realized.
In specific implementation, referring to fig. 1, a gate line group is provided between each adjacent sub-pixel row, and the gate line group includes a first gate line 21 and a second gate line 22 that are sequentially arranged along a first direction, that is, for any sub-pixel row, the second gate line 22 (compared to the first gate line 21 in the same gate line group) in the gate line group above the sub-pixel row is closer to the sub-pixel row, and the first gate line 21 (compared to the second gate line 22 in the same gate line group) in the gate line group below the sub-pixel row is closer to the sub-pixel row;
for any sub-pixel row, as shown in fig. 2 or 3, the compensation unit F includes: a first compensation section F1 and a second compensation section F2; the first compensation part F1 is connected to the first gate line 21 between the current sub-pixel row and the next sub-pixel row, and extends toward the protrusion E side; the second compensation part F2 is connected to the second gate line 22 between the current sub-pixel row and the previous sub-pixel row and extends toward the protrusion E side, so that the compensation part can be formed through the same composition process when the gate line is formed, and the arrangement positions of the first compensation part F1 and the second compensation part F2 are the same as the arrangement position of the gate line layer at the position where the transistor is arranged inside the display region, thereby realizing accurate elimination of the overlapping capacitance difference between the data line at the edge and the data line inside the display region.
In specific implementation, the area of the first compensation portion F1 is equal to the area of the gate connected to the first gate line 21 in the display area AA; the area of the second compensation portion F2 is equal to the area of the gate electrode to which the second gate line 22 is connected in the display area AA. Further, the shape of the first compensation portion F1 is the same as the shape of the gate electrode to which the first gate line 21 is connected in the display area AA; the shape of the second compensation portion F2 is the same as the shape of the gate connected to the second gate line 22 in the display area AA, so that the overlap capacitance generated by the data line 3 at the edge of the display area and the first compensation portion F1 is the same as the overlap capacitance generated by the data line 3 and the gate in the display area AA.
In specific implementation, referring to fig. 2 or 3, the width h1 of the first compensation part F1 perpendicular to the first direction OO 'is greater than the width h of the data line 3 perpendicular to the first direction OO'; the width h2 of the second compensation part F2 in the direction perpendicular to the first direction is greater than the width h of the data line 3 in the direction perpendicular to the first direction.
In a specific implementation, as shown in fig. 4 and 5, each of the arcuate Data lines 3 includes a plurality of sequentially connected arcuate portions 30, each of the arcuate portions 30 includes a first branch portion 31 located between two adjacent sub-pixels in the current sub-pixel row, a second branch portion 32 located between two adjacent sub-pixels in the next sub-pixel row, and a third branch portion 33 located between the current sub-pixel row and the next sub-pixel row and connecting the first branch portion 31 and the second branch portion 32 across two sub-pixels, two adjacent arcuate portions 30 of the same Data line 3 may be connected by a fourth branch portion 34, for example, as shown in fig. 5 Data2, two segments of arcuate portions 30 connected to each other are included in the first direction OO' for the second Data line 2, and for the arcuate portion 30 located above, including the first branch portion 31 located between two adjacent sub-pixels in the first row of sub-pixels S1, the second branch portion 32 located between two adjacent sub-pixels in the second row of sub-pixels S2, and a third section 33 located between the first row of sub-pixels S1 and the second row of sub-pixels S2, spanning the width of two sub-pixels and connecting the first section 31 and the second section 32;
both sides of the first sub-part 31 of the data line 5 in the display area AA are electrically connected with sub-pixels through transistors respectively, and both sides of the second sub-part 32 are electrically connected with sub-pixels through transistors respectively; the display area edge data lines are only located at two sides of the first subsection 31 or the second subsection 32 of the display area AA and are respectively connected with the sub-pixels through transistors. For example, as shown in fig. 5, when the first subsection 31 of the leftmost first Data line Data1 is located in the display area AA, sub-pixels are connected to both sides of the first subsection 31 located in the display area AA through transistors; on the other hand, when the second section 32 of the seventh Data line Data7 on the rightmost side is located in the display area AA, the sub-pixels are connected to both sides of the second section 32 located in the display area AA through the transistors.
In specific implementation, as shown in fig. 1 or fig. 5, two sub-pixels electrically connected to the first sub-portion 31 are electrically connected to different gate line groups respectively; the two sub-pixels electrically connected to the second sub-portion 32 are electrically connected to different gate line groups, respectively.
In a specific implementation, as shown in fig. 5, each sub-pixel row includes a plurality of first sub-pixel group Z1, second sub-pixel group Z2, and third sub-pixel group Z3 arranged in a cyclic sequence; the first sub-pixel group Z1, the second sub-pixel group Z2 and the third sub-pixel group Z3 are respectively provided with a first color sub-pixel R, a second color sub-pixel G and a third color sub-pixel B which are sequentially arranged;
the data lines 3 in the display region include a plurality of data line groups D arranged in a circle, each of the data line groups D including a first type data line D1, a second type data line D2, and a third type data line D3;
the first section 31 of the first-type Data line D1 (e.g., the second Data line Data2 from the left in fig. 5) is located between the first sub-pixel group Z1 and the second sub-pixel group Z2 of the current sub-pixel row (the sub-pixel row where the first section 31 is located, e.g., the first row sub-pixel S1 in fig. 5) and electrically connects the third color sub-pixel B of the first sub-pixel group Z1 and the first color sub-pixel R of the second sub-pixel group Z2 via a transistor, and the second section 32 is located between the first color sub-pixel R and the second color sub-pixel G of the first sub-pixel group Z1 of the next sub-pixel row (e.g., the second row sub-pixel S2 in fig. 5) and electrically connects the first color sub-pixel R and the second color sub-pixel G via a transistor;
the first subsection 31 of the second-type Data line D2 (e.g., the third Data line Data3 from the left in fig. 5) is located between the second color sub-pixel G and the third color sub-pixel B in the second sub-pixel group Z2 of the current sub-pixel row (e.g., the first row sub-pixel S1 in fig. 5) and is electrically connected to the second color sub-pixel G and the third color sub-pixel B through a transistor, respectively, and the second subsection 32 is located between the first sub-pixel group Z1 and the second sub-pixel group Z2 of the next sub-pixel row (e.g., the second row sub-pixel S2 in fig. 5) and is electrically connected to the third color sub-pixel B of the first sub-pixel group Z1 and the first color sub-pixel R of the second sub-pixel group Z2 through a transistor, respectively;
the first sub-section 31 of the third type Data line D3 (e.g., the fourth Data line Data4 from the left in fig. 5) is located between the first color sub-pixel R and the second color sub-pixel G in the third sub-pixel group Z3 of the current sub-pixel row (e.g., the first row sub-pixel S1 in fig. 5) and is electrically connected to the first color sub-pixel R and the second color sub-pixel G, respectively, via a transistor, and the second sub-section 32 is located between the second color sub-pixel G and the third color sub-pixel B in the second sub-pixel group Z2 of the next sub-pixel row (e.g., the second row sub-pixel S2 in fig. 5) and is electrically connected to the second color sub-pixel G and the third color sub-pixel B, respectively, via a transistor.
In specific implementation, referring to fig. 5, the third color sub-pixel B electrically connected to the first sub-portion 31 in the first-type data line D1 is electrically connected to the first gate line 21 between the current sub-pixel row (e.g., the first row sub-pixel S1 in fig. 5) and the next sub-pixel row (e.g., the second row sub-pixel S2 in fig. 5), the first color sub-pixel R electrically connected to the first sub-portion 31 in the first-type data line D1 is electrically connected to the second gate line 22 between the current sub-pixel row (e.g., the first row sub-pixel S1 in fig. 5) and the previous sub-pixel row (e.g., the sub-pixel row above the first row sub-pixel S1 in fig. 5, not shown in fig. 5) through a transistor, the first color sub-pixel R electrically connected to the second sub-portion 32 in the first-type data line D1 is electrically connected to the current sub-pixel row (e.g., the first row sub-pixel S1 in fig. 5) and the next sub-pixel row (e.g., second row sub-pixels S2 in fig. 5), and second color sub-pixels G electrically connected to the second partition 32 in the first type data line D1 are electrically connected to the first gate line 21 between the next sub-pixel row (e.g., the second row sub-pixels S2 in fig. 5) and the next sub-pixel row (e.g., the third row sub-pixels S3 in fig. 5) through transistors;
the second color sub-pixel G electrically connected to the first segment 31 in the second type data line D2 is electrically connected to the first gate line 21 between the current sub-pixel row (e.g., the first row sub-pixel S1 in fig. 5) and the next sub-pixel row (e.g., the second row sub-pixel S2 in fig. 5) through a transistor, the third color sub-pixel B electrically connected to the first segment 31 in the second type data line D2 is electrically connected to the second gate line 22 between the current sub-pixel row (e.g., the first row sub-pixel S1 in fig. 5) and the previous sub-pixel row (e.g., the sub-pixel row above the first row sub-pixel S1 in fig. 5, not shown in fig. 5) through a transistor, and the third color sub-pixel B electrically connected to the second segment 32 in the second type data line D2 is electrically connected to the next sub-pixel row (e.g., the second row sub-pixel S2 in fig. 5) and the next sub-pixel row (e.g., third row of sub-pixels S3 in fig. 5), the first color sub-pixels R electrically connected to the second partition 3 in the second type data line D2 are electrically connected to the second gate line 22 between the current sub-pixel row (e.g., the first row of sub-pixels S1 in fig. 5) and the next sub-pixel row (e.g., the second row of sub-pixels S2 in fig. 5) through a transistor;
the first color sub-pixels R electrically connected to the first segments 31 in the third type data lines D3 are electrically connected to the second gate line 22 between the current sub-pixel row (e.g., the first row of sub-pixels S1 in fig. 5) and the previous sub-pixel row (e.g., the sub-pixel row above the first row of sub-pixels S1 in fig. 5, not shown in fig. 5) through transistors, the second color sub-pixels G electrically connected to the first segments 31 in the third type data lines D3 are electrically connected to the first gate line 21 between the current sub-pixel row (e.g., the first row of sub-pixels S1 in fig. 5) and the next sub-pixel row (e.g., the second row of sub-pixels S2 in fig. 5) through transistors, and the second color sub-pixels G electrically connected to the second segments 32 in the third type data lines D3 are electrically connected to the next sub-pixel row (e.g., the second row of sub-pixels S2 in fig. 5) and the next sub-pixel row (e.g., the gate line), third row of sub-pixels S3 in fig. 5), and the third color sub-pixel B electrically connected to the second partition 32 in the third type data line D3 are electrically connected to the second gate line 22 between the current sub-pixel row (e.g., the first row of sub-pixels S1 in fig. 5) and the next sub-pixel row (e.g., the second row of sub-pixels S2 in fig. 5) through a transistor.
It should be noted that, the above is a schematic illustration in which the arched data line 3 spans the width of two sub-pixels in the direction perpendicular to the first direction OO ', and in a specific implementation, the arched data line 3 may also be disposed in other manners, for example, the arched data line 3 spans the width of three, four or more sub-pixels in the direction perpendicular to the first direction OO', which is not limited by the present invention.
In specific implementation, referring to fig. 6, 7 and 8, where fig. 7 is an enlarged schematic view of fig. 6 at a position of a protrusion E on the left side, and fig. 8 is an enlarged schematic view of fig. 6 at a position of a protrusion E on the right side, the display substrate further includes a touch signal line 4, and the touch signal line 4 is in an arc shape and is located at a gap between two columns of sub-pixels between two adjacent data lines 3.
In specific implementation, as shown in fig. 7 or 8, the orthographic projection of the compensation portion F on the substrate does not overlap with the orthographic projection of the touch signal line 4 on the substrate.
As shown in fig. 6 and 9, the display substrate provided in the embodiment of the present application is configured by using Source 2dot inversion and an arc scanning pixel architecture, and the polarities of the pixels in the same column in one frame are opposite, so that the brightness cancellation can be achieved and the phenomenon of head shaking is avoided. Meanwhile, the Source 2dot inversion and bow-shaped scanning pixel architecture can also perform capacitance compensation design on the AA area Data1 (the leftmost Data line of the display substrate) and the DataN (the rightmost Data line of the display substrate, such as Data7 in fig. 1), so that the problem of brightness difference caused by the charging rate difference between the pixels at the edge of the display area and the pixels in the display area due to different loads can be solved.
The utility model also provides a liquid crystal display panel, include if the utility model provides a display substrate.
The utility model also provides a display device, include if the utility model provides a liquid crystal display panel.
The embodiment of the application has the following beneficial effects: the display substrate provided by the embodiment of the application, for the protruding portion of the data line bent to the non-display area, the compensation portion capable of overlapping with the protruding portion is arranged on the layer where the gate line is located, so that the protruding portion of the data line located in the non-display area and the compensation portion can form a compensation capacitor, thereby avoiding the problem that the display substrate in the prior art is different in brightness due to the fact that when the display substrate is driven by the zigzag data line, the data line is bent to the non-display area partially, but the non-display area is not provided with the sub-pixel, and the part of the data line bent to the non-display area is not electrically connected with the transistor, compared with the data line which is entirely located in the display area in the direction perpendicular to the first direction, the number of the transistors connected by the data line at the edge is reduced, the formed overlapping capacitor is lower, when the pixels in the same row are charged, the signal delay amount which can be generated is different, and the charging, the display substrate provided by the embodiment of the application can solve the problems that the pixel at the edge position is insufficiently charged due to the fact that part of the data line is located in the non-display area, and the pixel brightness of the pixel at the edge is different from that of the pixel in the display area; moreover, the main reason for the difference between the overlap capacitance (Cdg) at the edge of the display area and the overlap capacitance (Cdg) inside the display area is that the transistor is not disposed at the edge portion, that is, the overlap capacitance generated by the gate and the data line of the transistor is lacked.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A display substrate having a display area and a non-display area surrounding the display area, the display substrate comprising: the pixel structure comprises a substrate, a plurality of sub-pixels, grid lines and arched data lines, wherein the sub-pixels are arranged on one side of the substrate in an array mode, the grid lines are arranged between adjacent sub-pixel rows, and the data lines extend along a first direction in a main body direction;
the data line at the edge of the display area comprises a convex part bent to the non-display area; the grid line layer is provided with a compensation part, and the orthographic projection of the compensation part on the substrate is overlapped with the orthographic projection of the projection part on the substrate to form a compensation capacitor.
2. The display substrate of claim 1, wherein a gate line group is disposed between each adjacent sub-pixel row, and the gate line group comprises a first gate line and a second gate line sequentially arranged along the first direction;
for any sub-pixel row, the compensation section includes: a first compensation section and a second compensation section; the first compensation part is connected to the first grid line between the current sub-pixel row and the next sub-pixel row and extends towards one side of the projection part; the second compensation part is connected to the second gate line between the current sub-pixel row and the previous sub-pixel row and extends towards one side of the protrusion part.
3. The display substrate according to claim 2, wherein an area of the first compensation portion is equal to an area of a gate electrode to which the first gate line is connected in the display region;
the area of the second compensation part is equal to the area of the grid electrode connected with the second grid line in the display area.
4. The display substrate according to claim 2, wherein a shape of the first compensation portion is the same as a shape of a gate electrode to which the first gate line is connected in the display region;
the shape of the second compensation part is the same as that of a gate electrode connected with the second gate line in the display region.
5. The display substrate according to claim 2, wherein a width of the first compensation portion in a direction perpendicular to the first direction is larger than a width of the data line in the direction perpendicular to the first direction;
the width of the second compensation portion in the direction perpendicular to the first direction is larger than the width of the data line in the direction perpendicular to the first direction.
6. The display substrate according to any one of claims 2-5, wherein each of the arcuate data lines comprises a plurality of sequentially connected arcuate portions, each of the arcuate portions comprising a first portion located between two adjacent subpixels in a current subpixel row, a second portion located between two adjacent subpixels in a next subpixel row, and a third portion located between the current subpixel row and the next subpixel row and connecting the first portion and the second portion across two subpixels;
both sides of the first sub-part of the data line in the display area are respectively electrically connected with the sub-pixels through transistors, and both sides of the second sub-part of the data line in the display area are respectively electrically connected with the sub-pixels through transistors; the data lines at the edge of the display area are only positioned at two sides of the first subsection or the second subsection of the display area and are respectively connected with the sub-pixels through transistors.
7. The display substrate according to claim 6, wherein the two sub-pixels electrically connected to the first portion are electrically connected to different gate line groups, respectively; the two sub-pixels electrically connected to the second sub-portion are electrically connected to different gate line groups respectively.
8. The display substrate according to claim 7, wherein each of the sub-pixel rows comprises a plurality of first sub-pixel groups, second sub-pixel groups and third sub-pixel groups arranged in a circular sequence; the first sub-pixel group, the second sub-pixel group and the third sub-pixel group are provided with a first color sub-pixel, a second color sub-pixel and a third color sub-pixel which are sequentially arranged;
the data lines in the display area comprise a plurality of data line groups which are circularly arranged, and each data line group comprises a first type of data line, a second type of data line and a third type of data line;
the first sub-pixel group of the first sub-pixel row is electrically connected with the first color sub-pixel of the first sub-pixel group and the second color sub-pixel of the second sub-pixel group through a transistor, and the second sub-pixel group of the first sub-pixel row is electrically connected with the first color sub-pixel of the second sub-pixel group through a transistor;
the first sub-pixel group of the second sub-pixel row is electrically connected with the first sub-pixel group of the first sub-pixel group and the second sub-pixel group of the second sub-pixel row through a transistor;
the first sub-pixel in the third sub-pixel group of the current sub-pixel row is electrically connected with the first color sub-pixel and the second color sub-pixel through a transistor, and the second sub-pixel in the second sub-pixel group of the next sub-pixel row is electrically connected with the second color sub-pixel and the third color sub-pixel through a transistor.
9. The display substrate of claim 8, wherein the third color sub-pixel electrically connected to the first segment of the first type data line is electrically connected to the first gate line between a current sub-pixel row and a next sub-pixel row, the first color sub-pixel electrically connected with the first sub-part of the first type data line is electrically connected with the second grid line between the current sub-pixel row and the previous sub-pixel row through the transistor, the first color sub-pixel electrically connected with the second division part in the first type data line is electrically connected with the second grid line between the current sub-pixel row and the next sub-pixel row through the transistor, the second color sub-pixel electrically connected with the second part in the first type data line is electrically connected with the first grid line between the next sub-pixel row and the next sub-pixel row through the transistor;
the second color sub-pixel electrically connected with the first part in the second type data line is electrically connected with the first grid line between the current sub-pixel row and the next sub-pixel row through the transistor, the third color sub-pixel electrically connected with the first part in the second type data line is electrically connected with the second grid line between the current sub-pixel row and the previous sub-pixel row through the transistor, the third color sub-pixel electrically connected with the second part in the second type data line is electrically connected with the first grid line between the next sub-pixel row and the next sub-pixel row through the transistor, and the first color sub-pixel electrically connected with the second part in the second type data line is electrically connected with the second grid line between the current sub-pixel row and the next sub-pixel row through the transistor;
the first color sub-pixel electrically connected with the first division part in the third type data line is electrically connected with the second grid line between the current sub-pixel row and the previous sub-pixel row through the transistor, the second color sub-pixel electrically connected with the first division part in the third type data line is electrically connected with the first grid line between the current sub-pixel row and the next sub-pixel row through the transistor, the second color sub-pixel electrically connected with the second division part in the third type data line is electrically connected with the first grid line between the next sub-pixel row and the next sub-pixel row through the transistor, and the third color sub-pixel electrically connected with the second division part in the third type data line is electrically connected with the second grid line between the current sub-pixel row and the next sub-pixel row through the transistor.
10. The display substrate according to claim 6, wherein the display substrate further comprises touch signal lines, and the touch signal lines are in an arc shape and are located at a gap between two columns of sub-pixels between two adjacent data lines.
11. The display substrate according to claim 10, wherein an orthogonal projection of the compensation portion on the substrate does not overlap an orthogonal projection of the touch signal line on the substrate.
12. A liquid crystal display panel comprising the display substrate according to any one of claims 1 to 11.
13. A display device comprising the liquid crystal display panel according to claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021829249.0U CN212781608U (en) | 2020-08-27 | 2020-08-27 | Display substrate, liquid crystal display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021829249.0U CN212781608U (en) | 2020-08-27 | 2020-08-27 | Display substrate, liquid crystal display panel and display device |
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| CN212781608U true CN212781608U (en) | 2021-03-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038408A (en) * | 2021-11-23 | 2022-02-11 | 武汉华星光电半导体显示技术有限公司 | Display panel, driving method thereof and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038408A (en) * | 2021-11-23 | 2022-02-11 | 武汉华星光电半导体显示技术有限公司 | Display panel, driving method thereof and display device |
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