CN212781099U - Chip testing module - Google Patents
Chip testing module Download PDFInfo
- Publication number
- CN212781099U CN212781099U CN202021223303.7U CN202021223303U CN212781099U CN 212781099 U CN212781099 U CN 212781099U CN 202021223303 U CN202021223303 U CN 202021223303U CN 212781099 U CN212781099 U CN 212781099U
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- Prior art keywords
- chip
- carrier plate
- tested
- test
- conductive element
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The application provides a chip test module. This chip test module includes: the mounting seat is used for mounting a chip to be tested; and the inner carrier plate assembly is assembled with the mounting seat and comprises an inner carrier plate, a first needle carrier plate and a second needle carrier plate, the inner carrier plate is arranged between the first needle carrier plate and the second needle carrier plate, the first needle carrier plate is provided with a first conductive element electrically connected with the chip to be tested and the inner carrier plate, the second needle carrier plate is provided with a second conductive element and a communication interface electrically connected with the inner carrier plate, the inner carrier plate is used for mounting the test chip, the test chip is electrically connected with the chip to be tested through the inner carrier plate and the first conductive element and is used for testing the chip to be tested, and a test result is output through the communication interface. The chip testing module solves the problem of signal integrity between a testing chip and a chip to be tested.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a chip testing module.
Background
After the chip is manufactured, the chip must be tested to ensure the correct functioning of the chip. In a conventional chip testing method, a chip to be tested is usually mounted in a chip testing module, a testing chip is attached to the surface of a testing carrier, and is connected to the chip to be tested through a wire, and the testing carrier is connected to the packaged chip to be tested and an automatic testing machine. The automatic testing machine detects whether the function and the performance of the chip to be tested are normal or not through the test carrier plate, and chips with indexes which do not meet the requirements are removed. However, as the speed of the chips to be tested increases, the signal integrity problem encountered by the test carrier during the chip test increases, for example: reflection, loss and crosstalk have not been able to meet chip testing requirements.
SUMMERY OF THE UTILITY MODEL
The application provides a chip test module. This chip test module includes: the mounting seat is used for mounting a chip to be tested; and the inner carrier plate assembly is assembled with the mounting seat together, the inner carrier plate assembly comprises an inner carrier plate, a first needle carrier plate and a second needle carrier plate, the inner carrier plate is arranged between the first needle carrier plate and the second needle carrier plate, the first needle carrier plate is provided with a first conductive element electrically connected with the chip to be tested and the inner carrier plate, the second needle carrier plate is provided with a second conductive element electrically connected with the inner carrier plate and a communication interface electrically connected with the second conductive element, the inner carrier plate is used for mounting a test chip, the test chip passes through the inner carrier plate and the first conductive element and the chip to be tested are electrically connected, and is used for testing the chip to be tested and outputting a test result through the communication interface.
Optionally, the mounting base includes a base body and a cover body installed in cooperation with the base body, the chip to be tested is disposed between the base body and the cover body, and the base body is provided with a channel for the first conductive element to pass through.
Optionally, the cover is rotatably mounted to the base.
Optionally, the mounting base further comprises a knob and a pressing block matched with the knob, and the pressing block can be enabled to press the chip to be tested by rotating the knob.
Optionally, the seat body, the first needle carrier plate and the second needle carrier plate are fixedly connected.
Optionally, the chip test module further includes a test carrier, and the base, the first pin carrier, the second pin carrier and the test carrier are fixedly connected through a fastener.
Optionally, the inner carrier plate is mounted on the second needle carrier plate, and the second needle carrier plate is provided with a limiting column for limiting the inner carrier plate.
Optionally, the first conductive element comprises one of the following conductive elements: a metal probe, a copper pillar; the second conductive element comprises one of the following conductive elements: metal probes, copper columns.
Optionally, the inner carrier plate is manufactured by adopting an HDI process or a substrate process.
Optionally, the chip to be tested includes: SoC, CPU and FPGA.
According to the chip testing module, the inner carrier plate used for mounting the testing chip is arranged between the first pin carrier plate and the second pin carrier plate, so that the distance between the testing chip and the chip to be tested is short, the signal loss and crosstalk problems can be effectively reduced, the thickness of the inner carrier plate is small, the distance between the testing chips arranged on the upper surface and the lower surface of the inner carrier plate is short, the influence caused by signal reflection can be reduced, and therefore the problem of signal integrity between the testing chip and the chip to be tested in the prior art is solved; in addition, different inner carrier plates can be replaced according to the test requirements of different models of test chips, so that the cost can be reduced, and the inner carrier plates can be upgraded along with the progress of the process of the printed circuit board.
Drawings
FIG. 1 is an exploded view of a chip test module according to the present application.
Fig. 2 is an assembly view of the chip test module shown in fig. 1.
Fig. 3 is an assembly view of the chip test module shown in fig. 1, wherein the cover is in an open state.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The chip test module of the present application will be described in detail with reference to the accompanying drawings. The features of the following examples and embodiments may be combined with each other without conflict.
Referring to fig. 1 to fig. 3, an embodiment of the present application provides a chip testing module 100 for performing a mass production Test on a chip FT (Final Test) to be tested, so as to detect whether the function and performance of the chip to be tested are normal or not, and to remove the chip to be tested whose index does not meet the requirement.
The chip to be tested includes a digital chip with a high-speed memory interface, for example: SoC (System on Chip), CPU (central processing Unit), FPGA (Field programmable gate Array), and other chips, but not limited thereto.
The chip test module 100 includes a mount 10 and an inner carrier assembly. The mounting base 10 is used for mounting a chip to be tested. The inner carrier plate assembly is assembled with the mounting seat 10, and specifically, the inner carrier plate assembly is mounted below the mounting seat 10.
Interior carrier plate subassembly includes interior carrier plate 21, first needle carrier plate 22, second needle carrier plate 23, interior carrier plate 21 install in between first needle carrier plate 22 and the second needle carrier plate 23, first needle carrier plate 22 be equipped with the chip that awaits measuring with the first conductive element 221 that interior carrier plate electricity is connected, second needle carrier plate 23 be equipped with the second conductive element (not shown) that interior carrier plate 21 electricity is connected and with the communication interface that the second conductive element electricity is connected, interior carrier plate 21 is used for installing test chip 24. The test chip 24 is electrically connected to the chip to be tested through the inner carrier plate 21 and the first conductive element 221, and is configured to test the chip to be tested and output a test result through the communication interface.
In one embodiment, the test chip 24 is a memory chip, and correspondingly, the signal for completing the wiring on the inner carrier 21 is a memory high-speed interface signal. In another embodiment, the test chip 24 may be other chips that are difficult to operate at high rates for signal integrity reasons.
According to the chip testing module 100, the inner carrier plate 21 used for mounting the testing chip 24 is arranged between the first needle carrier plate 22 and the second needle carrier plate 23, so that the distance between the testing chip 24 and a chip to be tested is short, the problems of signal loss and crosstalk can be effectively reduced, the thickness of the inner carrier plate 21 is small, the distance between the testing chips 24 arranged on the upper surface and the lower surface of the inner carrier plate 21 is short, the influence caused by signal reflection can be reduced, and therefore the problem of signal integrity between the testing chip 24 and the chip to be tested is solved; in addition, for the test requirements of different models of test chips, different inner carrier boards 21 can be replaced, so that the cost can be reduced, and the inner carrier boards 21 can be upgraded along with the progress of the printed circuit board process.
In one embodiment, the mounting base 10 includes a base 11 and a cover 12 installed to match with the base, the chip to be tested is disposed between the base 11 and the cover 12, and the base 11 is provided with a channel for the first conductive element 221 to pass through. Therefore, the chip to be tested can be more conveniently and reliably limited by matching the base body 11 and the cover body 12. When the chip mounting base is used, the cover body 12 is firstly opened, then a chip to be tested is arranged on the base body 11, and then the cover body 12 is closed, so that the chip to be tested can be arranged on the mounting base 10. In one embodiment, the chip to be tested is disposed on the base 11. In another embodiment, the chip to be tested may also be disposed on the cover 12.
In the illustrated embodiment, the cover 12 is rotatably mounted to the housing 11. In this manner, by rotating the cover 12, the cover 12 can be urged to switch between the open state and the closed state. When the chip to be tested needs to be disposed on the mounting base 10, the cover 12 is rotated first, so that the cover 12 is rotated to an open state (see fig. 3), then the chip to be tested is disposed on the base 11, and then the cover 12 is rotated in a reverse direction, so that the cover 12 is switched to a closed state (see fig. 2), and at this time, the chip to be tested is limited between the base 11 and the cover 12. When the cover 12 is in the closed state, the cover 12 and the base 11 can be fixed by means of a snap fit or the like.
In other embodiments, the cover 12 may also be detachably mounted on the base 11, and when the chip to be tested needs to be mounted on the mounting base 10, the cover 12 is first detached, the chip to be tested is then mounted on the base 11, and then the cover 12 is mounted on the base 11. The above are only some examples and are not limited to the above examples.
The mounting seat 10 further comprises a knob 13 and a pressing block 14 matched with the knob 13, and the pressing block 14 can press the chip to be tested by rotating the knob 13. In this way, the pressing block 14 is pressed against the chip to be tested by the adjusting knob 13, so that the chip to be tested and the first conductive element 221 are stably and well electrically connected.
In the illustrated embodiment, the knob 13 is connected with the pressing block 14 through a screw thread, and the pressing block 14 is matched with the cover 12 for limiting, so that when the knob 13 is rotated, the pressing block 14 can be driven to move in the up-down direction, and the chip to be tested is pressed tightly by the pressing block 14.
In another embodiment, the mounting base 10 includes an elastic element abutting against the chip to be tested, and the elastic element is disposed between the cover 12 and the chip to be tested, and abuts against the chip to be tested through the elastic element, so as to press the chip to be tested, and the chip to be tested and the first conductive element 221 are kept in stable and good electrical connection. The above are only some examples and are not limited to the above examples.
In the illustrated embodiment, the housing 11, the first needle carrier plate 22 and the second needle carrier plate 23 are fixedly connected. That is, the mounting socket 10 and the inner carrier plate assembly are fixed together. In other embodiments, the mounting base 10 and the inner carrier plate assembly may be removably mounted together.
The chip test module 100 further includes a test carrier, which is a circuit board for connecting the packaged chip to be tested and the automatic tester. The base body 11, the first needle carrier plate 22, the second needle carrier plate 23 and the test carrier plate are fixedly connected through fasteners. Therefore, the fixing mode is convenient and reliable.
In the illustrated embodiment, the fastening member is a bolt, and the bolt is sequentially inserted through the base body 11, the first needle carrier plate 22, the second needle carrier plate 23 and the test carrier plate and then is fixed with a nut. In this embodiment, the base 11, the first needle carrier 22, the second needle carrier 23 and the test carrier are respectively square, and through holes for bolts to pass through are respectively disposed at four corners of the base 11, the first needle carrier 22, the second needle carrier 23 and the test carrier. In other embodiments, the seat 11, the first needle carrier plate 22, the second needle carrier plate 23 and the test carrier plate may be fixed together by means of snapping, gluing, or the like.
The inner carrier 21 is mounted on the second needle carrier 23, and the second needle carrier 23 is provided with a limiting post 231 for limiting the inner carrier 21. The limiting post 231 may be made of nylon or other materials. Thus, by providing the limiting column 231 on the second needle carrier plate 23, the inner carrier plate 21 can be conveniently and reliably limited, and the inner carrier plate 21 can be conveniently replaced according to the detection requirement. In the illustrated embodiment, the two rows of the retaining pillars 231 are provided, the inner carrier 21 is limited between the two rows of the retaining pillars 231, and two or more retaining pillars 231 are provided in each row.
The first conductive element 221 includes one of the following conductive elements: a metal probe, a copper pillar; the second conductive element comprises one of the following conductive elements: metal probes, copper columns. In the illustrated embodiment, the first conductive element 221 is a metal probe, and the second conductive element is a metal probe. In another embodiment, the first conductive element 221 is a copper pillar and the second conductive element is a copper pillar. The above are only some examples and are not limited to the above examples.
In a preferred embodiment, the inner carrier 21 adopts a HDI (High Density Interconnection) process. Because the inner carrier plate 21 adopts the HDI process, the advantages are as follows: 1. the inner carrier plate 21 is thin, the distance between the test chips 24 arranged on the upper surface and the lower surface of the inner carrier plate 21 is short, and the influence caused by signal reflection is small; 2. the inner carrier plate 21 adopts a blind hole burying process, Stub (Stub) is not generated in a via hole, and the signal reflection quantity is small; 3. the test chip 24 is arranged close to the chip to be tested, so that the problems of signal loss and crosstalk can be solved; 4. for the test requirements of different models of test chips, different inner carrier plates 21 can be replaced without replacing the test carrier plates, so that the cost can be reduced, and the inner carrier plates 21 can be upgraded along with the progress of the printed circuit board process. Therefore, the inner carrier plate 21 has good signal integrity due to the HDI process, the problem of yield loss caused by the signal integrity is solved, and the cost is saved.
In other embodiments, the inner carrier 21 may also be manufactured by a package substrate process, and is not limited thereto.
When the chip testing module 100 of the present application is used to test a chip to be tested, the chip to be tested is electrically connected to the inner carrier 21 through the first conductive element 221 of the first needle carrier 22, so that a high-speed signal is transmitted between the chip to be tested and the testing chip 24, and the chip to be tested can determine whether the signal transmission between the chip to be tested and the testing chip 24 is normal; then, the test chip 24 transmits the determination result to the test carrier plate 30 through the second conductive elements and the communication interface on the inner carrier plate 21 and the second pin carrier plate 23 via a low-speed signal, and the test carrier plate 30 transmits the determination result to an automatic test machine (not shown), which can determine whether the function and performance of the chip to be tested are normal according to the received information, so as to reject the chip to be tested that does not meet the requirement.
Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
The disclosure of this patent document contains material which is subject to copyright protection. The copyright is owned by the copyright owner. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office official records and records.
Claims (10)
1. A chip test module, comprising:
the mounting seat (10) is used for mounting a chip to be tested; and
the inner carrier plate component is assembled with the mounting seat (10) and comprises an inner carrier plate (21), a first needle carrier plate (22) and a second needle carrier plate (23), the inner carrier plate (21) is installed between the first needle carrier plate (22) and the second needle carrier plate (23), the first needle carrier plate (22) is provided with a first conductive element (221) electrically connected with the chip to be tested and the inner carrier plate, the second needle carrier plate (23) is provided with a second conductive element electrically connected with the inner carrier plate (21) and a communication interface electrically connected with the second conductive element, the inner carrier plate (21) is used for installing a test chip (24),
the test chip is electrically connected with the chip to be tested through the inner carrier plate (21) and the first conductive element (221), and is used for testing the chip to be tested and outputting a test result through the communication interface.
2. The chip testing module according to claim 1, wherein the mounting base (10) includes a base body (11) and a cover body (12) installed in cooperation with the base body, the chip to be tested is disposed between the base body and the cover body, and the base body is provided with a channel for the first conductive element to pass through.
3. The chip test module according to claim 2, wherein the cover is rotatably mounted to the housing.
4. The die testing module set of claim 2, wherein the mounting base further comprises a knob (13) and a pressing block (14) matched with the knob (13), and the pressing block can be pressed against the die to be tested by rotating the knob.
5. The die test module of claim 2, wherein the base, the first pin carrier and the second pin carrier are fixedly connected.
6. The die test module of claim 5, wherein the die test module further comprises a test carrier, and the base, the first pin carrier, the second pin carrier and the test carrier are fixedly connected by a fastener.
7. The die test module according to claim 1, wherein the inner carrier (21) is mounted to the second pin carrier (23) which is provided with a stopper (231) for limiting the inner carrier.
8. The chip test module of claim 1, wherein the first conductive element comprises one of: a metal probe, a copper pillar; the second conductive element comprises one of the following conductive elements: metal probes, copper columns.
9. The chip test module of claim 1, wherein the inner carrier is fabricated by an HDI process or a substrate process.
10. The chip test module of claim 1, wherein the chip under test comprises: SoC, CPU and FPGA.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021223303.7U CN212781099U (en) | 2020-06-28 | 2020-06-28 | Chip testing module |
| PCT/CN2020/134978 WO2022001007A1 (en) | 2020-06-28 | 2020-12-09 | Chip test module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021223303.7U CN212781099U (en) | 2020-06-28 | 2020-06-28 | Chip testing module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212781099U true CN212781099U (en) | 2021-03-23 |
Family
ID=75087000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021223303.7U Expired - Fee Related CN212781099U (en) | 2020-06-28 | 2020-06-28 | Chip testing module |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN212781099U (en) |
| WO (1) | WO2022001007A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113466664A (en) * | 2021-07-02 | 2021-10-01 | 深圳市宏旺微电子有限公司 | DDR chip testing method and device, terminal device and storage medium |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117054859B (en) * | 2023-10-11 | 2023-12-29 | 苏州朗之睿电子科技有限公司 | Chip heating test device and test method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7338295B2 (en) * | 2006-07-21 | 2008-03-04 | Protos Electronics | Test socket-lid assembly |
| CN102788947A (en) * | 2011-05-17 | 2012-11-21 | 联咏科技股份有限公司 | Testing chip and chip testing system thereof |
| CN204389644U (en) * | 2015-02-11 | 2015-06-10 | 中芯国际集成电路制造(北京)有限公司 | Test board device |
| CN105959067A (en) * | 2016-04-22 | 2016-09-21 | 北京联盛德微电子有限责任公司 | Calibration method and device for transmitter chip |
| CN207557414U (en) * | 2016-12-28 | 2018-06-29 | 上海捷策创电子科技有限公司 | A kind of wafer-level test device |
| CN210668281U (en) * | 2019-12-06 | 2020-06-02 | 加特兰微电子科技(上海)有限公司 | Chip testing device and antenna packaging chip |
-
2020
- 2020-06-28 CN CN202021223303.7U patent/CN212781099U/en not_active Expired - Fee Related
- 2020-12-09 WO PCT/CN2020/134978 patent/WO2022001007A1/en active Application Filing
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113466664A (en) * | 2021-07-02 | 2021-10-01 | 深圳市宏旺微电子有限公司 | DDR chip testing method and device, terminal device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022001007A1 (en) | 2022-01-06 |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20210323 |