CN212752490U - TS stream Ethernet transmission device - Google Patents
TS stream Ethernet transmission device Download PDFInfo
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- CN212752490U CN212752490U CN202021536595.XU CN202021536595U CN212752490U CN 212752490 U CN212752490 U CN 212752490U CN 202021536595 U CN202021536595 U CN 202021536595U CN 212752490 U CN212752490 U CN 212752490U
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Abstract
The application discloses a TS Ethernet transmission device, which comprises a CPU chip and a data receiving interface circuit, the input end of the data receiving interface circuit is suitable for being electrically connected with the output end of the TS data sending device, the output end of the data receiving interface circuit is electrically connected with the input end of the FPGA chip, the input and output ends of the CPU chip are electrically connected with the first input and output end of the FPGA chip, the second input and output end of the FPGA chip is electrically connected with the input end of the Ethernet interface circuit, the scheme realizes the function of MAC by using the FPGA, TS stream data are directly packaged by the FPGA, the CPU completes the filling of a packet header and the analysis and realization of a protocol stack, the efficiency of the FPGA and the flexibility of the CPU are fully exerted, and the problems of imperfect realization of the protocol stack, low efficiency, low speed and the like existing in the previous scheme are effectively solved.
Description
Technical Field
The present disclosure relates to the field of digital television technologies, and in particular, to a TS stream ethernet transmission device.
Background
The TS stream is a transport stream in which compressed data obtained by compression-encoding video and audio data is packetized, and data reception is mainly performed in DVB applications. The current method for realizing TS Ethernet transmission is realized by packaging TS stream with FPGA, meanwhile, FPGA is also responsible for realizing TCP/IP protocol stack, Ethernet interface circuit is completed by connecting MAC + PHY chip externally. The main problem of the current scheme is that the protocol stack which can be completed by the method for realizing the TCP/IP protocol stack by using the FPGA is imperfect, so that the efficiency is low and the speed is slow.
Disclosure of Invention
In view of this, the present disclosure provides a TS streaming ethernet transmission apparatus, including: the system comprises a CPU chip, a data receiving interface circuit, an FPGA chip and an Ethernet interface circuit;
the input end of the data receiving interface circuit is suitable for being electrically connected with the output end of the TS data sending device;
the output end of the data receiving interface circuit is electrically connected with the input end of the FPGA chip;
the input and output end of the CPU chip is electrically connected with the first input and output end of the FPGA chip;
the second input/output end of the FPGA chip is electrically connected with the input end of the Ethernet interface circuit;
the CPU chip is configured to generate a data packet header and a protocol data packet, and send the data packet header and the protocol data packet to the FPGA chip;
the data receiving interface circuit is configured to receive TS stream data information and send the TS stream data information to the FPGA chip;
the FPGA chip is configured to receive the data packet header and the protocol data packet sent by the CPU chip, receive the TS stream data information sent by the data receiving interface circuit, package the TS stream data information, the data packet header and the protocol data packet to obtain a TS stream data packet, and send the TS stream data packet to the Ethernet interface circuit;
the Ethernet interface circuit is configured to receive the TS streaming data packet sent by the FPGA chip and send the TS streaming data packet to an Ethernet.
In one possible implementation, the CPU chip is electrically connected to the FPGA chip through an EMI bus.
In one possible implementation manner, the FPGA chip includes an SPI interface, a data storage and forwarding circuit, a block random access memory, and a clock management circuit;
the input end of the SPI interface is used as the input end of the FPGA unit and is suitable for being electrically connected with the output end of the TS data sending device;
a first input/output end of the SPI is electrically connected with a first input/output end of the data storage and forwarding circuit;
a second input/output end of the SPI is used as a first input/output end of the FPGA unit and is electrically connected with an input/output end of the CPU chip;
the input and output ends of the block random access memory are electrically connected with the second input and output ends of the data storage and forwarding circuit;
and the input and output end of the clock management circuit is electrically connected with the fourth input and output end of the data storage unit.
In a possible implementation manner, the FPGA chip further includes an ethernet data frame processing circuit;
the first input/output end of the Ethernet data frame processing circuit is electrically connected with the third input/output end of the data storage and forwarding circuit;
and a second input/output end of the Ethernet data frame processing circuit is electrically connected with a second input/output end of the SPI interface.
In a possible implementation manner, the FPGA chip further includes an ethernet port circuit;
a first input/output end of the Ethernet interface circuit is electrically connected with a second input/output end of the Ethernet data frame processing circuit;
and the second input/output end of the Ethernet interface circuit is electrically connected with the input/output end of the Ethernet interface circuit.
In one possible implementation, the ethernet interface circuit includes a PHY chip.
In one possible implementation, the FPGA chip is electrically connected to the PHY chip through a GMII interface.
In one possible implementation, the data receiving interface circuit includes an ASI chip.
In one possible implementation, the CPU chip is embedded.
In one possible implementation, the CPU chip has a model of STI 7101;
the model F of the FPGA chip is ALTERA EP3C16F 484.
The data receiving interface circuit is configured to receive TS stream data information and send the TS stream data information to the FPGA chip, the FPGA chip is configured to receive a data packet header and a protocol data packet sent by the CPU chip and receive the TS stream data information sent by the data receiving interface circuit, and the Ethernet interface circuit is configured to receive the TS streaming data packet sent by the FPGA chip and send the TS streaming data packet to the Ethernet. The efficiency of the FPGA and the flexibility of the CPU are fully exerted, and the problems of imperfect realization of a protocol stack, low efficiency, low speed and the like in the prior scheme are effectively solved.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a block schematic diagram of a TS streaming ethernet transport apparatus according to an embodiment of the present disclosure;
fig. 2 shows a schematic diagram of a CPU chip of the TS streaming ethernet transport apparatus according to the embodiment of the present disclosure;
fig. 3 shows a register chip schematic diagram of a TS streaming ethernet transport apparatus according to an embodiment of the present disclosure;
fig. 4 shows an ASI chip schematic diagram of a TS streaming ethernet transport device according to an embodiment of the present disclosure;
fig. 5 shows a PHY chip schematic diagram of a TS streaming ethernet transmission device according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
It should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the invention or for simplicity in description, and do not indicate or imply that the device or element so indicated must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Fig. 1 shows a block schematic diagram of a TS flow ethernet transmission device 100 according to an embodiment of the present disclosure. As shown in fig. 1, the TS streaming ethernet transmission apparatus 100 includes:
a CPU chip 110, a data receiving interface circuit 120, an FPGA chip 130 and an ethernet interface circuit 140, wherein an input terminal of the data receiving interface circuit 120 is adapted to be electrically connected to an output terminal of a TS data transmitting device, an output terminal of the data receiving interface circuit 120 is electrically connected to an input terminal of the FPGA chip 130, an input/output terminal of the CPU chip 110 is electrically connected to a first input/output terminal of the FPGA chip 130, a second input/output terminal of the FPGA chip 130 is electrically connected to an input terminal of the ethernet interface circuit 140, the CPU chip 110 is configured to generate a packet header and a protocol packet and transmit the packet header and the protocol packet to the FPGA chip 130, the data receiving interface circuit 120 is configured to receive TS data information and transmit the TS data information to the FPGA chip 130, the FPGA chip 130 is configured to receive the packet header and the protocol packet transmitted by the CPU chip 110, receive the TS data information transmitted by the data receiving interface circuit 120, and the Ethernet interface circuit 140 is configured to receive the TS streaming data packet sent by the FPGA chip 130 and send the TS streaming data packet to the Ethernet.
By including the CPU chip 110, the data receiving interface circuit 120, the FPGA chip 130, and the ethernet interface circuit 140, an input terminal of the data receiving interface circuit 120 is adapted to be electrically connected to an output terminal of the TS data transmitting apparatus, an output terminal of the data receiving interface circuit 120 is electrically connected to an input terminal of the FPGA chip 130, an input/output terminal of the CPU chip 110 is electrically connected to a first input/output terminal of the FPGA chip 130, a second input/output terminal of the FPGA chip 130 is electrically connected to an input terminal of the ethernet interface circuit 140, the CPU chip 110 is configured to generate a packet header and a protocol packet, and transmit the packet header and the protocol packet to the FPGA chip 130, the data receiving interface circuit 120 is configured to receive TS stream data information and transmit the TS stream data information to the FPGA chip 130, the FPGA chip 130 is configured to receive the packet header and the protocol packet transmitted by the CPU chip 110, the ethernet interface circuit 140 is configured to receive the TS stream data packet sent by the FPGA chip 130 and send the TS stream data packet to the ethernet. The efficiency of the FPGA and the flexibility of the CPU are fully exerted, and the problems of imperfect realization of a protocol stack, low efficiency, low speed and the like in the prior scheme are effectively solved.
Specifically, referring to fig. 1, in a possible implementation manner, the FPGA chip 130 includes an SPI interface, a data storage and forwarding circuit, a block ram, an ethernet data frame processing circuit, and a clock management circuit, wherein an input end of the SPI interface is adapted to be electrically connected to an output end of the TS data transmitting device as an input end of the FPGA unit, a first input/output end of the SPI interface is electrically connected to a first input/output end of the data storage and forwarding circuit, a second input/output end of the SPI interface is electrically connected to the CPU chip 110 as a first input/output end of the FPGA unit, an input/output end of the block ram is electrically connected to a second input/output end of the data storage and forwarding circuit, and an input/output end of the clock management circuit is electrically connected to a third input/output end of the data. The CPU chip 110 is connected to the ethernet interface circuit 140 through the SPI interface in the FPGA chip 130. For example, FPGA chip 130 is model number ALTERA EP3C16F484, and packetizes the data packet header and the protocol data packet received by data receiving interface circuit 120 and transmitted from CPU chip 110 and the TS stream data information transmitted by data receiving interface circuit 120, and then transmits the TS stream data information to ethernet interface circuit 140.
Further, in a possible implementation manner, the FPGA chip 130 further includes an ethernet data frame processing circuit, a first input/output end of the ethernet data frame processing circuit is electrically connected to a second input/output end of the SPI interface, and a second input/output end of the ethernet data frame processing circuit is electrically connected to a fourth input/output end of the data storage and forwarding circuit. For example, the ethernet frame processing circuit packetizes the packet header and the protocol packet received by the SPI from the CPU chip 110 and the TS stream data information received by the data receiving interface circuit 120, and then sends the TS stream data information to the ethernet interface circuit 140 in the form of a data frame.
Further, in a possible implementation manner, the FPGA chip 130 further includes an ethernet port circuit, where a first input/output end of the ethernet port circuit is electrically connected to a second input/output end of the ethernet data frame processing circuit, a second input/output end of the ethernet port circuit is electrically connected to an input/output end of the ethernet interface circuit 140, and the ethernet port circuit is a physical port connected to the ethernet interface circuit 140.
Further, referring to fig. 2, in a possible implementation, the CPU chip 110 is electrically connected to the FPGA chip 130 through an external EMI bus, where the model of the CPU chip 110 is STI7101, referring to fig. 3, the CPU chip 110 further includes a register chip, the model of the register chip is AM29LV128MHL-TSOP5, the CPU chip 110 constructs a packet header and a protocol packet, and then sends the packet header and the protocol packet to the FPGA chip for packaging.
It should be noted that the CPU chip 110 is an embedded CPU.
Further, referring to fig. 4, in one possible implementation, the data receiving interface circuit 120 includes an ASI chip. Illustratively, the ASI chip may be of a type CYP15G0101DXB-BBC, and the ASI chip is connected to an external TS data transmitting device, receives TS stream data information transmitted from the TS data transmitting device, and transmits the TS stream data information to the FPGA chip 130 for packaging.
Further, referring to fig. 5, in a possible implementation manner, the ethernet interface circuit 140 includes a PHY chip, for example, the PHY chip is RTL8201BL, the FPGA chip 130 is electrically connected to the PHY chip through a GMII interface, receives the TS stream packet packaged by the FPGA chip and forwards the TS stream packet to the ethernet, so as to fully exert the efficiency of the FPGA and the flexibility of the CPU, thereby effectively solving the problems of imperfect protocol stack implementation, low efficiency, low speed, and the like in the previous scheme
It should be noted that, although the TS streaming ethernet transmission apparatus 100 is described above by taking the above embodiments as examples, those skilled in the art can understand that the disclosure should not be limited thereto. In fact, the user can flexibly set the TS streaming ethernet transmission apparatus 100 according to personal preference and/or practical application scenario, as long as the required functions are achieved.
Thus, by including the CPU chip 110, the data receiving interface circuit 120, the FPGA chip 130, and the ethernet interface circuit 140, an input terminal of the data receiving interface circuit 120 is adapted to be electrically connected to an output terminal of the TS data transmitting apparatus, an output terminal of the data receiving interface circuit 120 is electrically connected to an input terminal of the FPGA chip 130, an input/output terminal of the CPU chip 110 is electrically connected to a first input/output terminal of the FPGA chip 130, and a second input/output terminal of the FPGA chip 130 is electrically connected to an input terminal of the ethernet interface circuit 140, the CPU chip 110 is configured to generate a packet header and a protocol packet and transmit the packet header and the protocol packet to the FPGA chip 130, the data receiving interface circuit 120 is configured to receive TS stream data information and transmit the TS stream data information to the FPGA chip 130, the FPGA chip 130 is configured to receive the packet header and the protocol packet transmitted by the CPU chip 110, the ethernet interface circuit 140 is configured to receive the TS stream data packet sent by the FPGA chip 130 and send the TS stream data packet to the ethernet. The efficiency of the FPGA and the flexibility of the CPU are fully exerted, and the problems of imperfect realization of a protocol stack, low efficiency, low speed and the like in the prior scheme are effectively solved.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A TS streaming ethernet transport apparatus, comprising: the system comprises a CPU chip, a data receiving interface circuit, an FPGA chip and an Ethernet interface circuit;
the input end of the data receiving interface circuit is suitable for being electrically connected with the output end of the TS data sending device;
the output end of the data receiving interface circuit is electrically connected with the input end of the FPGA chip;
the input and output end of the CPU chip is electrically connected with the first input and output end of the FPGA chip;
the second input/output end of the FPGA chip is electrically connected with the input end of the Ethernet interface circuit;
the CPU chip is configured to generate a data packet header and a protocol data packet, and send the data packet header and the protocol data packet to the FPGA chip;
the data receiving interface circuit is configured to receive TS stream data information and send the TS stream data information to the FPGA chip;
the FPGA chip is configured to receive the data packet header and the protocol data packet sent by the CPU chip, receive the TS stream data information sent by the data receiving interface circuit, package the TS stream data information, the data packet header and the protocol data packet to obtain a TS stream data packet, and send the TS stream data packet to the Ethernet interface circuit;
the Ethernet interface circuit is configured to receive the TS streaming data packet sent by the FPGA chip and send the TS streaming data packet to an Ethernet.
2. The TS streaming Ethernet transmission device of claim 1 wherein the CPU chip is electrically connected to the FPGA chip through an EMI bus.
3. The TS streaming Ethernet transmission device of claim 1 wherein the FPGA chip comprises an SPI interface, a data storage and forwarding circuit, a block random access memory and a clock management circuit;
the input end of the SPI interface is used as the input end of the FPGA unit and is suitable for being electrically connected with the output end of the TS data sending device;
a first input/output end of the SPI is electrically connected with a first input/output end of the data storage and forwarding circuit;
a second input/output end of the SPI is used as a first input/output end of the FPGA unit and is electrically connected with an input/output end of the CPU chip;
the input and output ends of the block random access memory are electrically connected with the second input and output ends of the data storage and forwarding circuit;
and the input and output end of the clock management circuit is electrically connected with the fourth input and output end of the data storage unit.
4. The TS streaming Ethernet transmission device of claim 3 wherein the FPGA chip further comprises Ethernet data frame processing circuitry;
the first input/output end of the Ethernet data frame processing circuit is electrically connected with the third input/output end of the data storage and forwarding circuit;
and a second input/output end of the Ethernet data frame processing circuit is electrically connected with a second input/output end of the SPI interface.
5. The TS streaming Ethernet transmission device of claim 4 wherein the FPGA chip further comprises Ethernet port circuitry;
a first input/output end of the Ethernet interface circuit is electrically connected with a second input/output end of the Ethernet data frame processing circuit;
and the second input/output end of the Ethernet interface circuit is electrically connected with the input/output end of the Ethernet interface circuit.
6. The TS streaming Ethernet transmission of claim 1 wherein the Ethernet interface circuitry comprises a PHY chip.
7. The TS streaming Ethernet transmission device of claim 6 wherein the FPGA chip is electrically connected to the PHY chip via a GMII interface.
8. The TS streaming Ethernet transmission device of any one of claims 1 to 6 wherein the data receiving interface circuit comprises an ASI chip.
9. The TS streaming Ethernet transmission device of any one of claims 1 to 6 wherein the CPU chip is an embedded chip.
10. The TS streaming Ethernet transmission device of claim 1 wherein the CPU chip of the CPU chip is of type STI 7101;
the model of the FPGA chip is ALTERA EP3C16F 484.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021536595.XU CN212752490U (en) | 2020-07-29 | 2020-07-29 | TS stream Ethernet transmission device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021536595.XU CN212752490U (en) | 2020-07-29 | 2020-07-29 | TS stream Ethernet transmission device |
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| CN212752490U true CN212752490U (en) | 2021-03-19 |
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| CN202021536595.XU Active CN212752490U (en) | 2020-07-29 | 2020-07-29 | TS stream Ethernet transmission device |
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