CN212725310U - CMOS image sensor - Google Patents
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- CN212725310U CN212725310U CN202021309711.4U CN202021309711U CN212725310U CN 212725310 U CN212725310 U CN 212725310U CN 202021309711 U CN202021309711 U CN 202021309711U CN 212725310 U CN212725310 U CN 212725310U
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Abstract
The utility model belongs to the technical field of the semiconductor, a CMOS image sensor is related to, this CMOS image sensor includes peripheral logic district and pixel district, and peripheral logic district all includes the substrate and lies in the multilayer metal layer on the substrate with the pixel district, and the metal level height of pixel district is highly unanimous with the metal level of peripheral logic district, and includes the virtual metal level that is used as the structure compensation in the multilayer metal level of pixel district. Therefore, the utility model provides a CMOS image sensor has increased the virtual metal level and has made the metal level height in pixel area and the metal level highly uniform in peripheral logic district to make CMOS image sensor's stress distribution even, dark current diminishes, and then can improve the problem that there is the shadow at the edge of the image that obtains under the high temperature condition.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a CMOS image sensor and manufacturing method thereof.
Background
In the camera module, the image sensor is a soul component, determines the imaging quality of the camera and the structure and specification of other components, and occupies about 52% of the cost in the camera module. An image sensor is a semiconductor device that can convert an optical image into an electrical signal. Image sensors can be broadly classified into Charge Coupled Devices (CCDs) and complementary metal oxide semiconductor Image sensors (CIS). The CCD image sensor is integrated on a monocrystalline silicon material, pixel signals move sequentially row by row and column and are amplified sequentially at the edge outlet position, and the CCD image sensor has the advantages of higher image sensitivity and low noise, but is difficult to integrate with other devices, and has higher power consumption. In contrast, the CMOS image sensor gradually replaces the CCD due to its simple process, easy integration with other devices, small size, light weight, low power consumption, low cost, and the like. CMOS image sensors are widely used in the fields of digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), vehicle imaging devices, and the like.
CMOS image sensors typically include a logic area and a pixel area, and for CMOS image sensors, the characteristics of the pixel area used for sensing light directly determine the performance of the final image sensor. Parameters commonly used for defining the performance of the pixel region include quantum efficiency, dark current, dynamic range, signal-to-noise ratio, and the like, where the dark current refers to an output signal of the pixel region in the absence of incident light, the larger the dark current is, the lower the signal-to-noise ratio of the pixel region is, and the dark current of the pixel region increases exponentially with temperature, and in a high temperature condition, if the dark current is too large, the dark current signal may completely drown out a photoelectric signal of the pixel region, causing image distortion and image quality degradation.
At present, the stress distribution of some types of CMOS image sensors is not uniform due to the difference between the height of the metal layer in the pixel region and the height of the metal layer in the logic region, so that the dark current of the photodiodes at the corners of the CMOS image sensors is relatively large during photoelectric conversion, and the edges of the obtained images are easily shaded under high temperature conditions (e.g., 80 degrees).
In view of the above problems, those skilled in the art have sought solutions.
The foregoing description is provided for general background information and is not admitted to be prior art.
Disclosure of Invention
The to-be-solved technical problem of the utility model lies in, to above-mentioned prior art's defect, provided CMOS image sensor and preparation method to increase virtual metal layer in CMOS image sensor and make the metal level height of pixel district and the metal level highly uniform of peripheral logic district, thereby make CMOS image sensor's stress distribution even, the dark current diminishes, and then can improve the problem that there is the shadow at the edge of the image that obtains under the high temperature condition.
The utility model discloses a realize like this:
the utility model provides a CMOS image sensor, including peripheral logic district and pixel district, peripheral logic district all includes the substrate and is located the multilayer metal level on the substrate with the pixel district, and the metal level height of pixel district is highly unanimous with the metal level of peripheral logic district, and includes the virtual metal level that is used as the structure compensation in the multilayer metal level of pixel district.
Furthermore, the number of metal layers in the pixel area is greater than or equal to that in the peripheral logic area.
Further, the structure of the metal layer of each level of the peripheral logic region is the same as that of the metal layer of the corresponding level of the pixel region.
Further, the height of the metal layer of each level of the peripheral logic region coincides with the height of the metal layer of the corresponding level of the pixel region.
Furthermore, the multi-layer metal layers in the pixel region and the peripheral logic region include a chip interconnection layer and a metal wiring layer.
Further, an electrical contact optimization metal layer is arranged below the metal layer of the bottom layer of the pixel area.
Further, the peripheral logic area and the pixel area each further include a plurality of transistors in the substrate. Wherein the plurality of transistors in the peripheral logic region include transistors formed from an N-type doped layer in the substrate of the peripheral logic region. Wherein the plurality of transistors in the pixel region include transistors formed from an N-type doped layer in the substrate of the pixel region.
Furthermore, the pixel structure also comprises an oxide layer positioned above the metal layer on the top layer of the peripheral logic area and the pixel area.
Furthermore, a micro lens is arranged on the upper surface of the oxide layer of the pixel area.
Further, a color filter is disposed under the microlens.
Furthermore, the upper surface of the oxide layer of the peripheral logic area is provided with a pad area, and the pad area is used for being electrically connected with other hardware. The metal layer on the top layer of the peripheral logic area is electrically connected with the pad area.
Further, the thickness of the dummy metal layer is 4500 angstroms to 5500 angstroms.
Further, the thickness of the dummy metal layer was 5000 angstroms.
Further, the CMOS image sensor is a front-illuminated (FSI) CMOS image sensor, and the multiple metal layers are located on the light receiving surface of the substrate.
The utility model also provides a CMOS image sensor's manufacturing method, include: the semiconductor substrate is divided into a substrate of a peripheral logic region and a substrate of a pixel region. And processing the upper surface of the semiconductor substrate to form a plurality of metal layers on the upper surfaces of the substrate of the peripheral logic area and the substrate of the pixel area, wherein the height of the metal layer of the pixel area is consistent with that of the metal layer of the peripheral logic area, and the plurality of metal layers of the pixel area comprise a virtual metal layer used for structure compensation.
Further, in the step of processing the upper surface of the semiconductor substrate to form the plurality of metal layers on the upper surfaces of the substrate in the peripheral logic region and the substrate in the pixel region, the method includes: the metal layer in the pixel region is optimized to have the same height as that of the metal layer in the peripheral logic region by a CMP (Chemical Mechanical Polishing) process.
Furthermore, the number of metal layers in the pixel area is greater than or equal to that in the peripheral logic area.
Further, the method for manufacturing the CMOS image sensor further includes the steps of: an electrical contact optimization metal layer is disposed below the bottom metal layer of the pixel region.
Further, the thickness of the dummy metal layer is 4500 angstroms to 5500 angstroms.
Further, the thickness of the dummy metal layer was 5000 angstroms.
Further, the CMOS image sensor is a front-illuminated (FSI) CMOS image sensor, and the plurality of metal layers are located on the light receiving surface of the semiconductor substrate.
The utility model provides a CMOS image sensor and manufacturing method thereof, wherein, CMOS image sensor includes peripheral logic district and pixel district, and peripheral logic district all includes the substrate and lies in the multilayer metal layer on the substrate with the pixel district, and the metal level height of pixel district is highly unanimous with the metal level height of peripheral logic district, and includes the virtual metal level that is used as the structure compensation in the multilayer metal layer of pixel district. Therefore, the utility model provides a CMOS image sensor has increased the virtual metal level and has made the metal level height of the metal level height in pixel area and peripheral logic district highly uniform to make CMOS image sensor's stress distribution even, dark current diminishes, and then can improve the problem that there is the shadow at the edge of the image that obtains under the high temperature condition.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a basic structure of a CMOS image sensor system;
fig. 2 is a schematic diagram of an image sensing chip according to a first embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a CMOS image sensor according to a first embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of an example of a CMOS image sensor provided by a first embodiment of the present invention;
fig. 5 is a schematic connection diagram of a transistor according to a first embodiment of the present invention;
fig. 6 is a schematic diagram of a pixel circuit according to a first embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of a CMOS image sensor according to a second embodiment of the present invention;
fig. 8 is a schematic cross-sectional view of an example of a CMOS image sensor according to a second embodiment of the present invention;
fig. 9 is a schematic flow chart of a method for manufacturing a CMOS image sensor according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The term "connected," as used in the present application, is defined as follows, and "connected" is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two connection elements may be directly connected by a metal line or indirectly connected by an intermediate circuit element (e.g., a capacitor, a resistor, or a source or a drain of a transistor).
The terms "upper", "lower", "left", "right", "row direction", "column direction", etc. used in the present invention are only for the sake of clarity and convenience of description of the technical solution, and therefore, are not to be construed as limiting the present invention, for the position or positional relationship indicated based on the drawings.
The embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram of a basic structure of a CMOS image sensor system. As shown in fig. 1, the CMOS image sensor 100 includes a read circuit 104 and a control circuit 108 connected to a pixel array 102, and a functional logic circuit 106 connected to the read circuit 104, logically controlling reading of the pixel circuits; the read circuit 104 and the control circuit 108 are connected to the status register 112, and read control of the pixel array 102 is realized. The pixel array 101 includes a plurality of pixel cells in rows (R1, R2, R3 … Ry) and columns (C1, C2, C3 … Cx), and pixel signals output from the pixel array 102 are output to the read circuit 104 via column lines.
In one embodiment, after each pixel unit obtains image data, the image data is read out using the read circuit 104 whose status register 112 specifies the read mode, and then transferred to the functional logic 106. In particular applications, the read circuit 104 may include analog-to-digital conversion (ADC) circuitry, amplification circuitry, and others. In some embodiments, the status register 112 may include a programming selection system for determining whether the read system is read in a rolling shutter mode or a global shutter mode. The function logic 106 may store only image data or image data applied or processed by an image effect. In one application, read circuit 104 may read out image data a row at a time along read-out column lines (as shown in FIG. 1), or may read out the image data in various other ways. The operation of the control circuit 108 may be determined by the current setting of the status register 112. For example, the control circuit 108 generates a shutter signal for controlling image acquisition. In some applications, the shutter signal may be a global exposure signal such that all pixels of the pixel array 102 acquire their image data simultaneously through a single acquisition window. In some other applications, the shutter signal may be a rolling exposure signal, and each pixel row is sequentially read through the capture window.
The first embodiment:
fig. 2 is a schematic diagram of an image sensing chip according to a first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of a CMOS image sensor according to a first embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of an example of a CMOS image sensor according to a first embodiment of the present invention. Fig. 5 is a schematic connection diagram of a transistor according to a first embodiment of the present invention. Fig. 6 is a schematic diagram of a pixel circuit according to a first embodiment of the present invention. For clarity of description, please refer to fig. 2, fig. 3, fig. 4, fig. 5, and fig. 6 for a CMOS image sensor according to a first embodiment of the present invention.
Referring to fig. 2, a CMOS image sensor according to a first embodiment of the present invention includes a peripheral logic region 1 and a pixel region 2.
The peripheral logic area and the pixel area comprise a substrate and a plurality of metal layers positioned on the substrate.
In one embodiment, referring to fig. 3, the substrate of the peripheral logic region and the substrate of the pixel region are obtained by dividing a semiconductor substrate 301 (e.g., a silicon substrate). It should be understood that the division of the semiconductor substrate 301 into the substrate of the peripheral logic region as the substrate of the pixel region is merely for convenience of description, and not an actual division or division.
In one embodiment, the peripheral logic region is configured to process light detected by the pixel region into electrical signals to obtain optical data.
In one embodiment, the peripheral logic region further includes a plurality of transistors located in the substrate. Wherein the plurality of transistors in the peripheral logic region comprise transistors formed from an N-type doped layer 302 (as shown in fig. 3) in the substrate of the peripheral logic region. Specifically, the N-type doped layer 302 may be formed by doping an N-type ion material (e.g., N-type silicon) in a P-type silicon substrate.
In one embodiment, referring to FIG. 3, the multi-layered metal layers of the peripheral logic region on the substrate may include M1, … …, Mn-1, Mn, where M1 is the bottom metal layer, M2 to Mn-1 are the middle metal layers, and Mn is the top metal layer.
The height of the metal layer of the pixel area is consistent with that of the metal layer of the peripheral logic area, and the multiple metal layers of the pixel area comprise a virtual metal layer used for structure compensation.
In one embodiment, referring to fig. 3, the metal layer height of the pixel region is the same as the metal layer height of the peripheral logic region, so that the top metal layer of the pixel region and the top metal layer of the peripheral logic region are on the same horizontal line.
In one embodiment, the pixel region includes, but is not limited to, at least one dummy structure layer.
In one embodiment, referring to fig. 3, the metal layers of the pixel region on the substrate may include M1, … …, Mn-1, Mn ', where M1 is the bottom metal layer, M2 to Mn-1 are the middle metal layers, and Mn' is the dummy metal layer.
In one embodiment, referring to fig. 3, the dummy metal layer Mn' included in the pixel region may not need to be electrically connected to any device, and may be used only for structural compensation of the pixel region metal layer or height compensation of the pixel region metal layer in order to make the stress distribution of the CMOS image sensor uniform.
In one embodiment, the thickness of the dummy metal layer in the pixel region is between 4500 angstroms and 5500 angstroms (preferably, the thickness of the dummy metal layer in the pixel region is 5000 angstroms).
In one embodiment, the number of metal layers in the pixel region may be greater than or equal to the number of metal layers in the peripheral logic region. For example, the number of metal layers in the pixel region is equal to the number of metal layers in the peripheral logic region, and referring to fig. 4, the number of metal layers in the pixel region and the number of metal layers in the peripheral logic region are both 3, that is, the pixel region includes: the bottom metal layer M1, the middle metal layer M2 and the top dummy metal layer M3', and the peripheral logic region includes: a bottom metal layer M1, a middle metal layer M2, and a top metal layer M3.
In one embodiment, when the number of metal layers in the pixel region is equal to the number of metal layers in the peripheral logic region, the structure of the metal layer in each level of the peripheral logic region may be the same as the structure of the metal layer in the corresponding level of the pixel region, and therefore, the foregoing arrangement may enable a more uniform stress distribution of the CMOS image sensor. Further, the height of the metal layer of each level of the peripheral logic region may be consistent with the height of the metal layer of the corresponding level of the pixel region, and thus, the foregoing arrangement may not make the stress distribution of the CMOS image sensor more uniform, and may also facilitate the wiring between the metal layers in the CMOS image sensor.
In one embodiment, the pixel region further includes a plurality of transistors in the substrate. Wherein the plurality of transistors in the pixel region include transistors formed from an N-type doped layer in the substrate of the pixel region. Further, various types of transistors (e.g., a transfer transistor TX, a reset transistor RST, a source follower transistor SF, a row select transistor RS, a conversion gain control transistor DCG, and the like) may be included in the pixel region. Specifically, the N-type doped layer may be formed by doping an N-type ion material (e.g., N-type silicon) in a P-type silicon substrate.
In one embodiment, the plurality of metal layers in the pixel region and the peripheral logic region each include a chip interconnection layer and a metal wiring layer. For example, referring to fig. 4, the metal layer M1 of the bottom layer may serve as a metal wiring layer for connecting with transistors in the substrate of the pixel region and/or transistors in the substrate of the peripheral logic, and is connected with the metal layer M2 of the upper level (wherein, the metal layer M2 may be a chip interconnection layer), and further, the chip interconnection layer of the peripheral logic region may be connected with the metal layer M3 of the upper level and the chip interconnection layer of the pixel region (wherein, the dummy metal layer M3' is not connected with any metal layer or component). The metal layer M3 in the peripheral logic region is an off-chip connection layer and is used for connecting with a pad region on the top of a chip so as to connect with other components outside the chip.
In an embodiment, the connection manner of the transistor and the metal layer in the pixel region can refer to fig. 5.
In one embodiment, the pixel region may include a pixel circuit of a 3T or 4T structure, and the pixel circuit may include various transistors and photodiodes of the pixel region.
In one embodiment, referring to FIG. 6, each sensor pixel circuit 200 includes a photodiode 210 (e.g., a photosensor element) and pixel support circuitry 211. The photodiode 210 may be a buried photodiode currently used in a CMOS image sensor. In one example, pixel support circuit 211 includes a reset transistor 220, a Source Follower (SF) transistor 225, and a row select transistor 230, coupled to a pass transistor 215 and a photodiode 210 as shown. In another embodiment, not shown, the pixel support circuit 211 includes a reset transistor 220, a source follower transistor 225, a row select transistor 234 and a transfer transistor 215 disposed on a circuit chip, coupled to a photodiode 210. During operation, photo-charges generated by the photo-sensing element 210 are responsive to incident light during exposure. The transfer transistor 215 is connected to a transfer signal TX that controls the transfer transistor 215 to transfer the charge accumulated in the photodiode 210 to a floating diffusion region (FD) 217. When the photodiode 210 is the source of the transfer transistor 215, the floating diffusion region 217 is effectively the drain of the transfer transistor 215. In one embodiment, the pass transistor 215 may be a MOSFET (metal oxide semiconductor field effect transistor). A reset transistor 220 is connected between VDD and the floating diffusion region 217, in response to a reset signal RST to reset the sensor pixel circuit 200 (e.g., discharge or charge the floating diffusion region 217 and photodiode 210 to a present voltage). The floating diffusion region 217 is connected to the source of a source follower transistor 225. A source follower transistor 225 is connected between VDD and a row select transistor 230, amplifying the signal in response to the potential of the floating diffusion FD region 217. The row select transistor 230 connects the pixel circuit output from the source follower transistor 225 to the readout column, or bit line 235, in response to a row select control signal RS.
In one embodiment, in the pixel circuit described above, the photodiode 210 and the floating diffusion region 217 are reset by the temporarily active reset signal RST and the transfer control signal TX. When the transmission control signal TX is released, an accumulation window (e.g., an exposure phase) starts to act, and incident light causes electric charges to be generated in the photodiode 210. As the light in the photodiode 210 generates electrons that gradually accumulate, its voltage increases (the electrons are negative charges). The voltage or charge of the photodiode 210 represents the intensity incident to the photodiode 210 during exposure. At the end of the exposure, the RST signal is de-asserted, turning off the reset transistor 220 and isolating VDD from the floating diffusion region 217. The transfer control signal TX is active, connecting the photodiode 210 to the floating diffusion region 217. Charge is transferred from the photodiode 210 to the floating diffusion region 217 through the transfer transistor 215 such that the voltage of the floating diffusion region 217 is proportionally reduced by the photo-generated electrons accumulated on the photodiode 210 during exposure.
In an embodiment, referring to fig. 3, the CMOS image sensor provided in this embodiment may further include several oxide layers 303 over the top metal layers (e.g., the top dummy metal layers) of the peripheral logic region and the pixel region to suppress dark current and insulate.
In an embodiment, referring to fig. 3, the upper surface of the oxide layer of the peripheral logic region may be provided with a pad region 304, and the pad region 304 is used for electrical connection with other hardware. The metal layer Mn of the top layer of the peripheral logic region is electrically connected to the pad region 304 (not shown). Specifically, the metal layer Mn on the top layer of the peripheral logic region is connected to the pad region 304, and is electrically connected to other hardware.
In one embodiment, referring to fig. 3, an upper surface of the oxide layer of the pixel region may be provided with a microlens 305.
In one embodiment, a color filter (not shown in fig. 3) may be disposed under the microlens of the pixel region.
In one embodiment, the CMOS image sensor of the present invention is a front-illuminated (FSI) CMOS image sensor, and the plurality of metal layers and the dummy metal layer are located on the light receiving surface of the semiconductor substrate.
The utility model discloses CMOS image sensor that first embodiment provided includes peripheral logic district and pixel district, and peripheral logic district all includes the substrate and lies in the multilayer metal layer on the substrate with the pixel district, and the metal level height of pixel district is highly unanimous with the metal level of peripheral logic district, and includes the virtual metal level that is used as the structure compensation in the multilayer metal layer of pixel district. Therefore, the utility model discloses the CMOS image sensor that the first embodiment provided has increased the virtual metal layer and has made the metal level height of pixel area and the metal level highly uniform of peripheral logic district to make CMOS image sensor's stress distribution even, the dark current diminishes, and then can improve the problem that there is the shadow at the edge of the image that obtains under the high temperature condition.
Second embodiment:
fig. 7 is a schematic cross-sectional view of a CMOS image sensor according to a second embodiment of the present invention. Fig. 8 is a schematic cross-sectional view of an example of a CMOS image sensor according to a second embodiment of the present invention. For clarity of description of the CMOS image sensor provided by the second embodiment of the present invention, please refer to fig. 7 and 8.
The utility model provides a CMOS image sensor, including peripheral logic district and pixel district, peripheral logic district all includes the substrate and is located the multilayer metal layer on the substrate with the pixel district, and the metal level height of pixel district is highly unanimous with the metal level of peripheral logic district, and includes among the multilayer metal layer of pixel district as the virtual metal layer of structural compensation and sets up the electrical contact optimization metal level (for example, electrical contact optimization metal level M0 in figure 7) in the below of the metal level of bottom.
In one embodiment, the number of metal layers in the pixel region may be greater than the number of metal layers in the peripheral logic region, e.g., referring to fig. 7, the metal layers in the pixel region may have only one more electrical contact optimization metal layer than the metal layers in the peripheral logic region.
In an embodiment, the metal layer of each level of the remaining multi-layer metal layers of the pixel region may have the same structure as the metal layer of the corresponding level of the peripheral logic region, except for the electrical contact optimization metal layer in the pixel region. Further, a height of the metal layer of each of the remaining multi-layered metal layers of the pixel region may coincide with a height of the metal layer of the corresponding level of the peripheral logic region. For example, referring to fig. 8, the number of metal layers in the pixel region is 4, where the number of metal layers includes an electrical contact optimization metal layer M0, a bottom metal layer M1, an intermediate metal layer M2, and a top dummy metal layer M3 ', and the number of metal layers in the peripheral logic region is 3, where the number of metal layers includes a bottom metal layer M1, an intermediate metal layer M2, and a top metal layer M3, and in the CMOS image sensor, the structure and/or height of the bottom metal layer M1 in the pixel region may be the same as the bottom metal layer M1 in the peripheral logic region, the structure and/or height of the intermediate metal layer M2 in the pixel region may be the same as the middle metal layer M2 in the peripheral logic region, and the structure and/or height of the top dummy metal layer M3' in the pixel region may be the same as the top metal layer M3 in the peripheral logic.
In one embodiment, the plurality of metal layers in the pixel region and the peripheral logic region each include a chip interconnection layer and a metal wiring layer. For example, referring to fig. 8, the metal layer M1 at the bottom of the peripheral logic region may serve as a metal wiring layer for connecting with transistors in the substrate of the pixel region and/or transistors in the substrate of the peripheral logic region, and is connected with the metal layer M2 (wherein, the metal layer M2 may be a chip interconnection layer) at the upper level of the peripheral logic region, and further, the chip interconnection layer of the peripheral logic region may be connected with the metal layer M3 at the upper level and the metal layer M2 at the middle level of the pixel region; the metal layer M1 of the bottom layer of the pixel region serves as a metal wiring layer for connecting with transistors in the substrate of the pixel region and/or transistors in the substrate of the peripheral logic by the electrical contact optimization metal layer M0, and is connected with the metal layer M2 of the upper level of the pixel region (wherein, the metal layer M2 may be a chip interconnection layer). The metal layer M3 in the peripheral logic region is an off-chip connection layer and is used for connecting with a pad region on the top of a chip so as to connect with other components outside the chip.
Wherein the pixel region further comprises a plurality of transistors in the substrate.
In one embodiment, the plurality of transistors in the pixel region include various transistors (e.g., a transfer transistor TX, a reset transistor RST, a source follower transistor SF, a row select transistor RS, a conversion gain control transistor DCG, etc.) formed of an N-type doped layer in the substrate of the pixel region. Specifically, the N-type doped layer may be formed by doping an N-type ion material (e.g., N-type silicon) in a P-type silicon substrate.
Wherein the electrical contact optimization metal layer of the pixel region is similar to the bottom metal layer of the pixel region (e.g., the bottom metal layer M1 of the pixel region in fig. 6), and the connection between the transistors is realized. The electrical contact optimization metal layer can ensure better electrical contact with the transistor, thereby improving the sensitivity of the pixel area.
In one embodiment, not every transistor in the pixel area needs to be connected to an electrical contact optimized metal layer.
In an embodiment, the technical features of the CMOS image sensor provided in the second embodiment of the present invention and the technical features of the CMOS image sensor provided in the first embodiment of the present invention can be combined arbitrarily without contradiction, and will not be described herein again.
Therefore, the utility model discloses the virtual metal layer that the CMOS image sensor that the second embodiment provided increases can make the metal level height of pixel region and the metal level highly uniform of peripheral logic district to make CMOS image sensor's stress distribution even, the dark current diminishes, and then can improve the problem that there is the shadow at the edge of the image that obtains under the high temperature condition, in addition, the sensitivity that the pixel region can be improved to the electric contact optimization metal layer that the pixel region in the CMOS image sensor increases.
The third embodiment:
fig. 9 is a schematic flow chart of a method for manufacturing a CMOS image sensor according to a third embodiment of the present invention. For clearly describing the third embodiment of the present invention, please refer to fig. 9, which provides a method for fabricating a CMOS image sensor.
The utility model discloses a third embodiment provides a CMOS image sensor's manufacturing method, include:
s91, the semiconductor substrate is divided into a substrate of a peripheral logic region and a substrate of a pixel region.
And S92, processing the upper surface of the semiconductor substrate to form a plurality of metal layers on the upper surfaces of the substrate of the peripheral logic area and the substrate of the pixel area, wherein the height of the metal layer of the pixel area is consistent with that of the metal layer of the peripheral logic area, and the plurality of metal layers of the pixel area comprise a virtual metal layer used for structure compensation.
In one embodiment, in step S92, the step of processing the upper surface of the semiconductor substrate to form a plurality of metal layers on the upper surfaces of the substrate of the peripheral logic region and the substrate of the pixel region may include, but is not limited to: and optimizing through a chemical mechanical polishing process to ensure that the height of the metal layer of the pixel area is the same as that of the metal layer of the peripheral logic area.
In one embodiment, the dummy metal layer has a thickness of 4500 angstroms to 5500 angstroms. Preferably, the thickness of the dummy metal layer is 5000 angstroms.
In one embodiment, the number of metal layers in the pixel region is greater than or equal to the number of metal layers in the peripheral logic region.
In one embodiment, an electrical contact optimization metal layer is disposed below the bottom metal layer of the pixel region.
In one embodiment, the CMOS image sensor in this embodiment is a front-illuminated (FSI) CMOS image sensor, and the plurality of metal layers are located on the light receiving surface of the semiconductor substrate.
The utility model discloses the third embodiment provides a CMOS image sensor's manufacturing method, can increase virtual metal layer in CMOS image sensor's pixel area and make the metal level height of pixel area and the metal level highly uniform of peripheral logic district to make CMOS image sensor's stress distribution even, the dark current diminishes, and then can improve the problem that there is the shadow at the edge of the image that obtains under the high temperature condition.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of an element by the phrase "comprising an … …" does not exclude the presence of additional like elements in processes, methods, articles, or devices that include the element, and further, various embodiments of the present invention may have identically or differently named components, features, and elements, and their specific meanings need not be determined by their interpretation in such embodiments or by their further context in such embodiments.
It should be understood that, although the steps in the flowcharts in the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, in different orders, and may be performed alternately or at least partially with respect to other steps or sub-steps of other steps.
The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modification, equivalent replacement or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A CMOS image sensor comprises a peripheral logic area and a pixel area, wherein the peripheral logic area and the pixel area respectively comprise a substrate and a plurality of metal layers positioned on the substrate, and the CMOS image sensor is characterized in that:
the height of the metal layer of the pixel area is consistent with that of the metal layer of the peripheral logic area, and the multiple metal layers of the pixel area comprise a virtual metal layer used for structure compensation.
2. The CMOS image sensor of claim 1, wherein the number of metal layers of the pixel region is greater than or equal to the number of metal layers of the peripheral logic region.
3. The CMOS image sensor of claim 2, wherein a structure of the metal layer of each level of the peripheral logic region is the same as a structure of the metal layer of the corresponding level of the pixel region.
4. The CMOS image sensor of any one of claims 1-3, wherein a height of the metal layer of each level of the peripheral logic region coincides with a height of the metal layer of the corresponding level of the pixel region.
5. The CMOS image sensor of claim 4, wherein the pixel region and the peripheral logic region each include a chip interconnect layer and a metal wiring layer in the multi-metal layer.
6. The CMOS image sensor of claim 5, wherein an electrical contact optimized metal layer is disposed under the metal layer of the bottom layer of the pixel region.
7. The CMOS image sensor of claim 1, wherein the peripheral logic region and the pixel region each further comprise a plurality of transistors in a substrate;
wherein the plurality of transistors in the peripheral logic region comprise transistors formed from an N-type doped layer in the substrate of the peripheral logic region;
wherein the plurality of transistors in the pixel region include transistors formed from an N-type doped layer in a substrate of the pixel region.
8. The CMOS image sensor of claim 1, further comprising an oxide layer over the peripheral logic region and a metal layer of a top layer of the pixel region.
9. The CMOS image sensor according to claim 8, wherein an upper surface of the oxide layer of the pixel region is provided with a microlens.
10. The CMOS image sensor as claimed in claim 9, wherein a color filter is disposed under the microlens.
11. The CMOS image sensor according to claim 8, wherein an upper surface of the oxide layer of the peripheral logic region is provided with a pad region for electrical connection with an external component;
and the metal layer at the top layer of the peripheral logic area is electrically connected with the pad area.
12. The CMOS image sensor of claim 1, wherein the dummy metal layer has a thickness between 4500 angstroms and 5500 angstroms.
13. The CMOS image sensor of claim 1, wherein the dummy metal layer has a thickness of 5000 angstroms.
14. The CMOS image sensor as in claim 1, wherein the CMOS image sensor is a front-illuminated CMOS image sensor, and the plurality of metal layers are on the light-receiving surface of the substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113903754A (en) * | 2020-07-06 | 2022-01-07 | 思特威(上海)电子科技股份有限公司 | CMOS image sensor and manufacturing method thereof |
| CN114068327A (en) * | 2021-10-29 | 2022-02-18 | 深圳基本半导体有限公司 | Power semiconductor device and preparation process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113903754A (en) * | 2020-07-06 | 2022-01-07 | 思特威(上海)电子科技股份有限公司 | CMOS image sensor and manufacturing method thereof |
| CN114068327A (en) * | 2021-10-29 | 2022-02-18 | 深圳基本半导体有限公司 | Power semiconductor device and preparation process |
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