CN212723930U - Novel PSU redundancy management circuit - Google Patents
Novel PSU redundancy management circuit Download PDFInfo
- Publication number
- CN212723930U CN212723930U CN202021850776.XU CN202021850776U CN212723930U CN 212723930 U CN212723930 U CN 212723930U CN 202021850776 U CN202021850776 U CN 202021850776U CN 212723930 U CN212723930 U CN 212723930U
- Authority
- CN
- China
- Prior art keywords
- bmc
- psu
- cpld
- management circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229920002492 poly(sulfone) Polymers 0.000 claims description 63
- 230000003862 health status Effects 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 4
- 101150085905 DCP2 gene Proteins 0.000 claims description 3
- 101100031494 Schizosaccharomyces pombe (strain 972 / ATCC 24843) psu1 gene Proteins 0.000 claims description 3
- 101100422754 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sui1 gene Proteins 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 6
- 238000012544 monitoring process Methods 0.000 abstract description 6
- 238000013461 design Methods 0.000 abstract description 5
- 238000007726 management method Methods 0.000 description 25
- 230000002159 abnormal effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000036541 health Effects 0.000 description 3
- 238000011217 control strategy Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Images
Landscapes
- Hardware Redundancy (AREA)
Abstract
The utility model provides a novel redundant management circuit of PSU, the utility model discloses consider when BMC is down the machine state, the risk that PCU no management brought through taking over the management to PSU immediately when monitoring BMC work is unusual at CPLD to resume normal back at BMC, PSU management mode switches to BMC, and BMC can carry out the readback to the information that CPLD recorded in the unusual time simultaneously. By the aid of the redundancy design method, stability can be enhanced, the PSU is in a non-management state when the BMC is down, high-temperature risk of the PSU is avoided, stability of the PSU is improved, and stability of a server can be improved; and the BMC logs are completely recorded, when the BMC is down to reset, the CPLD monitors in time, and the BMC reads back the happy preference when resetting, so that the log records are complete.
Description
Technical Field
The utility model relates to a power supply circuit technical field, especially a novel redundant management circuit of PSU.
Background
With the continuous development of server technology, especially the rapid development of digital technology and application, the technology of each part of a computer has great progress, and as for a power supply, with the continuous expansion of the server market, the application field of the server is wider, and the application environment is more complex. Therefore, higher requirements are made on the load capacity, safety, expandability, versatility, and the like of the server power supply system.
The commonly used power management method comprises the following steps: the BMC acquires parameters such as PSU temperature and current through the PMBUS (I2C), regulates and controls the PSU fan according to the temperature, avoids overheating abnormality and influences the stability of the PSU and the server, but when the BMC is down, the PSU is temporarily in an unmanaged state, and small-probability problems such as overheating and overcurrent cannot be managed and monitored in time, and when the BMC is down, the BMC cannot respond any more and cannot record log files.
In order to ensure the stability of the power supply of the two-way server in the prior art, the general PSUs can be made into 1+1 redundancy, namely two PSUs, the BMC manages the two PSUs through one PMBUS, the power consumption, the temperature and the fan of the PSUs are monitored in real time, the working principle of the PSU is shown in figure 1, meanwhile, the redundancy of a communication line is considered, and the two PSUs can be managed by using the two PMBUSs in some designs, as shown in figure 2, but when the BMC is abnormal, the redundancy is not considered. When the BMC is down, the PSU is in a no-host management state, and the PSU fan can be adjusted without a host; the BMC can not acquire the PSU power consumption and monitor the abnormal alarm signal at the moment and act; the BMC cannot record logs in time, and the logs of the BMC and the system logs do not correspond to each other.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a novel redundant management circuit of PSU aims at solving and lacks the problem that redundant design leads to BMC unable to monitor PSU when unusual among the prior art, realizes improving PSU's stability, complete record monitoring information.
In order to achieve the technical purpose, the utility model provides a novel redundant management circuit of PSU, management circuit includes:
the BMC is connected to the CPLD through a Health _ Status signal and an I2C signal, and is also connected to the Switch chip through a BMC _ I2C signal;
the CPLD is connected with the Switch chip through a CPLD _ I2C signal and a cs signal;
the Switch chip is connected with two PSU chips.
Preferably, when the BMC is working normally, the I2C signal BMC _ I2C coming out directly from the BMC manages PSU1 and PSU2 via the Switch chip; when the BMC works abnormally, the I2C channels of the BMC and the PSUs are switched to be CPLD _ I2C signals of the CPLD to manage the two PSUs.
Preferably, the Switch chip model is SN74LVC1G3157 DRYR.
The utility model also provides a novel redundant management circuit of PSU, management circuit includes:
the BMC is connected to the CPLD through BMC _ I2C, Health _ Status and I2C signals;
the CPLD is signal connected to the two PSUs through CPLD _ I2C.
Preferably, when the BMC works normally, the CPLD performs direct connection processing inside, and the BMC directly manages the PSU; when the BMC works abnormally, the CPLD is converted from device to host, and the BMC is taken over to manage the work of the PSU.
The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:
compared with the prior art, the utility model discloses consider when the BMC is down the state, the risk that PSU no management brought provides neotype PSU redundant management method, promptly when CPLD is monitoring BMC work unusual, take over the management to PSU immediately to resume normal back at BMC, PSU administrative mode switches to BMC, and BMC can read back the information that CPLD recorded in unusual time simultaneously. By the aid of the redundancy design method, stability can be enhanced, the PSU is in a non-management state when the BMC is down, high-temperature risk of the PSU is avoided, stability of the PSU is improved, and stability of a server can be improved; and the BMC logs are completely recorded, when the BMC is down to reset, the CPLD monitors in time, and the BMC reads back the happy preference when resetting, so that the log records are complete.
Drawings
FIG. 1 is a schematic diagram of a single PMBUS management circuit according to the prior art;
FIG. 2 is a schematic diagram of a dual PMBUS management circuit according to the prior art;
fig. 3 is a schematic structural diagram of a novel PSU redundancy management circuit for CPLD and Switch collocation management according to the present invention;
fig. 4 is a schematic structural diagram of a novel PSU redundancy management circuit separately managed by a CPLD according to the present invention.
Detailed Description
In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.
The following describes the control circuit of an auxiliary source according to the present invention in detail with reference to the accompanying drawings.
As shown in fig. 3, the utility model discloses a novel redundant management circuit of PSU, management circuit includes:
the BMC is connected to the CPLD through a Health _ Status signal and an I2C signal, and is also connected to the Switch chip through a BMC _ I2C signal;
the CPLD is connected with the Switch chip through a CPLD _ I2C signal and a cs signal;
the Switch chip is connected with two PSU chips.
The CPLD monitors the working state of the BMC through a Health _ Status Health state signal of the BMC, the Health state signal is a 1Hz square wave signal when being normal, if the Health state signal is continuously high or low, the BMC is judged to be abnormal, after the BMC is detected to be abnormal, the CPLD resets the BMC through the GPIO, and the restarting process of the BMC FW is about 1 minute.
When the BMC works normally, an I2C signal BMC _ I2C which is directly sent out by the BMC directly manages the PSU1 and the PSU2 through the Switch chip, and when the CPLD monitors that the BMC works abnormally, the CPLD controls the change of the select signal level of the Switch chip and switches the I2C channel of the BMC and the PSU into a CPLD _ I2C signal of the CPLD to manage the two PSUs. And the CPLD records the time stamp when monitoring the PSU information so that the BMC can read back the record.
The content managed by the CPLD includes: reading information such as current and voltage, monitoring temperature, and regulating and controlling the rotation speed of a PSU fan, wherein the fan regulation and control strategy is the same as the BMC regulation and control strategy.
After the BMC is restarted and returns to normal, the CPLD recorded information in the abnormal BMC time is read through an I2C link which originally realizes CPLD information reading and FW upgrading. When the information recorded by the CPLD is read after the BMC is restarted, the protocol is not limited to the I2C protocol, and an SPI protocol or the like may be used.
The model of the Switch chip is SN74LVC1G3157 DRYR.
In other embodiments, the Switch chip may be removed and implemented separately using a CPLD. The BMC, I2C for managing PSUs, is also connected to the CPLD, so that the Switch chip can be omitted.
As shown in fig. 4, the circuit structure is as follows:
the BMC is connected to the CPLD through BMC _ I2C, Health _ Status and I2C signals;
the CPLD is signal connected to the two PSUs through CPLD _ I2C.
When the BMC works normally, the CPLD performs direct connection processing inside, the BMC directly manages the PSU, when the BMC works abnormally, the CPLD is switched from device to host to take over the work of the BMC for managing the PSU, and after the BMC works normally, the BMC is restored to the default state.
The utility model discloses consider when the BMC is down the state, the risk that PSU no management brought provides neotype PSU redundancy management method, promptly at CPLD when monitoring BMC work is unusual, takes over the management to PSU immediately to resume normal back at BMC, PSU management mode switches to BMC, and BMC can carry out the readback to the information that CPLD recorded in unusual time simultaneously. By the aid of the redundancy design method, stability can be enhanced, the PSU is in a non-management state when the BMC is down, high-temperature risk of the PSU is avoided, stability of the PSU is improved, and stability of a server can be improved; and the BMC logs are completely recorded, when the BMC is down to reset, the CPLD monitors in time, and the BMC reads back the happy preference when resetting, so that the log records are complete.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (5)
1. A novel PSU redundancy management circuit, the management circuit comprising:
the BMC is connected to the CPLD through a Health _ Status signal and an I2C signal, and is also connected to the Switch chip through a BMC _ I2C signal;
the CPLD is connected with the Switch chip through a CPLD _ I2C signal and a cs signal;
the Switch chip is connected with two PSU chips.
2. The novel PSU redundancy management circuit of claim 1, wherein when the BMC is working normally, the I2C signal BMC _ I2C coming out from the BMC directly manages PSU1 and PSU2 via Switch chip; when the BMC works abnormally, the I2C channels of the BMC and the PSUs are switched to be CPLD _ I2C signals of the CPLD to manage the two PSUs.
3. The PSU redundancy management circuit of claim 2, wherein the Switch chip model is SN74LVC1G3157 DRYR.
4. A novel PSU redundancy management circuit, the management circuit comprising:
the BMC is connected to the CPLD through BMC _ I2C, Health _ Status and I2C signals;
the CPLD is signal connected to the two PSUs through CPLD _ I2C.
5. The novel PSU redundancy management circuit according to claim 4, characterized in that when the BMC works normally, the CPLD performs through processing inside, and the BMC manages the PSU directly; when the BMC works abnormally, the CPLD is converted from device to host, and the BMC is taken over to manage the work of the PSU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021850776.XU CN212723930U (en) | 2020-08-28 | 2020-08-28 | Novel PSU redundancy management circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021850776.XU CN212723930U (en) | 2020-08-28 | 2020-08-28 | Novel PSU redundancy management circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212723930U true CN212723930U (en) | 2021-03-16 |
Family
ID=74924619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021850776.XU Active CN212723930U (en) | 2020-08-28 | 2020-08-28 | Novel PSU redundancy management circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212723930U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113204466A (en) * | 2021-04-29 | 2021-08-03 | 山东英信计算机技术有限公司 | Over-temperature protection method and electronic equipment |
-
2020
- 2020-08-28 CN CN202021850776.XU patent/CN212723930U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113204466A (en) * | 2021-04-29 | 2021-08-03 | 山东英信计算机技术有限公司 | Over-temperature protection method and electronic equipment |
| CN113204466B (en) * | 2021-04-29 | 2022-11-18 | 山东英信计算机技术有限公司 | Over-temperature protection method and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4723290B2 (en) | Disk array device and control method thereof | |
| US8656003B2 (en) | Method for controlling rack system using RMC to determine type of node based on FRU's message when status of chassis is changed | |
| EP1372076B1 (en) | Storage control system and method | |
| US7437585B2 (en) | Storage system and power control method therefor, adapter and power control method therefor, and storage controller and control method therefor | |
| US20110145620A1 (en) | Method of using power supply to perform far-end monitoring of electronic system | |
| CN111120383A (en) | Control method and control device for equipment fan, switch and storage medium | |
| CN212723930U (en) | Novel PSU redundancy management circuit | |
| US7045914B2 (en) | System and method for automatically providing continuous power supply via standby uninterrupted power supplies | |
| JP2005267111A (en) | Storage control system and method for controlling storage control system | |
| CN110985426B (en) | Fan control system and method for PCIE Switch product | |
| JP2023071968A (en) | Storage system, and method for switching operation mode of storage system | |
| US9760143B2 (en) | Switching module, related server device and power switching method | |
| WO2020238746A1 (en) | Log information processing system, log information processing method and apparatus, and switch | |
| CN115047954B (en) | Equipment heat dissipation control method, system, device, equipment and storage medium | |
| CN106844176A (en) | A kind of integrated processing method of the sensing data of multi-unit server | |
| JP2010267003A (en) | Programmable controller | |
| JPH10207586A (en) | Power-off control system for computer | |
| CN219204558U (en) | Network video recorder and network video recorder system | |
| JP2000020336A (en) | Duplex communication system | |
| CN116204502B (en) | NAS storage service method and system with high availability | |
| JP2836336B2 (en) | Power off control method | |
| CN209233849U (en) | Environmental monitoring system | |
| EP2083537B1 (en) | Data network and method of controlling thereof | |
| Wang et al. | A dual BIOS safe startup method based on national devices | |
| CN114610242A (en) | Method, system and device for improving system availability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |