CN212723129U - Intelligent line load and fault detection device - Google Patents
Intelligent line load and fault detection device Download PDFInfo
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- CN212723129U CN212723129U CN202021068155.6U CN202021068155U CN212723129U CN 212723129 U CN212723129 U CN 212723129U CN 202021068155 U CN202021068155 U CN 202021068155U CN 212723129 U CN212723129 U CN 212723129U
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Abstract
The utility model discloses an intelligence circuit load and fault detection device, detection device is including controller, LCD display module, frequency sweep circuit, modulate circuit and AD sampling circuit, controller control frequency sweep circuit produces the frequency sweep signal, the frequency sweep circuit is handled frequency sweep signal through being measured the circuit transmission to modulate circuit in, signal transmission after the modulate circuit will handle is to the AD sampling circuit in, AD sampling circuit is according to the signal after handling, and the sampling acquires voltage data, and will voltage data sends and handles in the controller, the controller converts voltage data, and send to show among the LCD display module. The utility model discloses detection device except can accurately discern the network structure of line load, measure load element's impedance value, in time carry out the short circuit and open a way fault alarm, can also be under the short circuit condition the distance of automatic measure short-circuit point to absolute error control has been within 1 cm.
Description
Technical Field
The utility model relates to an electronic circuit detects technical field, especially relates to an intelligent line load and fault detection device.
Background
Line load and fault detection have wide practical application in electronic products and communication networks, various faults often occur in long-distance line transmission, simple faults such as line short circuit or open circuit, and more complex conditions can cause various combinations of capacitive loads and inductive loads. These faults are the main causes of errors in the transmission of the line. Conventional line testing devices currently separate the detection of line loads from faults.
For the load detection of a line, few instruments can automatically detect a load network structure, generally, the electrical property of a detected load is manually selected and then LCR measurement is carried out, and pure electric loads, inductive loads and capacitive loads can be divided according to the electrical property. Particularly, no instrument capable of distinguishing series-parallel combination of three loads of a resistor, a capacitor and an inductor is available in the market. In addition, for the measurement of the original component value of the load, the traditional instrument uses a control relay to select different measuring ranges (such as a multimeter), and is not intelligent enough.
In addition, for the fault detection part of the line, in addition to being capable of distinguishing short circuit, open circuit and normal operation of the line, a device capable of accurately measuring a short circuit point is not found in the market.
SUMMERY OF THE UTILITY MODEL
Utility model purpose: in the load detection to current circuit, the unable automatic accurate problem that detects load network structure of instrument, the utility model provides an intelligent line load and fault detection device.
The technical scheme is as follows: for realizing the purpose of the utility model, the utility model adopts the technical proposal that:
an intelligent line load and fault detection device comprises a controller, an LCD display module, a frequency sweep circuit, a conditioning circuit and an AD sampling circuit, wherein the controller controls the frequency sweep circuit to generate a frequency sweep signal, the frequency sweep circuit sends the frequency sweep signal to the conditioning circuit through a tested line for processing, the conditioning circuit sends the processed signal to the AD sampling circuit, the AD sampling circuit samples and acquires voltage data according to the processed signal and sends the voltage data to the controller for processing, and the controller converts the voltage data and sends the voltage data to the LCD display module for display;
the conditioning circuit comprises a first conditioning circuit and a second conditioning circuit, wherein the first conditioning circuit is used for judging the state of a tested line according to a sweep frequency signal sent by the tested line and sending a processed signal to the second conditioning circuit or an AD sampling circuit according to a judgment result;
the second conditioning circuit is used for receiving the processing signal sent by the first conditioning circuit, carrying out secondary processing on the processing signal and sending the secondary processed processing signal to the AD sampling circuit.
Furthermore, the first conditioning circuit comprises a voltage division circuit and an effective value detection circuit, wherein the voltage division circuit is used for carrying out voltage division processing on the output voltage of the tested circuit and sending the voltage signal subjected to voltage division processing to the effective value detection circuit;
the effective value detection circuit is used for detecting the effective value of the voltage signal subjected to the voltage division processing, judging the state of the tested line according to the effective value signal, and sending the effective value signal to the second conditioning circuit or the AD sampling circuit according to the judgment result.
Further, the valid value detection circuit includes a third chip U3, a first operational amplifier a1, a second operational amplifier a2, and a third pin bank J3, wherein a buffer port of the third chip U3 is electrically connected to an input terminal of a sixth capacitor C6, an output terminal of the sixth capacitor C6 is grounded, a COMMON port of the third chip U3 is grounded, a dei port and an RMSOUT port of the third chip U3 are both electrically connected to an input terminal of a twenty-first resistor R21, a Cav port of the third chip U3 is electrically connected to an input terminal of a twenty-first resistor R21 through a seventh capacitor C7, an output terminal of the twenty-first resistor R21 is electrically connected to an input terminal of a sixth capacitor C6 through a twelfth resistor R22, a VS-port of the third chip U3 is grounded through an eighth capacitor C8, and a VS + port of the third chip U3 is grounded through a ninth capacitor C9;
the VIN port of the third chip U3 is electrically connected to the output terminal of a first operational amplifier a1 through a nineteenth resistor R19, the non-inverting input terminal of the first operational amplifier a1 is electrically connected to the output terminal of a sixteenth resistor R16, the input terminal of the sixteenth resistor R16 is electrically connected to the output terminal of a fifteenth resistor R15 and the P4 port of the SMA socket, the input terminal of the fifteenth resistor R15 and the P4 port of the SMA socket are both grounded, the inverting input terminal of the first operational amplifier a1 is electrically connected to the output terminal of the first operational amplifier a1 through an eighteenth resistor R18, and the inverting input terminal of the first operational amplifier a1 is grounded through a seventeenth resistor R17;
the BUFFOUT port of the third chip U3 is electrically connected to the input terminal of a tenth capacitor C10 and the non-inverting input terminal of the second operational amplifier a2 through a twenty-third resistor R23, the output terminal of the tenth capacitor C10 is electrically connected to the input terminal of a sixth capacitor C6 through a twenty-second resistor R22, the inverting input terminal of the second operational amplifier a2 is electrically connected to the output terminal of the second operational amplifier a2, the output terminal of the second operational amplifier a2 is electrically connected to the 2-port of the third pin bank J3, and the 1-port of the third pin bank J3 is grounded.
The second conditioning circuit comprises a precision bridge loop and an instrument amplifying circuit, wherein the precision bridge loop is used for measuring the resistance value of a short-circuit wire in a tested line according to an effective value signal and sending the resistance value signal to the instrument amplifying circuit;
the instrument amplifying circuit is used for amplifying the resistance value signal and sending the amplified resistance value signal to the AD sampling circuit.
Further, the meter amplifying circuit comprises a second chip U2, an RG port of the second chip U2 is electrically connected to another RG port of the second chip U2 through an eighth resistor R8, an IN-port of the second chip U2 is electrically connected to an input terminal of a ninth resistor R9 and a P1 port of the SMA socket, an output terminal of the ninth resistor R9 and the P1 port of the SMA socket are both grounded, an IN + port of the second chip U2 is electrically connected to an input terminal of a tenth resistor R10 and the P2 port of the SMA socket, and an output terminal of the tenth resistor R10 and the P2 port of the SMA socket are both grounded;
the OUT port of the second chip U2 is electrically connected to the P3 port of the SMA socket through a fourteenth resistor R14, the P3 port of the SMA socket is grounded, the REF port of the second chip U2 is electrically connected to the input end of an eleventh resistor R11 and the input end of a twelfth resistor R12, the output end of the eleventh resistor R11 is grounded, and the output end of the twelfth resistor R12 is electrically connected to a thirteenth resistor R13.
Further, the frequency sweeping circuit includes a first chip U1 and a first crystal oscillator CY1, a DACRset port of the first chip U1 is grounded through a fifth resistor R5, a DACBP port of the first chip U1 is electrically connected to an AVDD port of the first chip U1 through a fifth capacitor C5, an IOUT1 port of the first chip U1 is electrically connected to an input terminal of a sixth resistor R6 and a1 port of a first pin bank J1, an IOUT b port of the first chip U1 is electrically connected to an input terminal of a second resistor R2, another IOUT1 port of the first chip U1 is electrically connected to an input terminal of a third resistor R3, and another IOUT1 port of the first chip U1 is electrically connected to an input terminal of a seventh resistor R7 and a2 port of a second pin bank J2;
an output end of the second resistor R2 is electrically connected to an output end of the third resistor R3, an output end of the sixth resistor R6 and an output end of the seventh resistor R7, an output end of the second resistor R2, an output end of the third resistor R3, an output end of the sixth resistor R6 and an output end of the seventh resistor R7 are all grounded, and a 2-port of the first pin bank J1 is electrically connected to a 1-port of the second pin bank J2;
the PLLFILLTER port of the first chip U1 is electrically connected to the AVDD port of the first chip U1 through a first resistor R1 and a first capacitor C1, the REFCLK port of the first chip U1 is electrically connected to the 2 port of the first crystal CY1, the 1 port of the first crystal CY1 is electrically connected to the DVDD port of the first chip U1, and the 3 port and the 4 port of the first crystal CY1 are both grounded.
Furthermore, the AD sampling circuit comprises a fourth chip U4 and a fourth chip U4
The port is electrically connected with the input end of a twenty-fourth resistor R24 and the input end of a twenty-fifth resistor R25, the output end of the twenty-fifth resistor R25 is grounded, and the VDRIVE port of the fourth chip U4 is grounded through a fifteenth capacitor C15;
the REGCAP port of the fourth chip U4 is grounded through a twelfth capacitor C12, the other REGCAP port of the fourth chip U4 is grounded through an eleventh capacitor C11, the REFIN/refut port of the fourth chip U4 is grounded through a thirteenth capacitor C13, and the refcap port of the fourth chip U4 is grounded through a fourteenth capacitor C14.
Has the advantages that: compared with the prior art, the technical scheme of the utility model following beneficial technological effect has:
the utility model discloses a detection device except can accurately discern the network structure of line load, measure the impedance value of load component, in time carry out the short circuit and open a way fault alarm, can also be under the short circuit condition the distance of automatic measure short circuit point to absolute error control has been within 1cm, and it is more intelligent for the mode that the tradition carries out the measurement through the relay switching range, the utility model discloses a detection device more has the novelty.
Drawings
FIG. 1 is a schematic view of the connection of the detecting device of the present invention;
fig. 2 is a schematic circuit connection diagram of the frequency sweeping circuit of the present invention;
FIG. 3 is a schematic diagram of the circuit connection of the instrument amplification circuit of the present invention;
fig. 4 is a schematic circuit diagram of the effective value detection circuit of the present invention;
fig. 5 is a schematic diagram of the circuit connection of the AD sampling circuit of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings in the embodiments of the present invention are combined below to clearly and completely describe the technical solutions in the embodiments of the present invention. The described embodiments are some, but not all embodiments of the invention. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention.
Example 1
Referring to fig. 1, the present embodiment provides an intelligent line load and fault detection apparatus, which includes a controller, an LCD display module, a frequency sweep circuit, a conditioning circuit, and an AD sampling circuit. The detection device can accurately identify the network structure of the line load, measure the impedance value of a load element, perform short-circuit and open-circuit fault alarm in time, and can also automatically measure the distance of a short-circuit point under the condition of short circuit, and the absolute error is controlled within 1 cm. The controller controls the frequency sweeping circuit to generate frequency sweeping signals, the frequency sweeping circuit sends the frequency sweeping signals to the conditioning circuit through the tested circuit to be processed, the conditioning circuit sends the processed signals to the AD sampling circuit, the AD sampling circuit samples and obtains voltage data according to the processed signals, the voltage data are sent to the controller to be processed, and the controller converts the voltage data and sends the voltage data to the LCD display module to be displayed.
In this embodiment, the conditioning circuit includes a first conditioning circuit and a second conditioning circuit, where the first conditioning circuit is configured to determine a state of the measured line according to a sweep frequency signal sent by the measured line, and send a processed signal to the second conditioning circuit or the AD sampling circuit according to a determination result.
The second conditioning circuit is used for receiving the processing signal sent by the first conditioning circuit, carrying out secondary processing on the processing signal and sending the secondary processed processing signal to the AD sampling circuit.
Specifically, according to the knowledge of high-frequency electronic circuits, different load networks generate different amplitude-frequency responses to the frequency sweep signal, and a total of 13 different load conditions can be distinguished by combining different amplitude-frequency characteristics. Therefore, in the detection device of this embodiment, the controller first controls the frequency sweep circuit to generate a frequency sweep signal, and when the frequency sweep signal passes through the voltage division of the line to be detected, different amplitude-frequency responses are generated due to different loads, then the first conditioning circuit converts the waveform parameters into voltage data, and finally the AD sampling circuit reads the voltage data and transmits the voltage data to the controller, and the data processing and analysis are performed inside the controller.
Referring to fig. 2, fig. 2 is a circuit connection diagram of the frequency sweep circuit in this embodiment. Specifically, the frequency sweeping circuit comprises a first chip U1 and a first crystal oscillator CY1, a DACRset port of a first chip U1 is grounded through a fifth resistor R5, a DACBP port of the first chip U1 is electrically connected to an AVDD port of a first chip U1 through a fifth capacitor C5, an IOUT1 port of the first chip U1 is electrically connected to an input terminal of a sixth resistor R6 and a1 port of a first pin bank J1, an IOUT b port of a first chip U1 is electrically connected to an input terminal of a second resistor R2, another IOUT1 port of the first chip U1 is electrically connected to an input terminal of a third resistor R3, and another IOUT1 port of the first chip U1 is electrically connected to an input terminal of a seventh resistor R7 and a2 port of a second pin bank J2.
The output end of the second resistor R2 is electrically connected to the output end of the third resistor R3, the output end of the sixth resistor R6 and the output end of the seventh resistor R7, meanwhile, the output end of the second resistor R2, the output end of the third resistor R3, the output end of the sixth resistor R6 and the output end of the seventh resistor R7 are all grounded, and the 2 port of the first row of pins J1 is electrically connected to the 1 port of the second row of pins J2.
A PLL FILLTER port of the first chip U1 is electrically connected to an AVDD port of the first chip U1 through the first resistor R1 and the first capacitor C1, a REFCLK port of the first chip U1 is electrically connected to a2 port of the first crystal CY1, a1 port of the first crystal CY1 is electrically connected to a DVDD port of the first chip U1, and a 3 port and a 4 port of the first crystal CY1 are both grounded.
Specifically, the first chip U1 in the frequency sweeping circuit selects a DDS chip with model AD9854, which has a frequency resolution of 48 bits, and even under a clock of 300MHz, the frequency resolution can still reach 1 μ Hz. Meanwhile, 17bit phase truncation can ensure that no spurious waveform is output, the-1 dB bandwidth is 70M, and the-dB bandwidth can be reached when the-1 dB bandwidth is 100M, so that the bandwidth used by the frequency sweeping circuit of the embodiment is basically not attenuated.
In this embodiment, the first conditioning circuit includes a voltage divider circuit and an effective value detection circuit. The voltage division circuit is used for carrying out voltage division processing on the output voltage of the tested circuit and sending the voltage signal subjected to voltage division processing to the effective value detection circuit. The effective value detection circuit is used for detecting the effective value of the voltage signal subjected to the voltage division processing, judging the state of the detected line according to the effective value signal, and sending the effective value signal to the second conditioning circuit or the AD sampling circuit according to the judgment result.
Referring to fig. 4, fig. 4 is a circuit connection diagram of the effective value detection circuit in the present embodiment. Specifically, the valid value detection circuit includes a third chip U3, a first operational amplifier a1, a second operational amplifier a2, and a third pin bank J3. The BUFFIN port of the third chip U3 is electrically connected with the input end of a sixth capacitor C6, the output end of the sixth capacitor C6 is grounded, the COMMON port of the third chip U3 is grounded, both the DENI port and the RMSOUT port of the third chip U3 are electrically connected with the input end of a twenty-first resistor R21, the Cav port of the third chip U3 is electrically connected with the input end of the twenty-first resistor R21 through a seventh capacitor C7, the output end of the twenty-first resistor R21 is electrically connected with the input end of the sixth capacitor C6 through a twenty-second resistor R22, the VS-port of the third chip U3 is grounded through an eighth capacitor C8, and the VS + port of the third chip U3 is grounded through a ninth capacitor C9.
The VIN port of the third chip U3 is electrically connected to the output terminal of the first operational amplifier a1 through a nineteenth resistor R19, the non-inverting input terminal of the first operational amplifier a1 is electrically connected to the output terminal of a sixteenth resistor R16, the input terminal of the sixteenth resistor R16 is electrically connected to the output terminal of a fifteenth resistor R15 and the P4 port of the SMA socket, the input terminal of the fifteenth resistor R15 and the P4 port of the SMA socket are both grounded, the inverting input terminal of the first operational amplifier a1 is electrically connected to the output terminal of the first operational amplifier a1 through an eighteenth resistor R18, and the inverting input terminal of the first operational amplifier a1 is grounded through a seventeenth resistor R17.
The BUFFOUT port of the third chip U3 is electrically connected to the input terminal of the tenth capacitor C10 and the non-inverting input terminal of the second operational amplifier a2 through a twenty-third resistor R23, the output terminal of the tenth capacitor C10 is electrically connected to the input terminal of the sixth capacitor C6 through a twenty-second resistor R22, the inverting input terminal of the second operational amplifier a2 is electrically connected to the output terminal of the second operational amplifier a2, the output terminal of the second operational amplifier a2 is electrically connected to the 2-port of the third pin bank J3, and the 1-port of the third pin bank J3 is grounded.
Specifically, the third chip U3 in the effective value detection circuit selects a high-precision root-mean-square direct-current converter chip with the model AD637, and the effective value range of the input signal of the third chip U3 is up to 7V. When the effective value of the input signal is 3V, the error of the chip in the range of 0-2MHz is 2%, and the error in the range of 2MHz-4Hz is 10%. The input and output relationship under the condition of the sine wave is as follows:
wherein: voutIs the corresponding output in the case of a sine wave, VinThe corresponding input in the case of a sine wave.
In this embodiment, the second conditioning circuit includes a precision bridge circuit and an instrument amplifier circuit. The precise bridge loop is used for measuring the resistance value of a short-circuit wire in a measured line according to the effective value signal and sending the measured resistance value signal to the instrument amplifying circuit. The instrument amplifying circuit is used for amplifying the resistance value signal and sending the amplified resistance value signal to the AD sampling circuit.
Referring to fig. 3, fig. 3 is a circuit connection diagram of the instrument amplification circuit in the present embodiment. Specifically, the instrument amplification circuit comprises a second chip U2, wherein an RG port of the second chip U2 is electrically connected with another RG port of the second chip U2 through an eighth resistor R8, an IN-port of the second chip U2 is electrically connected with an input end of a ninth resistor R9 and a P1 port of an SMA socket, an output end of the ninth resistor R9 and the P1 port of the SMA socket are both grounded, an IN + port of the second chip U2 is electrically connected with an input end of a tenth resistor R10 and the P2 port of the SMA socket, and an output end of the tenth resistor R10 and the P2 port of the SMA socket are both grounded.
The OUT port of the second chip U2 is electrically connected with the P3 port of the SMA socket through a fourteenth resistor R14, the P3 port of the SMA socket is grounded, the REF port of the second chip U2 is electrically connected with the input end of an eleventh resistor R11 and the input end of a twelfth resistor R12, the output end of the eleventh resistor R11 is grounded, and the output end of the twelfth resistor R12 is electrically connected with a thirteenth resistor R13.
Specifically, the model of the second chip U2 in the instrument amplifying circuit is an AD620 chip, and the gain range of the AD620 chip is 1-10000, so that the design requirement of 500 times of gain can be met.
Referring to fig. 5, fig. 5 is a circuit connection diagram of the AD sampling circuit in this embodiment. Specifically, the AD sampling circuit comprises a fourth chip U4 and a fourth chip U4
The port is electrically connected with the input end of the twenty-fourth resistor R24 and the input end of the twenty-fifth resistor R25, the output end of the twenty-fifth resistor R25 is grounded, and the VDRIVE port of the fourth chip U4 is grounded through a fifteenth capacitor C15.
The REGCAP port of the fourth chip U4 is grounded through a twelfth capacitor C12, another REGCAP port of the fourth chip U4 is grounded through an eleventh capacitor C11, the REFIN/refut port of the fourth chip U4 is grounded through a thirteenth capacitor C13, and the refcap port of the fourth chip U4 is grounded through a fourteenth capacitor C14.
Specifically, the model of a fourth chip U4 in the AD sampling circuit is an AD7606-4 chip, the AD7606-4 chip is a 16-bit and 4-channel synchronous sampling analog-digital data acquisition system, and an analog input clamping protection, a second-order anti-aliasing filter, a tracking and holding amplifier, a 16-bit charge redistribution successive approximation type analog-digital converter, a digital filter, a 2.5V reference voltage source, a buffer and a high-speed serial and parallel interface are integrated in the AD7606-4 chip.
The present invention and its embodiments have been described in an illustrative manner, and not in a limiting sense, and it is to be understood that only one of the embodiments of the invention has been shown in the drawings and that the actual construction and process are not limited thereto. Therefore, if the person skilled in the art receives the teaching of the present invention, the technical scheme and the embodiments similar to the above technical scheme are not creatively designed without departing from the spirit of the present invention, and all of the technical scheme and the embodiments belong to the protection scope of the present invention.
Claims (7)
1. An intelligent line load and fault detection device is characterized by comprising a controller, an LCD display module, a frequency sweep circuit, a conditioning circuit and an AD sampling circuit, wherein the controller controls the frequency sweep circuit to generate frequency sweep signals, the frequency sweep circuit sends the frequency sweep signals to the conditioning circuit through a tested line for processing, the conditioning circuit sends the processed signals to the AD sampling circuit, the AD sampling circuit samples and acquires voltage data according to the processed signals and sends the voltage data to the controller for processing, and the controller converts the voltage data and sends the voltage data to the LCD display module for display;
the conditioning circuit comprises a first conditioning circuit and a second conditioning circuit, wherein the first conditioning circuit is used for judging the state of a tested line according to a sweep frequency signal sent by the tested line and sending a processed signal to the second conditioning circuit or an AD sampling circuit according to a judgment result;
the second conditioning circuit is used for receiving the processing signal sent by the first conditioning circuit, carrying out secondary processing on the processing signal and sending the secondary processed processing signal to the AD sampling circuit.
2. An intelligent line load and fault detection device according to claim 1, wherein the first conditioning circuit comprises a voltage divider circuit and an effective value detection circuit, the voltage divider circuit is configured to divide the output voltage of the circuit under test and send the voltage signal after the voltage division to the effective value detection circuit;
the effective value detection circuit is used for detecting the effective value of the voltage signal subjected to the voltage division processing, judging the state of the tested line according to the effective value signal, and sending the effective value signal to the second conditioning circuit or the AD sampling circuit according to the judgment result.
3. The intelligent line load and fault detection device of claim 2, wherein the valid value detection circuit comprises a third chip U3, a first operational amplifier A1, a second operational amplifier A2 and a third pin bank J3, the BUFF IN port of the third chip U3 is electrically connected to the input terminal of a sixth capacitor C6, the output terminal of the sixth capacitor C6 is grounded, the COMMON port of the third chip U3 is grounded, the DENI port and the RMS OUT port of the third chip U3 are electrically connected to the input terminal of a twenty-first resistor R21, the Cav port of the third chip U3 is electrically connected to the input terminal of a twenty-first resistor R21 through a seventh capacitor C7, the output terminal of the twenty-first resistor R21 is electrically connected to the input terminal of a sixth capacitor C6 through a twelfth resistor R22, the VS-32 port of the third chip U3 is grounded through an eighth capacitor C8, the VS + port of the third chip U3 is grounded through a ninth capacitor C9;
the VIN port of the third chip U3 is electrically connected to the output terminal of a first operational amplifier a1 through a nineteenth resistor R19, the non-inverting input terminal of the first operational amplifier a1 is electrically connected to the output terminal of a sixteenth resistor R16, the input terminal of the sixteenth resistor R16 is electrically connected to the output terminal of a fifteenth resistor R15 and the P4 port of the SMA socket, the input terminal of the fifteenth resistor R15 and the P4 port of the SMA socket are both grounded, the inverting input terminal of the first operational amplifier a1 is electrically connected to the output terminal of the first operational amplifier a1 through an eighteenth resistor R18, and the inverting input terminal of the first operational amplifier a1 is grounded through a seventeenth resistor R17;
the BUFF OUT port of the third chip U3 is electrically connected to the input terminal of a tenth capacitor C10 and the non-inverting input terminal of the second operational amplifier a2 through a twenty-third resistor R23, the output terminal of the tenth capacitor C10 is electrically connected to the input terminal of a sixth capacitor C6 through a twenty-second resistor R22, the inverting input terminal of the second operational amplifier a2 is electrically connected to the output terminal of the second operational amplifier a2, the output terminal of the second operational amplifier a2 is electrically connected to the 2-port of the third pin bank J3, and the 1-port of the third pin bank J3 is grounded.
4. An intelligent line load and fault detection device according to claim 1, 2 or 3, wherein the second conditioning circuit comprises a precision bridge circuit and an instrument amplification circuit, the precision bridge circuit is used for measuring the resistance value of a short-circuit wire in a measured line according to an effective value signal and sending the resistance value signal to the instrument amplification circuit;
the instrument amplifying circuit is used for amplifying the resistance value signal and sending the amplified resistance value signal to the AD sampling circuit.
5. An intelligent line load and fault detection device as claimed IN claim 4, wherein the instrument amplification circuit comprises a second chip U2, the RG port of the second chip U2 is electrically connected to another RG port of the second chip U2 through an eighth resistor R8, the IN-port of the second chip U2 is electrically connected to the input terminal of a ninth resistor R9 and the P1 port of the SMA socket, the output terminal of the ninth resistor R9 and the P1 port of the SMA socket are both grounded, the IN + port of the second chip U2 is electrically connected to the input terminal of a tenth resistor R10 and the P2 port of the SMA socket, and the output terminal of the tenth resistor R10 and the P2 port of the SMA socket are both grounded;
the OUT port of the second chip U2 is electrically connected to the P3 port of the SMA socket through a fourteenth resistor R14, the P3 port of the SMA socket is grounded, the REF port of the second chip U2 is electrically connected to the input end of an eleventh resistor R11 and the input end of a twelfth resistor R12, the output end of the eleventh resistor R11 is grounded, and the output end of the twelfth resistor R12 is electrically connected to a thirteenth resistor R13.
6. An intelligent line load and fault detection device as claimed in claim 5, wherein the frequency sweep circuit comprises a first chip U1 and a first crystal CY1, the DAC Rset port of the first chip U1 is grounded through a fifth resistor R5, the DACBP port of the first chip U1 is electrically connected to the AVDD port of the first chip U1 through a fifth capacitor C5, the IOUT1 port of the first chip U1 is electrically connected to the input terminal of a sixth resistor R6 and the 1 port of the first pin bank J1, the IOUTB port of the first chip U1 is electrically connected to the input terminal of a second resistor R2, another IOUTB port of the first chip U1 is electrically connected to the input terminal of a third resistor R3, and another IOUT1 port of the first chip U1 is electrically connected to the input terminal of a seventh resistor R7 and the 2 port of the second pin bank J2;
an output end of the second resistor R2 is electrically connected to an output end of the third resistor R3, an output end of the sixth resistor R6 and an output end of the seventh resistor R7, an output end of the second resistor R2, an output end of the third resistor R3, an output end of the sixth resistor R6 and an output end of the seventh resistor R7 are all grounded, and a 2-port of the first pin bank J1 is electrically connected to a 1-port of the second pin bank J2;
the PLL FILLTER port of the first chip U1 is electrically connected to the AVDD port of the first chip U1 through a first resistor R1 and a first capacitor C1, the REFCLK port of the first chip U1 is electrically connected to the 2 port of the first crystal CY1, the 1 port of the first crystal CY1 is electrically connected to the DVDD port of the first chip U1, and the 3 port and the 4 port of the first crystal CY1 are both grounded.
7. The device as claimed in claim 6, wherein the AD sampling circuit comprises a fourth chip U4, and the fourth chip U4
The port is electrically connected with the input end of the twenty-fourth resistor R24 and the twentieth resistorAn input end of a fifth resistor R25, an output end of the twenty-fifth resistor R25 is grounded, and a VDRIVE port of the fourth chip U4 is grounded through a fifteenth capacitor C15;
the REGCAP port of the fourth chip U4 is grounded through a twelfth capacitor C12, the other REGCAP port of the fourth chip U4 is grounded through an eleventh capacitor C11, the REFIN/refut port of the fourth chip U4 is grounded through a thirteenth capacitor C13, and the refcap port of the fourth chip U4 is grounded through a fourteenth capacitor C14.
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| CN202021068155.6U CN212723129U (en) | 2020-06-11 | 2020-06-11 | Intelligent line load and fault detection device |
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| CN202021068155.6U CN212723129U (en) | 2020-06-11 | 2020-06-11 | Intelligent line load and fault detection device |
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Effective date of registration: 20221207 Address after: Room 307, Building 3, No. 1128, Wuzhong Road, Minhang District, Shanghai, 201103 Patentee after: Shanghai Fumeidi Engineering Technology Co.,Ltd. Address before: No.219, ningliu Road, Jiangbei new district, Nanjing, Jiangsu Province, 210032 Patentee before: Nanjing University of Information Science and Technology |