CN212694306U - Digital LDO circuit for reducing limit loop oscillation - Google Patents
Digital LDO circuit for reducing limit loop oscillation Download PDFInfo
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- CN212694306U CN212694306U CN202022185600.3U CN202022185600U CN212694306U CN 212694306 U CN212694306 U CN 212694306U CN 202022185600 U CN202022185600 U CN 202022185600U CN 212694306 U CN212694306 U CN 212694306U
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Abstract
The utility model provides a digital LDO circuit for reducing limit loop oscillation, which comprises a digital LDO circuit, an LCO detection circuit and an LCO reduction circuit which are connected in sequence, wherein the digital LDO circuit is connected with the LDC reduction circuit; the LCO detection circuit is used for comparing the output voltage of the digital LDO circuit with the maximum overshoot voltage and controlling the LCO reduction circuit to be started according to the comparison result; when the LCO reduction circuit is started, the output voltage is restrained from rising, and limit loop oscillation is reduced. The circuit is simple in structure, excessive theoretical analysis is not needed to determine parameters of devices in the LCO reduction circuit, the LCO pretreatment mode does not need to be set for analysis of nodes in the circuit, and the circuit is very convenient to use.
Description
Technical Field
The utility model relates to a digital LDO circuit technical field, concretely relates to reduce digital LDO circuit of limit loop oscillation.
Background
With the appearance of the digital LDO, the advantages of the digital LDO gradually attract people's attention, and the digital LDO has the advantages of low-voltage working characteristics, high precision, stable output, process variability and the like, so that the digital LDO is widely applied to a low-input high-precision high-efficiency power management system. The traditional digital LDO consists of a clock comparator, a digital control part based on a bidirectional shift register and a switch array. The clock comparator is used for comparing the output voltage VOUT with the reference voltage VREF and providing a comparison result CMPout to the bidirectional shift register, controlling a shift direction sel of the register. The bidirectional shift register controls the conducting number of the switch array, and plays a role in adjusting output voltage. The switch array is composed of PMOS tubes with the same size, and the switched-on switch tubes work in a linear region under normal work to realize the low-voltage working characteristic of the digital LDO. The load capacitance at the output end is used for reducing the ripple of the output voltage. Conventional digital LDOs generate limit loop oscillations (i.e., LCO) in steady state, which increases the power consumption of the system. In order to solve the problem of the LCO, the mode of the LCO is reduced to the mode 1 by adding a feed-forward path between the output end of the comparator and the output end of the system based on the traditional digital LDO structure, so that the amplitude of the LCO can be reduced remarkably, the structure is simple, and the effect is obvious. However, the disadvantages of this way of reducing LCO are: firstly, the modeling process needs to be carried out on the whole circuit, and the model M parameter of the LCO and the proportionality coefficient beta of the size of the auxiliary tube relative to the main array switch tube can be obtained through a large number of theoretical calculations. Second, mode 1 LCO cannot be realized in the conventional structure, and mode 1 LCO can be realized in the structure with the feed-forward path added, but it is necessary to reasonably match the phase and oscillation frequency of the output of each node in the system.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a reduce digital LDO circuit of limit loop oscillation for solve and need a large amount of theoretical calculations and carry out reasonable setting etc. a great deal of difficult technical problem when reducing the mode of LCO to mode 1 through adding the feedforward route in traditional digital LDO at present.
A digital LDO circuit to reduce limit loop oscillation, comprising: the digital LDO circuit, the LCO detection circuit and the LCO reduction circuit are connected in sequence, and the digital LDO circuit is connected with the LDC reduction circuit;
the LCO detection circuit is used for comparing the output voltage of the digital LDO circuit with the maximum overshoot voltage and controlling the LCO reduction circuit to be started according to the comparison result; and when the LCO reduction circuit is started, the output voltage is restrained from rising, and limit loop oscillation is reduced.
Optionally, the method further comprises:
the LCO detection circuit is also used for controlling the LCO reduction circuit to be closed according to the comparison result and outputting the output voltage.
Alternatively,
the digital LDO circuit comprises a clock comparator, a bidirectional shift register and a switch array which are connected in sequence;
the negative input end of the clock comparator is used for inputting a reference voltage, and the positive input end of the clock comparator is used for inputting an output voltage;
the switch array is connected with the LCO reduction circuit.
Alternatively,
the LCO detection circuit comprises a static comparator and an inverter which are connected in sequence; wherein a positive input terminal of the static comparator is used for inputting the output voltage, and a negative input terminal of the static comparator is used for inputting the maximum overshoot voltage; and the output end of the inverter is connected with the LCO reduction circuit.
Alternatively,
the LCO reduction circuit comprises a current mirror control circuit and the current mirror circuit which are connected in sequence; the output end of the phase inverter is connected with the current mirror control circuit, and the switch array is connected with the current mirror circuit;
when the inverter outputs a low level signal, the current mirror control circuit is turned off, and the current mirror circuit reduces the output current of the digital LDO circuit to suppress the output voltage from rising.
Alternatively,
the current mirror control circuit is a control switch.
Alternatively,
the current mirror circuit comprises two NMOS (N-channel metal oxide semiconductor) tube groups, and the two NMOS tubes are connected; each NMOS tube group comprises a plurality of NMOS tubes, and the NMOS tubes are connected in series and/or in parallel;
the current mirror control circuit is connected between the two NMOS tube groups.
Alternatively,
the switch array is a PMOS tube switch array.
Alternatively,
the control switch is an NMOS tube or a PMOS tube.
Alternatively,
the PMOS tube switch array comprises a plurality of PMOS tubes which are connected in series and/or in parallel.
The embodiment of the utility model provides a reduce limit loop oscillation's digital LDO circuit, include: the digital LDO circuit, the LCO detection circuit and the LCO reduction circuit are connected in sequence, and the digital LDO circuit is connected with the LDC reduction circuit; the LCO detection circuit is used for comparing the output voltage of the digital LDO circuit with the maximum overshoot voltage and controlling the LCO reduction circuit to be started according to the comparison result; when the LCO reduction circuit is started, the output voltage is restrained from rising, and limit loop oscillation is reduced. In the digital LDO circuit for reducing the limit loop oscillation, the output voltage is compared with the maximum overshoot voltage by using the LCO detection circuit, whether the LCO reduction circuit is started or not is determined according to the comparison result, and when the LCO reduction circuit is started, the LCO reduction circuit can inhibit the output voltage from rising, so that the limit loop oscillation is reduced. The circuit is simple in structure, excessive theoretical analysis is not needed to determine parameters of devices in the LCO reduction circuit, the LCO pretreatment mode does not need to be set for analysis of nodes in the circuit, and the circuit is very convenient to use.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a digital LDO circuit for reducing limit loop oscillation according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a digital LDO circuit for reducing limit loop oscillation according to another embodiment of the present invention;
fig. 3 is a schematic structural diagram of a shift register in a digital LDO circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a simulation output result of a shift register according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a clock comparator in a digital LDO circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a simulation output result of the clock comparator according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below, and it should be understood that the described embodiments are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
For more detailed explanation of the present invention, the digital LDO circuit for reducing limit loop oscillation according to the present invention is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a digital LDO circuit for reducing limit loop oscillation includes: the digital LDO circuit 100, the LCO detection circuit 200 and the LCO reduction circuit 300 are connected in sequence, and the digital LDO circuit 100 is connected with the LDC reduction circuit 300; the LCO detection circuit 200 is configured to compare the output voltage of the digital LDO circuit 100 with the maximum overshoot voltage, and control the LCO reduction circuit 300 to be turned on according to the comparison result; when the LCO reduction circuit 300 is started, the output voltage is restrained from rising, and limit loop oscillation is reduced.
The maximum overshoot voltage is a threshold range of the output voltage of the digital LDO circuit detected by the LCO detection circuit, namely an upper limit of the voltage which can be detected by the LCO detection circuit, and is used for determining the state of the digital LDO circuit at the next moment; the LCO detection circuit 200 substantially adjusts the adjustment direction of the system according to the magnitude of the current output voltage, and when the output voltage is too large or too small, the digital LDO circuit can enter a coarse adjustment state to quickly adjust the output voltage to a desired value; when the output voltage is stabilized near the expected value, the digital LDO circuit can enter a fine-tuning state to slowly adjust the output voltage.
In this embodiment, the LCO detection circuit compares the output voltage with the maximum overshoot voltage, and determines whether to start or turn on the LCO reduction circuit according to the comparison result. In general, when the output voltage is greater than the maximum overcharge voltage, the LCO reduction circuit is turned on to suppress the rise of the output voltage and reduce the limit loop oscillation.
The embodiment of the utility model provides a reduce limit loop oscillation's digital LDO circuit, include: the digital LDO circuit, the LCO detection circuit and the LCO reduction circuit are connected in sequence, and the digital LDO circuit is connected with the LDC reduction circuit; the LCO detection circuit is used for comparing the output voltage of the digital LDO circuit with the maximum overshoot voltage and controlling the LCO reduction circuit to be started according to the comparison result; when the LCO reduction circuit is started, the output voltage is restrained from rising, and limit loop oscillation is reduced. In the digital LDO circuit for reducing the limit loop oscillation, the output voltage is compared with the maximum overshoot voltage by using the LCO detection circuit, whether the LCO reduction circuit is started or not is determined according to the comparison result, and when the LCO reduction circuit is started, the LCO reduction circuit can inhibit the output voltage from rising, so that the limit loop oscillation is reduced. The circuit is simple in structure, excessive theoretical analysis is not needed to determine parameters of devices in the LCO reduction circuit, the LCO pretreatment mode does not need to be set for analysis of nodes in the circuit, and the circuit is very convenient to use.
In one embodiment, further comprising: the LCO detection circuit is also used for controlling the LCO reduction circuit to be closed according to the comparison result and outputting the output voltage.
Optionally, the LCO detection circuit is configured to compare the output voltage of the digital LDO circuit with the maximum overshoot voltage, and control the LCO reduction circuit to be turned off according to a comparison result, in a general case, when the output voltage is smaller than the maximum overshoot voltage, the output voltage does not need to be adjusted, and the LCO reduction circuit may be turned off or not turned on, and an LCO phenomenon may not be generated at this time, so that the output voltage may be directly output.
In one embodiment, the digital LDO circuit comprises a clock comparator, a bidirectional shift register and a switch array which are connected in sequence; the negative input end of the clock comparator is used for inputting reference voltage, and the positive input end of the clock comparator is used for inputting output voltage; the switch array is connected with the LCO reduction circuit.
In one embodiment, the switch array is a PMOS transistor switch array.
In one embodiment, the PMOS tube switch array comprises a plurality of PMOS tubes which are connected in series and/or in parallel.
Specifically, as shown in fig. 2, the digital LDO circuit includes a clock comparator, a bidirectional shift register, and a switch array. The clock comparator is used for outputting the voltage VOUTAnd a reference voltage VREFAnd the comparison result CMPout is supplied to the sel terminal of the bidirectional shift register. The bidirectional shift register is composed of an alternative data selector and a D trigger to form a basic unit, an address input end sel of the data selector controls the shifting direction, and when sel is equal to 1, the shift register shifts to the right; when sel is 0, the shift register moves to left, the shift register can only control the on or off of one PMOS tube in one clock period, and the output Q [0: n ] of the shift register]The number of conducting tubes in the switch array is determined, and the function of regulating the output voltage is achieved. Switch array MP [0: n]Composed of PMOS tubes with same size, and the gates PG [0: n ] of the PMOS tubes in the switch array]And the output end Q [0: n ] of the bidirectional shift register]And connecting, wherein under normal work, the conducted switching tube works in a linear region, and the low-voltage working characteristic of the digital LDO is realized.
The working principle of the shift register is as follows: most of shift registers in the digital LDO circuit adopt an alternative data selector and a D edge trigger as basic units. The working principle of the D edge trigger is as follows: the output signal Q depends on the state of the rising edge coming time D; the specific operation principle of the data selector, which determines the shift condition of the register by selecting the high and low levels of the input signal of the port, can be described as follows in conjunction with fig. 3 and 4: first, all the shift register outputs are set to 1, so that the register controlled transistors are turned off before the valid clock signal comes.
② the 1 end of the lowest bit and the 0 end of the highest bit are respectively Grounded (GND) and power supply (VDD), which is the basic connection condition of the shift register.
When COMPOUT is 1, when the first valid clock signal comes, Q0 is 0, and the outputs Q1, Q2, Q3, Q4, Q …, Qn 1 of the rest shift registers; when the second valid clock signal comes, Q0-Q1-0, the outputs Q2-Q3-Q4-Qn … -Qn-1, … … of the rest shift registers, and when the nth valid clock signal comes, the outputs of the n-bit shift registers are all 0.
When COMPOUT is 0, Qn is 1, Qn-1 is Qn-2 is … … is Q2 is Q1 is 0 when the first active clock signal is on. When the second valid clock signal comes, Qn-1 is 1, and the outputs Qn-2, … …, Q2, Q1 are 0, … … of the rest of the shift registers, until when the nth valid clock signal comes, all the outputs of the shift registers are 1.
In summary, the following steps: macroscopically, the working principle of the shift register is that when COMPOUT is 1, every time an effective clock signal comes, in the clock period, the shift register moves one bit to the right, and a port with one bit output of 0 is added, so that the turned-on power tube in the power array can be added. When COMPOUT is 0, every time an active clock signal comes, the shift register is shifted to the left by one bit, so that the port of the shift register with the output of 1 is increased, and the conducting power tube in one power array can be turned off. For an n-bit shift register, when all output ends are 1, n effective clock signals are needed to set all output ends to be 0; similarly, on the premise that all the output terminals are 0, n clock signals are also needed to set all the output terminals of the shift register to 1. From the above analysis of the operating principle of the shift register and the simulation results of fig. 4 for the 8-bit shift register, it can be known that: within an effective clock range, the shift register either moves one bit to the right or one bit to the left, so that within one clock cycle, the shift register only controls the conduction or the shutdown of one power tube.
Referring to fig. 5 and fig. 6, the working principle of the clock comparator is as follows: (1) when VOUT > VREF, when clk is 0, A, B point charges, raising the voltage at A, B point. When CLK is 1, discharge starts at A, B two points, but the discharge speed differs due to the difference in gate voltages of M1 and M2, and the discharge speed at a point is greater than that at B point. After the voltage at the point a is rapidly changed to a low voltage, the CMPOUT becomes 0 after passing through the RS latch.
(2) When VOUT < VREF, when clk is 0, point A, B starts charging, raising the voltage at these two points. When clk is 1, the discharge starts at point A, B, but at this time, the discharge rate at point B is higher than that at point a, and after passing through the latch, CMPOUT is 1.
(3) The auxiliary transistors MA1 and MA2 are used to charge the drains of the differential pair transistors when clk is low, increasing the drain voltage to accelerate the A, B two-point discharge when clk is 1.
In summary, the control mechanism of the digital LDO circuit is: with reference to the schematic block diagram of fig. 2, when the output voltage vout > vref, the output signal CMPout of the clock comparator is equal to 0, and at this time, the shift register moves to the left by one bit, and the number of conducting transistors in the switch array controlled by the shift register is reduced by one, so that the output voltage vout becomes smaller; when the output voltage vout is smaller than vref, the output signal CMPout of the clock comparator is equal to 1, at this time, the shift register moves one bit to the right, and the number of the opened tubes in the switch array is increased by one, so that the output voltage is increased, and the purpose of voltage stabilization is achieved.
In one embodiment, the LCO detection circuit includes a static comparator and an inverter connected in series; the positive input end of the static comparator is used for inputting output voltage, and the negative input end of the static comparator is used for inputting maximum overshoot voltage; the output end of the inverter is connected with the LCO reduction circuit.
Specifically, as shown in fig. 2, the LCO detection circuit is composed of a static comparator and an inverter, and detects the output voltage V of the digital LDO voltage in real timeOUTAnd the detection result is used for generating an output signal EN through the inverter, so as to control whether the LCO reduction circuit works or not.
In one embodiment, the LCO reduction circuit includes a current mirror control circuit and a current mirror circuit connected in series; the output end of the phase inverter is connected with the current mirror control circuit, and the switch array is connected with the current mirror circuit; when the inverter outputs a low level signal, the current mirror control circuit is turned off, and the current mirror circuit reduces the output current of the digital LDO circuit to suppress the rise of the output voltage.
In one embodiment, the current mirror control circuit is a control switch.
In one embodiment, the current mirror circuit comprises two NMOS tube groups, and the two NMOS tubes are connected; each NMOS tube group comprises a plurality of NMOS tubes which are connected in series and/or in parallel; the current mirror control circuit is connected between the two NMOS tube groups.
In one embodiment, the control switch is an NMOS transistor or a PMOS transistor.
The LCO reduction circuit comprises a current mirror control circuit and a current mirror circuit; when EN is equal to 0, the current mirror control circuit is turned off, and the LCO reduction circuit (i.e., the current mirror circuit) starts operating. When EN is equal to 1, the current mirror control circuit is turned on or conducted, and the current mirror circuit is turned off, namely the LCO reduction circuit is in an inhibited working state.
Alternatively, the current mirror control circuit is essentially a control switch. In an alternative embodiment, the control switch is a PMOS transistor or an NMOS transistor. The number of the PMOS tube and the NMOS tube can be multiple. In this embodiment, the control switch is an NMOS transistor (i.e., MN3 in fig. 2).
The current mirror circuit comprises two NMOS tube groups (namely MN1 and MN2 in FIG. 2), each NMOS tube group comprises a plurality of NMOS tubes, and the plurality of NMOS tubes are connected in series and/or in parallel to form the NMOS tube group. Wherein the parameter M represents the number of MOS tubes, and beta represents the mirror ratio of MN2 tube in the current mirror circuit relative to MN1 tube connected with a diode.
As shown in fig. 2, the LCO reduction circuit operates on the following principle: when EN is equal to 0, the LCO reduction circuit operates when the MN3 switching tube is turned on and off. When EN is equal to 1, the MN3 switching tube is turned on, the gate voltages of the tubes MN1 and MN2 in the current mirror circuit are pulled low, and the tubes MN1 and MN2 cannot be normally turned on, so that the LCO reduction circuit is in an operation prohibition state. The parameter M marked in fig. 2 indicates the number of MOS transistors, and β indicates the mirror ratio of the MN2 transistor with respect to the diode-connected MN1 transistor in the current mirror circuit.
With reference to fig. 2, the working principle of the digital LDO circuit for reducing the limit loop oscillation in the embodiment of the present invention is as follows: first assume the allowable output voltage V of the digital LDO circuitOUTHas a maximum overshoot voltage of VREF_HThe minimum current of the PMOS switch array of the digital LDO circuit is ILSBThe operating principle of the core LCO reduction circuit is as follows:
when V isOUT>VREF_HTime, output signal VOUTVia a clock comparator CMP2And VREF_HMake a comparison at which CMP2After passing through the inverter, EN becomes 0, at which time the LCO reduction circuit starts operating and the current source MP [0 ]]Supplied current ILSBThrough a current mirror to betaILSBThe current flows from the output end to the ground through the MN2 tube, so that the output capacitance C is reducedLThereby suppressing VOUTThe increase in voltage thus reduces the output ripple.
When V isOUT<VREF_HTime, output signal VOUTVia a clock comparator CMP2And VREF_HMake a comparison at which CMP2After passing through the inverter, EN is equal to 1, MN3 in the LCO reduction circuit is turned on, the gate voltages of MN1 and MN2 in the current mirror circuit are pulled down to 0, the current mirror circuit cannot work, and the voltage V is directly output at the output end of the digital LDOOUT。
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A digital LDO circuit for reducing limit loop oscillation, comprising: the digital LDO circuit, the LCO detection circuit and the LCO reduction circuit are connected in sequence, and the digital LDO circuit is connected with the LCO reduction circuit;
the LCO detection circuit is used for comparing the output voltage of the digital LDO circuit with the maximum overshoot voltage and controlling the LCO reduction circuit to be started according to the comparison result; and when the LCO reduction circuit is started, the output voltage is restrained from rising, and limit loop oscillation is reduced.
2. The reduced limit loop oscillation digital LDO circuit of claim 1, further comprising:
the LCO detection circuit is also used for controlling the LCO reduction circuit to be closed according to the comparison result and outputting the output voltage.
3. The reduced limit loop oscillation digital LDO circuit of claim 1, wherein said digital LDO circuit comprises a clock comparator, a bidirectional shift register, and a switch array connected in series;
the negative input end of the clock comparator is used for inputting a reference voltage, and the positive input end of the clock comparator is used for inputting an output voltage;
the switch array is connected with the LCO reduction circuit.
4. The reduced limit loop oscillation digital LDO circuit of claim 3, wherein said LCO detection circuit comprises a static comparator and an inverter connected in series; wherein a positive input terminal of the static comparator is used for inputting the output voltage, and a negative input terminal of the static comparator is used for inputting the maximum overshoot voltage; and the output end of the inverter is connected with the LCO reduction circuit.
5. The reduced limit loop oscillation digital LDO circuit of claim 4, wherein said LCO reduction circuit comprises a current mirror control circuit and said current mirror circuit connected in series; the output end of the phase inverter is connected with the current mirror control circuit, and the switch array is connected with the current mirror circuit;
when the inverter outputs a low level signal, the current mirror control circuit is turned off, and the current mirror circuit reduces the output current of the digital LDO circuit to suppress the output voltage from rising.
6. The reduced limit loop oscillation digital LDO circuit of claim 5, wherein said current mirror control circuit is a control switch.
7. The digital LDO circuit for reducing limit loop oscillation according to claim 5 or 6, wherein said current mirror circuit comprises two NMOS transistors, and two said NMOS transistors are connected; each NMOS tube group comprises a plurality of NMOS tubes, and the NMOS tubes are connected in series and/or in parallel;
the current mirror control circuit is connected between the two NMOS tube groups.
8. The reduced limit loop oscillation digital LDO circuit of claim 7, wherein the switch array is a PMOS transistor switch array.
9. The reduced limit loop oscillation digital LDO circuit of claim 6, wherein said control switch is an NMOS transistor or a PMOS transistor.
10. The reduced limit loop oscillation digital LDO circuit of claim 8, wherein the PMOS tube switch array comprises a plurality of PMOS tubes, the plurality of PMOS tubes being connected in series and/or in parallel.
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| CN112034925A (en) * | 2020-09-29 | 2020-12-04 | 广东工业大学 | Digital LDO circuit for reducing limit loop oscillation |
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