CN212627855U

CN212627855U - Isolation circuit capable of adjusting output current

Info

Publication number: CN212627855U
Application number: CN202021215073.XU
Authority: CN
Inventors: 张丁辉
Original assignee: Ningbo Klite Electric Manufacture Co Ltd
Current assignee: Ningbo Klite Electric Manufacture Co Ltd
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2021-02-26
Anticipated expiration: 2030-06-28

Abstract

The utility model provides an adjustable output current's isolating circuit, including on-off control regulating element, on-off control regulating element includes dial switch, the one end of every switch in the dial switch all is connected with Vcc HV pin, the other end of every switch is connected with the positive pole that corresponds diode in the optical coupler through resistance, the negative pole and the GND pin of diode in the optical coupler are connected, the collecting electrode and the Vcc1 pin of transistor in the optical coupler are connected, the projecting pole and the grid of MOS pipe of transistor in the optical coupler are connected, the drain electrode of MOS pipe passes through resistance and is connected with the CS pin, the source electrode and the GND pin of MOS pipe are connected, the grid of MOS pipe passes through resistance and is connected with the GND pin. The utility model discloses a substantive effect is: the diode of the optical coupler is conducted to give a signal by adjusting the dial switch, the MOS tube is conducted after the corresponding transistor in the optical coupler receives the signal, the RS resistor is connected into the circuit, and the signal of the CS pin is changed, so that the output current is adjusted.

Description

Isolation circuit capable of adjusting output current

Technical Field

The utility model relates to the field of electronic technology, concretely relates to adjustable output current's isolating circuit.

Background

The optical coupler isolation is realized by adopting an optical coupler. The structure of the optical coupler is equivalent to packaging the light emitting diode and the phototriode together. The optical coupling isolation circuit ensures that the two isolated circuits are not electrically and directly connected, and mainly prevents interference caused by the electrical connection, particularly between a low-voltage control circuit and an external high-voltage circuit. The optical coupler isolation circuit has the advantages of adjustable duty ratio, high isolation withstand voltage, strong anti-interference capability and the like, the optical coupler with electrostatic shielding is easy to buy, the isolation performance between strong current and weak current is good, the optical coupler belongs to a current type device, voltage noise energy is effectively inhibited, and the optical coupler isolation circuit is mainly applied to the field of measurement and control. However, the method for adjusting the output current of the isolation circuit in the current market is single, and the adjustment of the output current is not convenient.

For example, chinese patent CN209283206U, published 2019, 8.20, an optocoupler isolation circuit includes: a first end of the first resistor R1 is connected with the signal input end; the first end of the optical coupler chip is connected with the second end of the first resistor R1, the second end of the optical coupler chip is connected with an input ground, and the third end of the optical coupler chip is connected with a digital ground; the output end of the voltage stabilizing diode D1 is connected with the second end of the first resistor R1; the input end of the voltage stabilizing diode D1 is connected with the second end of the optocoupler chip; a first end of the first capacitor C1 is connected with a second end of the first resistor R1; the second end of the first capacitor C1 is connected with the second end of the optocoupler chip; the first end of the second resistor is connected with the digital power supply, and the second end of the second resistor R2 is connected with the fourth end of the optocoupler chip; the first end of the second capacitor C2 is connected with the third end of the optocoupler chip, and the second end of the second capacitor C2 is connected with digital ground; the signal output end is connected with the fourth end of the optical coupling chip. But it has simple structure, when being in different environment and needing to adjust output power, adjusts output current inconvenient problem.

Disclosure of Invention

The to-be-solved technical problem of the utility model is: the technical problem that different output powers are inconvenient to set in the existing isolation circuit is solved. An isolation circuit with adjustable output current is provided.

In order to solve the technical problem, the utility model discloses the technical scheme who takes does: an isolating circuit capable of adjusting output current comprises a processing unit, a detection unit, a display unit, an auxiliary unit, a power supply unit, a dimming unit and a dial switch control and adjustment unit, wherein the detection unit is connected with the processing unit, the processing unit is connected with the display unit and the dial switch control and adjustment unit, the display unit is connected with the auxiliary unit, the auxiliary unit is connected with the dimming unit, the dimming unit is connected with the power supply unit and the dial switch control and adjustment unit, the dial switch control and adjustment unit comprises a plurality of optical couplers, a dial switch circuit for controlling the on-off of the optical couplers is connected between the anode of the input side of each optical coupler and the anode of the circuit, the cathode of the input side of each optical coupler is grounded, and the anode of the output side of each optical coupler is connected with the anode of the circuit, the negative pole of the output side of each optical coupler is connected with the signal receiving end of the processing unit through a regulating circuit, and each regulating circuit is grounded. The on-off of the optical coupler is controlled by the dial switch circuit, the on-off of the optical coupler influences the receiving signal of the processing unit through the adjusting circuit, so that the effect of adjusting the output current is achieved, and the change of the circuit output current is more convenient due to the dial switch controlling and adjusting unit.

Preferably, the dial switch circuit comprises dial switches, a plurality of optical couplers and a plurality of resistors, the adjusting circuit comprises MOS tubes and resistors, each dial switch comprises switches corresponding to the number of the optical couplers, one end of each switch is connected with a Vcc HV pin, the other end of each switch is connected with the anode of each diode in the corresponding optical coupler through a resistor, the cathode of each diode in each optical coupler is connected with a GND pin, the collector of each transistor in each optical coupler is connected with a Vcc1 pin, the emitter of each transistor in each optical coupler is connected with the gate of each MOS tube in the corresponding adjusting circuit, the drain of each MOS tube is connected with a CS pin through a resistor, the source of each MOS tube is connected with a GND pin, and the gate of each MOS tube is connected with a GND pin through a resistor. The dial switch control and adjustment unit enables the diode of the optical coupler to be conducted to give a signal by adjusting the dial switch, the MOS tube is conducted after the corresponding transistor in the optical coupler receives the signal, the RS resistor is connected into the circuit, and the signal of the pin of the CS pin is changed, so that the output current is changed, and the adjustment of the multi-section current can be realized through a plurality of optical coupler signals.

Preferably, the processing unit comprises a chip US, a MOS tube 7N, a transformer L41DL and an optical coupler U71, a GND pin of the chip US is grounded, a GATE pin of the chip US is connected with a cathode of a diode DS and one end of a resistor RS, an anode of the diode DS is connected with a CS pin of the chip US, the other end of the resistor RS is connected with a cathode of the diode DS, the diode DS is connected in parallel with the resistor RS, an anode of the diode DS is connected with a GATE of the MOS tube 7N and one end of the resistor RS, a source of the MOS tube 7N is connected with one end of a capacitor CS and the other end of the resistor RS, a drain of the MOS tube 7N is connected with the other end of the capacitor CS, the resistor RS37 is connected in parallel with the resistor RS37, the resistor RS37 and the resistor RS37 in sequence, one end of the resistor RS37 is grounded, the other end of the resistor RS37 is connected with one end of the resistor RS and one end of the resistor RS, the other end of the resistor RS32 is connected to a PWM pin of the chip US31, one end of the capacitor CS34 is connected to an anode of the polar capacitor C61 and an emitter of the transistor QS61, the other end of the capacitor CS34 is connected to a cathode of the polar capacitor C61 and an anode of the zener diode, a cathode of the zener diode is connected to a base of the transistor QS61, a cathode of the zener diode is connected to a GND pin, the capacitor CS33 is connected in parallel to the resistor RS33B, a FB pin of the chip US31 is connected to one end of the capacitor CS33, the other end of the capacitor CS33 is connected to the GND pin, a DIM pin of the chip US31 is connected to one end of the capacitor CS31, the other end of the capacitor CS31 is grounded, a COMP pin of the chip US31 is connected to one end of the capacitor CS32, the other end of the capacitor CS32 is connected to the pin and one end of the resistor RS33 32, the other end of the resistor RS33 32 is connected to one end of the resistor RS32, and the other end of the diode DS32 is connected, the cathode of the diode DS33 is connected with the collector of a transistor QS61 and a Vcc1 pin, the other end of the transformer L41DL8 is connected with the cathode of a voltage stabilizing diode and one end of a capacitor C62, the other end of the capacitor C62 is connected with one end of a resistor RS62 and the cathode of a diode DS33, the other end of the resistor RS62 is connected with the base of a transistor QS61, the PWM pin of the chip US31 is connected with the collector of a transistor in an optocoupler U71B, and the emitter of the transistor in the optocoupler U71B is grounded. And the information processing unit adjusts the size of the sampling resistor of the CS pin of the chip US31 through a dial switch on the output end, so that the output signal of the chip US31 changes to realize the change of the output current.

Preferably, the detection unit comprises a transformer L41AL, a transformer L, a fuse F, a varistor VD and a rectifier GBL, one end of the transformer L41AL is connected to the positive terminal of a diode DS and the drain of the MOS transistor 7N of the processing unit, the negative terminal of the diode DS is connected to one terminal of a resistor RS43, the resistor RS43 is connected in parallel to the resistor RS43, the other terminal of the resistor RS43 is connected to one terminal of a resistor RS42 and one terminal of a capacitor CS, the other terminal of the resistor RS42 is connected to one terminal of a resistor RS41, the other terminal of the resistor RS41 is connected to the other terminal of the capacitor CS and the other terminal of the transformer L41AL, the resistor RS31 is connected in series to the resistor RS31 and the resistor RS31, the other terminal of the resistor RS31 is connected to the VCC pin of the chip US, the other terminal of the resistor RS31 is connected to the other terminal of the resistor RS41 and the positive terminal of the diode DS, the negative pole of a polar capacitor CD21 is connected with the other end of a resistor RS24 and one end of a capacitor C22, the negative pole of a polar capacitor CD21 is grounded, the other end of a capacitor C22 is connected with one end of an inductor L21 and the positive pole of a diode DS21, a resistor RS21 is connected with an inductor L21 in parallel, the other end of an inductor L21 is connected with one end of a piezoresistor VD21 and one end of a capacitor C21, one end of a piezoresistor VD21 is connected with a1 interface of a rectifier GBL10, the 1 interface of a rectifier GBL10 is the negative pole of two diodes, the other end of a piezoresistor VD21 is connected with a 4 interface of a rectifier GBL10 and the other end of a capacitor C21, the 4 interface of a rectifier GBL10 is the positive pole of two diodes, the other end of a capacitor C10 is grounded, the 2 interface of a rectifier GBL10 is connected with one end of a capacitor C10, one end of an inductor LS 10 and one end of a transformer L10 is an interface of a transformer N10. The other end of inductor LS11 is connected with one end of capacitor CY11, the other end of capacitor CY11 is connected with GNDE end, the other end of capacitor CY11 is G interface and G2 interface, 3 interface of rectifier GBL10 is connected with the other end of capacitor C12 and one end of the other side of transformer L12, the other end of the other side of transformer L12 is connected with one end of fuse F12, the other end of fuse F12 is connected with the other end of varistor VD11 and one end of fuse F11, and the other end of fuse F11 is L interface. The detection unit detects external information through the piezoresistor, and the alternating current is converted into direct current through the rectifier and then processed through the processing unit.

Preferably, the display unit includes a transformer L41BL8 and a transformer L51, one end of the transformer L41BL8 is connected to the anode of the diode D51 and one end of the resistor RS51A, the resistor RS51A is connected to the resistor RS51B, the resistor RS51C and the resistor RS51D in this order, the other end of the resistor RS51A is connected to one end of the capacitor CS A, the other end of the capacitor CS A is connected to the cathode of the diode D A and the anode of the capacitor CD A, the cathode of the capacitor CD A is connected to the SGND end, the cathode of the diode D A is connected to the anode of the capacitor CD A and one end of the resistor RS52A, the cathode of the capacitor CD A is connected to the anode of the capacitor CD A, the resistor RS52 RS A is connected in parallel with the resistor RS 6372, the other end of the resistor RS 3652 is connected to the cathode of the capacitor CD A and the cathode of the diode RS A is connected to the anode of the diode RS A, the capacitor CD A, the resistor RS A, the diode RS, the other end of one side of the transformer L51 is an LED positive electrode interface, the other end of the resistor RS52B is connected with one end of the other side of the transformer L51, and the other end of the other side of the transformer L51 is an LED negative electrode interface. The display unit displays the data sent by the processing unit through the display screen.

Preferably, the auxiliary unit comprises an SGND terminal and a GND1 terminal, the SGND terminal is connected with one terminal of a capacitor CY33, the other terminal of the capacitor CY33 is connected with one terminal of a capacitor CY31, the other terminal of the capacitor CY33 is a G1 interface, the other terminal of the capacitor CY31 is grounded, the GND1 terminal is connected with one terminal of the capacitor CY32, and the other terminal of the capacitor CY32 is grounded. The auxiliary unit uses the capacitance to reduce the influence of external disturbance on experimental data.

Preferably, the power supply unit comprises a transformer L41CL8, a resistor RS71, a diode DS71 and a capacitor CD71, one end of the transformer L41C is connected with one end of the resistor RS71, the other end of the resistor RS71 is connected with the anode of the diode DS71, the cathode of the diode DS71 is connected with one end of the capacitor CD71, the other end of the capacitor CD71 is connected with the other end of the transformer L41C, and the other end of the transformer L41C is connected with the GND 1. The power supply unit supplies power to the dimming unit.

Preferably, the dimming unit includes a chip US71, a HV pin of the chip US71 is connected to a cathode of a diode DS71 and a Vcc HV terminal, a MODE pin of the chip US71 is connected to one terminal of a resistor RS73 and one terminal of a resistor RS74, a GND pin of the chip US71 is connected to one terminal of an inductor LS71 and a GND1 terminal, the other terminal of the inductor LS71 is a cathode interface of DIM, an ISET pin of the chip US71 is connected to the other terminal of a resistor RS74, a Vcc pin of the chip US71 is connected to one terminal of a capacitor CS71 and an anode of a diode in an optical coupler U71 71, the other terminal of the capacitor CS71 is connected to the GND 71 terminal, a cathode of a diode in the optical coupler U71 71 is connected to one terminal of the resistor RS71, an FSET pin of the chip US71 is connected to one terminal of the capacitor CS71, the other terminal of the capacitor CS71 is connected to the other terminal of the resistor RS71 and the GND 71, the diode CS71 is connected to the other terminal of the diode CS71, the cathode of the diode DS72 is a positive electrode interface of the DIM, the OUT pin of the chip US71 is connected to the other end of the resistor RS72 and one end of the capacitor CS74, and the other end of the capacitor CS74 is connected to the GND 1. The dimming unit controls the isolated main loop by controlling the brightness of the light emitting diode in the optical coupler.

The utility model discloses a substantive effect is: through adjusting dial switch, make the optical coupler diode switch on and give the signal, make the MOS pipe switch on after the transistor received the signal in the optical coupler that corresponds, with RS resistance access circuit in, change the signal of CS pin to change output current, can realize the regulation of multistage electric current through a plurality of opto-coupler signals, realize the regulation to isolator output current through dial switch control regulating unit promptly.

Drawings

Fig. 1 is a schematic diagram of an isolation circuit capable of adjusting output current.

Fig. 2 is a schematic circuit diagram of an isolation circuit dial switch control and regulation unit.

Fig. 3 is a schematic circuit diagram of the processing unit of the present invention.

Fig. 4 is a schematic circuit diagram of the detection unit of the present invention.

Fig. 5 is a schematic circuit diagram of the display unit of the present invention.

Fig. 6 is a schematic circuit diagram of the auxiliary unit of the present invention.

Fig. 7 is a schematic circuit diagram of the power supply unit of the present invention.

Fig. 8 is a schematic circuit diagram of the dimming unit of the present invention.

Wherein: 100. the device comprises a detection unit, 200, a processing unit, 300, a dial switch control adjusting unit, 400, a dimming unit, 500, a power supply unit, 600, a display unit, 700 and an auxiliary unit.

Detailed Description

The following provides a more detailed description of the present invention, with reference to the accompanying drawings.

A battery protection circuit is disclosed, as shown in FIG. 1, the embodiment includes a processing unit, a detecting unit, a display unit, an auxiliary unit, a power supply unit, a dimming unit and a dial switch control and adjustment unit, the detecting unit is connected with the processing unit, the processing unit is connected with the display unit and the dial switch control and adjustment unit, the display unit is connected with the auxiliary unit, the auxiliary unit is connected with the dimming unit, the dimming unit is connected with the power supply unit and the dial switch control and adjustment unit, the power supply unit supplies power to the dimming unit, the dial switch control and adjustment unit is connected between the dimming unit and the processing unit, so as to adjust the output current of the circuit through the dial switch, the dial switch control and adjustment unit is shown in FIG. 2, the dial switch control and adjustment unit includes a dial switch circuit, a plurality of adjustment circuits and a plurality of optical couplers, the positive pole of the input side of the optical coupler is connected with a dial switch circuit capable of controlling the on-off of the optical coupler, the dial switch circuit is connected with the positive pole of the circuit, the negative pole of the input side of the optical coupler is grounded, the positive pole of the output side of the optical coupler is connected with the positive pole of the circuit, the negative pole of the output side of the optical coupler is connected with a signal receiving end of a processing unit through a corresponding regulating circuit, the regulating circuit is grounded, the dial switch circuit comprises a dial switch, a plurality of optical couplers and a plurality of resistors, each regulating circuit comprises an MOS (metal oxide semiconductor) tube and a resistor, the dial switch comprises switches corresponding to the number of the optical couplers, one end of each switch is connected with a Vcc HV (voltage) pin, the other end of each switch is connected with the positive pole of a diode in the optical coupler through a resistor, the negative pole of a diode in the optical coupler is connected with a GND (ground) pin, a collector of, the drain electrode of the MOS tube is connected with the CS pin through a resistor, the source electrode of the MOS tube is connected with the GND pin, and the grid electrode of the MOS tube is connected with the GND pin through a resistor. Taking the photo coupler U37A as an example, the anode of the diode in the photo coupler U37A is connected with one end of a resistor RS11, the other end of the resistor RS11 is connected with one end of a switch line 1 in a dial switch DA04, the other end of the switch line 1 is connected with a Vcc HV pin, the cathode of the diode in the photo coupler U37A is connected with a GND pin, the collector of the transistor in the corresponding photo coupler U37B is connected with a Vcc1 pin, the emitter of the transistor in the photo coupler U37B is connected with the gate of the corresponding MOS transistor, the drain of the corresponding MOS transistor is connected with a CS pin through a resistor RS23, the source of the corresponding MOS transistor is connected with the GND pin, and the gate of the corresponding MOS transistor is connected with the GND pin through a resistor RS 24.

Fig. 3 shows a schematic circuit diagram of a processing unit in this embodiment, the processing unit includes a chip US31, a transformer L41DL8, a MOS tube 7N65, an optical coupler U71B, and a plurality of capacitors and a plurality of resistors, the processing unit processes information with the chip US31 as a core, a GND pin of the chip US31 is grounded, a GATE pin of the chip US31 is connected to a cathode of a diode DS32 and one end of a resistor RS34, an anode of the diode DS32 is connected to a CS pin of the chip US31, the other end of the resistor RS34 is connected to a cathode of a diode DS31 and one end of a resistor RS35, an anode of a diode DS31 and the other end of a resistor RS35 are connected to a GATE of a MOS tube 7N65, a GATE of a MOS tube 7N65 is connected to one end of a resistor RS36, the other end of a resistor RS36 is connected to one end of a resistor RS37A, a CS35 is connected in parallel to a source and a drain of a detection unit 7N 35, and a resistor RS35 a circuit of a detection unit is included in, Four resistors with the same resistance, including RS37B, RS37C and RS37D, are connected in parallel in sequence to form a parallel circuit 1, one end of the parallel circuit 1 is grounded, the other end of the parallel circuit 1 is connected with the source of the MOS 7N65 and one end of the resistor RS37, the other end of the resistor RS37 is connected with the CS pin of the chip US31, the CS pin of the chip US31 is further connected with a dial switch control and adjustment unit, a signal output by the dial switch control and adjustment unit can affect a signal received by the CS pin, so as to affect the chip US31 and realize adjustment of output current, the VCC pin of the chip US31 is connected with the anode of a polar capacitor C61 and one end of a resistor RS32, a line connecting the VCC pin of the chip US 8 and the detection unit is set to be a1, the other end of the resistor RS32 is connected with the PWM pin of the chip US31, the capacitor CS34 is connected in parallel with a polar capacitor C61, the cathode of a voltage regulator diode is connected with the base of a triode QS61, the anode of the, the cathode of a capacitor C61 with poles is connected with the anode of a voltage stabilizing diode, the cathode of the voltage stabilizing diode is connected with a GND pin, one end of a capacitor C62, one end of a capacitor C62 is respectively connected with one end of a resistor RS62, the cathode of a diode DS33 and a Vcc1 pin, the other end of a capacitor C62 is connected with the cathode of the voltage stabilizing diode, the other end of a resistor RS62 is connected with the cathode of the voltage stabilizing diode, the cathode of a diode DS33 is connected with the collector of a triode QS61, the anode of a diode DS33 is connected with one end of a resistor RS61, the other end of a resistor RS61 is respectively connected with one end of a transformer L41DL8 and one end of a resistor RS33A, the other end of a transformer L41DL8 is connected with the anode of the voltage stabilizing diode, the other end of a resistor RS33A is connected with the FB pin of a chip US31, a capacitor CS33 is connected with a resistor RS33B in parallel, the FB pin of a chip US31 is connected with one end, the DIM pin of the chip US31 is grounded through a capacitor CS31, the PWM pin of the chip US31 is connected to the collector of the transistor in the optocoupler U71B, and the emitter of the transistor in the optocoupler U71B is grounded.

As shown in fig. 4, the detection unit of this embodiment includes a transformer L41AL8, a transformer L12, a varistor VD11, a varistor VD21, a fuse F21 and a rectifier GBL 21, wherein one end of the transformer L41AL 21 is connected to the positive pole of a diode DS21 and a line a 21, the negative pole of the diode DS21 is connected to one end of a resistor RS43 21 and one end of the resistor RS43 21, the other end of the resistor RS43 21 is connected to the other end of the resistor RS43 21 and one end of a capacitor CS 21, the resistor RS42 21 is connected in series with the resistor RS41 21, the capacitor CS 21 is connected in parallel with a series circuit formed by the resistor RS42 21 and the resistor RS41 21, the other end of the capacitor CS 21 is connected to the other end of the transformer L41AL 21 and one end of the resistor RS31 21, three same resistors RS41 21, the other end of the series circuit is connected with the positive pole of the diode DS21, and the diode CD21, the capacitor CS 21 is connected in series, the negative electrode of the polar capacitor CD21 is grounded, three same resistors RS22, RS23 and RS24 are sequentially connected in series to form a series circuit 2, the series circuit 2 is connected in parallel with the polar capacitor CD21, the resistor RS21 is connected in parallel with the inductor L21, two ends of a resistor RS21 are respectively connected with one end of a capacitor C21 and one end of a capacitor C22, one end of the capacitor C22 is connected with the positive electrode of a diode DS 22, the other end of the capacitor C22 and the other end of the capacitor C22 are grounded, a voltage dependent resistor VD 22 is connected in parallel with the capacitor C22, two ends of the voltage dependent resistor VD 22 are connected with a bridge rectifier GBL 22, the other end of the bridge rectifier GBL 22 is connected with two ends of the capacitor C22, two ends of the capacitor C22 are connected with one end of two sides of the transformer L22, one end of the capacitor C22 is connected with one end of the inductor LS 22, the other end of the inductor LS 22 is connected with one end of the other end of the transformer GNN 22, and the other end of the transformer GNN 22 are, one side of a transformer L12 is connected with one end of a piezoresistor VD11, the other side of the transformer L12 is connected with one end of a fuse F12, the other end of the fuse F12 is respectively connected with the other end of a piezoresistor VD11 and one end of a fuse F11, and the other end of the fuse F11 is an L interface.

As shown in fig. 5, the display unit of this embodiment includes a transformer L41BL8, a transformer L51, a plurality of capacitors and a plurality of resistors, wherein four resistors RS51A, RS51B, RS51C, and RS51D with the same resistance are connected in parallel in sequence to form a parallel circuit 2, one end of the parallel circuit 2 is connected to the anode of a diode D51, the other end of the parallel circuit 2 is connected to the cathode of a diode D51 through a capacitor CS51, capacitances of active capacitors CD51, CD52, CD53, and CD54 are equal, an active capacitor CD51 is connected in series with an active capacitor CD52 to form a series circuit 3, an active capacitor CD53 is connected in series with an active capacitor CD54 to form a series circuit 4, the series circuit 3 is connected in parallel with the series circuit 4 to form a parallel circuit 3, a resistor RS52A is connected in parallel with the parallel circuit 3, one end of the transformer L41BL8 is connected to the anode of a diode D51, and the cathode of the diode D51 is connected with the anode of the capacitor 51, the other end of the transformer L41BL8 is connected to the negative electrode of the active capacitor CD52 and the SGND end, the two ends of the resistor RS52B are connected to one end of the transformer L51 at the two sides, and the other end of the transformer L51 at the two sides is an LED positive electrode interface and an LED negative electrode interface, respectively.

As shown in fig. 6, the auxiliary unit of this embodiment includes an SGND terminal and a GND1 terminal, the SGND terminal is connected to one terminal of a capacitor CY33, the other terminal of the capacitor CY33 is a G1 interface, the other terminal of the capacitor CY33 is grounded through a capacitor CY31, and the GND1 terminal is grounded through a capacitor CY 32.

Fig. 7 shows a schematic circuit diagram of the power supply unit of this embodiment, the power supply unit includes a transformer L41CL8, a resistor RS71, a diode DS71 and a capacitor CD71, one end of the transformer L41C is connected to an anode of the diode DS71 through a resistor RS71, a cathode of the diode DS71 is connected to one end of the capacitor CD71, a cathode of the diode DS71 is connected to the dimming unit through a line b, the other end of the capacitor CD71 is connected to the other end of the transformer L41C, and the other end of the transformer L41C is connected to a GND1 end.

As shown in fig. 8, the circuit schematic diagram of the dimming unit of this embodiment includes a chip US71, an optocoupler U71A and a diode DS72, a HV pin of the chip US71 is connected to a Vcc HV terminal, a HV pin of the chip US71 is connected to a power supply unit through a line b, a MODE pin of the chip US71 is connected to an ISET pin of the chip US71 through a resistor RS74, a resistor RS73 is connected in series with a capacitor CS71 to form a series circuit 5, a MODE pin of the chip US71 is connected to an FSET pin of the chip US71 through the series circuit 5, one end of the resistor RS73 connected to a capacitor CS71 is connected to a GND1 terminal, the other end of the resistor RS73 is connected to a MODE pin of the chip US71, GND pins of the chip US71 are connected to one end of an inductor 71 and a GND1 terminal, the other end of the inductor LS71 is a negative terminal of a DIM, one Vcc pin of the chip US71 is connected to one end of a Vcc terminal of a capacitor CS71 and the other end of a positive electrode of a diode U3671 and, the cathode of a diode in the optocoupler U71A is connected with an OUT pin of a chip US71 through a resistor RS72, the OUT pin of the chip US71 is connected with a GND1 end through a capacitor CS74, a DIM pin of the chip US71 is connected with the GND1 end through a capacitor CS73, the DIM pin of the chip US71 is connected with the anode of a diode DS72, and the cathode of the diode DS72 is an anode interface of a DIM.

The working process of the embodiment is as follows: through adjusting dial switch DA04, make the diode of optical coupler U73A switch on and give the signal, make the MOS pipe switch on after the transistor received the signal in the corresponding optical coupler U72B, incorporate RS resistance into resistance RS37A, resistance RS37B, resistance RS37C and resistance RS37D, change the signal of CS pin, thereby change output current, just can realize the regulation of multistage electric current through a plurality of opto-coupler signals like this, realize the regulation to isolation circuit output current through dial switch control regulating element promptly.

The above embodiment is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and other variations and modifications may be made without departing from the technical scope of the claims.

Claims

1. An isolation circuit capable of adjusting output current is characterized by comprising a processing unit, a detection unit, a display unit, an auxiliary unit, a power supply unit, a dimming unit and a dial switch control and adjustment unit, wherein the detection unit is connected with the processing unit, the processing unit is connected with the display unit and the dial switch control and adjustment unit, the display unit is connected with the auxiliary unit, the auxiliary unit is connected with the dimming unit, the dimming unit is connected with the power supply unit and the dial switch control and adjustment unit, the dial switch control and adjustment unit comprises a plurality of optical couplers, a dial switch circuit for controlling the on-off of the optical couplers is connected between the anode of the input side of each optical coupler and the anode of the circuit, the cathode of the input side of each optical coupler is grounded, and the anode of the output side of each optical coupler is connected with the anode of the circuit, the negative pole of the output side of each optical coupler is connected with the signal receiving end of the processing unit through a corresponding adjusting circuit, and each adjusting circuit is grounded.

2. The isolation circuit of claim 1, wherein the output current is adjustable, the dial switch circuit comprises a dial switch, a plurality of optical couplers and a plurality of resistors, the regulating circuit comprises an MOS tube and a resistor, the dial switch comprises switches corresponding to the number of optical couplers, one end of each switch is connected with a Vcc HV pin, the other end of each switch is connected with the anode of a diode in the corresponding optical coupler through a resistor, the cathode of the diode in each optical coupler is connected with a GND pin, the collector of a transistor in each optical coupler is connected with a Vcc1 pin, the emitter of the transistor in each optical coupler is connected with the grid of an MOS (metal oxide semiconductor) tube in the corresponding regulating circuit, the drain of each MOS tube is connected with a CS (circuit switching) pin through a resistor, the source of each MOS tube is connected with a GND pin, and the grid of each MOS tube is connected with a GND pin through a resistor.

3. The isolation circuit according to claim 1, wherein the processing unit comprises a chip US31, a MOS transistor 7N65, a transformer L41DL8 and an optical coupler U71B, a GND pin of the chip US31 is grounded, a GATE pin of the chip US31 is connected with a cathode of a diode DS32 and one end of a resistor RS34, an anode of a diode DS32 is connected with a CS pin of the chip US31, the other end of the resistor RS31 is connected with a cathode of the diode DS31, the diode DS31 is connected with a resistor RS31 in parallel, an anode of the diode DS31 is connected with a GATE of the MOS transistor 7N 31 and one end of the resistor RS31, a source of the MOS transistor 7N 31 is connected with one end of the capacitor CS31 and the other end of the resistor RS31, a drain of the MOS transistor 7N 31 is connected with the other end of the capacitor RS31, the resistor RS31 is connected with the resistor RS 3637 RS31, the resistor RS 3637 is connected with the resistor RS31, one end of the resistor RS 3637 is connected with the resistor RS31 and the other end of the RS31 in, the CS pin of a chip US31 is connected with the other end of a resistor RS37, the VCC pin of the chip US31 is connected with one end of a resistor RS32 and one end of a capacitor CS34, the other end of a resistor RS32 is connected with the PWM pin of the chip US31, one end of a capacitor CS34 is connected with the anode of an active capacitor C61 and the emitter of a transistor QS61, the other end of a capacitor CS34 is connected with the cathode of an active capacitor C61 and the anode of a zener diode, the cathode of the zener diode is connected with the base of a transistor QS61, the cathode of the zener diode is connected with a GND pin, a capacitor CS33 is connected with a resistor RS33B in parallel, the FB pin of a chip US31 is connected with one end of a capacitor CS33, the other end of a capacitor CS33 is connected with the GND pin, the DIM pin of the chip US31 is connected with one end of the capacitor CS31, the other end of the capacitor CS31 is grounded, the COMP pin of the chip US31 is connected with one end of the capacitor CS31, the, the other end of the resistor RS33A is connected with one end of a resistor RS61 and one end of a transformer L41DL8, the other end of the resistor RS61 is connected with the anode of a diode DS33, the cathode of a diode DS33 is connected with the collector of a triode QS61 and a Vcc1 pin, the other end of the transformer L41DL8 is connected with the cathode of a zener diode and one end of a capacitor C62, the other end of the capacitor C62 is connected with one end of a resistor RS62 and the cathode of a diode DS33, the other end of the resistor RS62 is connected with the base of a triode QS61, the PWM pin of the chip US31 is connected with the collector of a transistor in the optocoupler U71B, and.

4. An isolation circuit capable of adjusting output current according to claim 1 or 3, wherein the detection unit comprises a transformer L41AL8, a transformer L12, a fuse F11, a fuse F12, a varistor VD11, a varistor VD21 and a rectifier GBL10, one end of the transformer L41AL8 is connected with the positive electrode of a diode DS41 and the drain of a MOS tube 7N65 in the processing unit, the cathode of the diode DS 65 is connected with one end of a resistor RS43 65, the resistor RS43 65 is connected with the resistor RS43 65 in parallel, the other end of the resistor RS43 65 is connected with one end of a resistor RS42 65 and one end of a capacitor CS 65, the other end of the resistor RS42 65 is connected with one end of the resistor RS41 65, the other end of the resistor RS41 RS 65 is connected with the other end of the capacitor CS 65 and the other end of the transformer L41AL 65, the resistor RS31 65 is connected with the resistor RS31 65 and the resistor RS 3631 in series, the other end of the resistor RS 3631 is connected with the VCC pin of the chip US 65, the other end of the resistor RS 3631, the cathode of a diode DS21 is connected with the anode of a polar capacitor CD21 and one end of a resistor RS22, the other end of the resistor RS22 is sequentially connected with a resistor RS23 and a resistor RS24 in series, the cathode of a polar capacitor CD21 is connected with the other end of a resistor RS24 and one end of a capacitor C22, the cathode of a polar capacitor CD21 is grounded, the other end of a capacitor C22 is connected with one end of an inductor L21 and the anode of a diode DS21, a resistor RS21 is connected with an inductor L21 in parallel, the other end of the inductor L21 is connected with one end of a piezoresistor VD21 and one end of a capacitor C21, one end of the piezoresistor VD21 is connected with an interface 1 of a rectifier L21, the interface 1 of the rectifier GBL 21 is the cathode of two diodes, the other end of the rectifier GBL 21 is connected with the interface 4 of the rectifier GBL 21 and the other end of the capacitor C21, the interface 4 of the rectifier GBL 21 is connected with the anode of the capacitor C21, the other end of the rectifier GB, One end of an inductor LS11 is connected with one end of one side of a transformer L12, the other end of one side of a transformer L12 is connected with one end of a piezoresistor VD11, the other end of one side of a transformer L12 is an N interface, the other end of an inductor LS11 is connected with one end of a capacitor CY11, the other end of a capacitor CY11 is connected with a GNDE end, the other end of a capacitor CY11 is a G interface and a G2 interface, a 3 interface of a rectifier GBL10 is connected with the other end of a capacitor C12 and one end of the other side of a transformer L12, the other end of the other side of a transformer L12 is connected with one end of a fuse F12, the other end of a fuse F12 is connected with the other end of a piezoresistor VD11 and one end of a.

5. The isolating circuit according to claim 1, wherein the display unit comprises a transformer L41BL8 and a transformer L51, one end of the transformer L41BL8 is connected to the anode of the diode D51 and one end of a resistor RS51A, the resistor RS51A is connected to a resistor RS51B, a resistor RS51C and a resistor RS51D in sequence, the other end of the resistor RS51A is connected to one end of a capacitor CS51, the other end of the capacitor CS51 is connected to the cathode of a diode D51 and the anode of a capacitor CD51, the cathode of the capacitor CD51 is connected to the anode of a capacitor CD52, the cathode of the capacitor CD52 is connected to the SGND, the cathode of a diode D51 is connected to the anode of the capacitor CD53 and one end of a resistor RS52 53, the cathode of the capacitor CD53 is connected to the anode of the capacitor CD53, the resistor RS52 is connected to the cathode of the capacitor CD53, the resistor RS 53 is connected to the cathode of the capacitor CD53 and the other end of the CD53 in parallel, one end of the resistor RS52B is connected to the negative terminal of the diode D51 and one end of the transformer L51, the other end of the transformer L51 is an LED positive terminal, the other end of the resistor RS52B is connected to one end of the transformer L51, and the other end of the transformer L51 is an LED negative terminal.

6. The isolation circuit capable of adjusting the output current according to claim 1, wherein the auxiliary unit comprises an SGND terminal and a GND1 terminal, the SGND terminal is connected to one terminal of a capacitor CY33, the other terminal of the capacitor CY33 is connected to one terminal of a capacitor CY31, the other terminal of the capacitor CY33 is a G1 interface, the other terminal of the capacitor CY31 is grounded, the GND1 terminal is connected to one terminal of the capacitor CY32, and the other terminal of the capacitor CY32 is grounded.

7. The isolation circuit capable of adjusting the output current as claimed in claim 1, wherein the power supply unit comprises a transformer L41CL8, a resistor RS71, a diode DS71 and a capacitor CD71, one end of the transformer L41C is connected to one end of the resistor RS71, the other end of the resistor RS71 is connected to the anode of the diode DS71, the cathode of the diode DS71 is connected to one end of the capacitor CD71, the other end of the capacitor CD71 is connected to the other end of the transformer L41C, and the other end of the transformer L41C is connected to the GND 1.

8. The isolation circuit according to claim 1 or 7, wherein the dimming unit comprises a chip US71, the HV pin of the chip US71 is connected to the cathode of the diode DS71 and the Vcc HV terminal, the MODE pin of the chip US71 is connected to one end of the resistor RS73 and one end of the resistor RS74, the GND pin of the chip US71 is connected to one end of the inductor LS71 and the GND1 terminal, the other end of the inductor LS71 is the cathode interface of the DIM, the ISET pin of the chip US71 is connected to the other end of the resistor RS74, the VCC pin of the chip US71 is connected to one end of the capacitor CS72 and the anode of the diode in the optocoupler U71A, the other end of the capacitor CS72 is connected to the GND1 terminal, the cathode of the diode in the optocoupler U71A is connected to one end of the resistor RS72, the FSET pin of the chip US 72 is connected to one end of the capacitor CS72, the other end of the capacitor CS72 and the anode terminal of the resistor RS72 and the diode DS72 are connected to one end of the diode RS72, the other end of the capacitor CS73 is connected with the GND1 end, the cathode of the diode DS72 is a positive electrode interface of the DIM, the OUT pin of the chip US71 is connected with the other end of the resistor RS72 and one end of the capacitor CS74, and the other end of the capacitor CS74 is connected with the GND1 end.