CN212619003U

CN212619003U - Distributed intelligent adaptive power module

Info

Publication number: CN212619003U
Application number: CN202021542418.2U
Authority: CN
Inventors: 郭金成; 闫润; 雷维
Original assignee: Hairun Xinfeng Chongqing Intelligent Technology Co ltd
Current assignee: Hairun Xinfeng Chongqing Intelligent Technology Co ltd
Priority date: 2020-07-30
Filing date: 2020-07-30
Publication date: 2021-02-26
Anticipated expiration: 2030-07-30

Abstract

The utility model provides a distributed intelligent adaptive power module, which comprises a case, wherein a cavity partition is arranged in the case, the cavity partition divides the case into a fan cavity and an air-out noise reduction cavity, an air passing hole is arranged on the cavity partition, an air inlet communicated with the fan cavity and an air outlet communicated with the air-out noise reduction cavity are arranged on the case, and the air passing hole and the air outlet are arranged in a staggered manner; still include the fan intracavity is installed an intelligent adaptation fan, and the air current that supplies to come out from intelligent adaptation fan gets into the air-out and falls the chamber of making an uproar. The utility model discloses can be through the rotational speed of intelligent adaptation fan intelligent regulation fan.

Description

Distributed intelligent adaptive power module

Technical Field

The utility model relates to a ventilation system especially relates to a distributing type intelligence adaptation power module.

Background

The development result of the ventilation system is remarkable in recent years, and the control process of the existing power distributed ventilation system is as follows: and branch fans are arranged at the tail ends of the branches, and control signals (0-10V) of the branch fans are transmitted to the PLC for weighted calculation to obtain the operating voltage signal value of the main fan, so that the main fan can operate at a speed regulated mode according to system changes. Patent application No. 2019216413962, the name is "power distributed self-balancing ventilation system", discloses main road and a plurality of branch road, install main fan on the main road, install the branch road fan on whole or partial branch road, establish ties with the main road again after all branch roads are parallelly connected, and the terminal access room that corresponds separately of branch road, its characterized in that: the main fan adopts a self-adaptive fan or a direct current brushless fan provided with a pressure sensor, and the branch fan adopts a self-adaptive fan or a direct current brushless fan provided with an air speed sensor; when the main fan adopts a direct current brushless fan, the equipped pressure sensor is arranged on the trunk and is positioned on the air outlet side of the direct current brushless fan; when the branch fan adopts a direct-current brushless fan, the equipped wind speed sensor is arranged on the corresponding branch and is positioned on the air outlet side or the air inlet side of the corresponding direct-current brushless fan; and at least one of the main fan and the branch fan is a self-adaptive fan.

SUMMERY OF THE UTILITY MODEL

The utility model discloses aim at solving the technical problem who exists among the prior art at least, innovated a distributing type intelligence adaptation power module very much.

In order to realize the above purpose of the utility model, the utility model provides a distributed intelligent adaptive power module, which comprises a case, wherein a cavity partition is arranged in the case, the cavity partition divides the case into a fan cavity and an air-out noise-reduction cavity, an air-passing hole is arranged on the cavity partition, an air inlet communicated with the fan cavity and an air outlet communicated with the air-out noise-reduction cavity are arranged on the case, and the air-passing hole and the air outlet are arranged in a staggered way; still include the fan intracavity is installed an intelligent adaptation fan, and the air current that supplies to come out from intelligent adaptation fan gets into the air-out and falls the chamber of making an uproar.

In a preferred embodiment of the present invention, the intelligent adaptive fan comprises a fan and a controller connected to the fan, wherein the controller comprises a processor U1 and a fan rotation speed acquisition module connected to the processor U1;

fan rotational speed collection module includes: a fan rotation speed data input terminal PC4(HS)/TIM1_ CH4 of the processor U1 is respectively connected to a first terminal of a resistor R60 and a collector of a transistor Q7, a second terminal of a resistor R60 is connected to a +5V power supply, an emitter of the transistor Q7 is respectively connected to a power ground and a first terminal of the resistor R46, a second terminal of a resistor R46 and a base of the transistor Q7 are respectively connected to a first terminal of a resistor R5 and a fan rotation speed output terminal speed of the fan interface P2, a second terminal of the resistor R5 is respectively connected to a first terminal of a capacitor C38 and a power output terminal +10V of the fan interface P2, and a second terminal of the capacitor C38 is connected to the power ground. The rotating speed output by the fan is connected with the fan rotating speed output end speed of the fan interface P2, the rotating speed output by the fan rotating speed acquisition module is input into the processor U1, and the +10V voltage output by the fan is utilized to provide pull-up voltage for the rotating speed output by the fan.

The utility model discloses an in the preferred embodiment, still include fan rotational speed input module on the controller, fan rotational speed input module includes: a fan rotating speed data output end PC2(HS) TIM1_ CH2 of the processor U1 is connected with a first end of a resistor R13, a second end of a resistor R13 is respectively connected with a first end of a resistor R14 and a first end of a capacitor C14, a second end of the resistor R14 is respectively connected with a first end of a capacitor C15 and a non-inverting input end of an amplifier U3A, and a second end of a capacitor C14 and a second end of a capacitor C15 are respectively connected with a power ground; the inverting input end of the amplifier U3A is respectively connected with the first end of a resistor R9 and the first end of a resistor R10, the second end of the resistor R9 is connected with a power ground, the second end of a resistor R10 is respectively connected with the output end of the amplifier U3A and the first end of a resistor R43, the second end of the resistor R43 is respectively connected with the first end of a capacitor C31, the cathode of a diode DZ2 and the fan rotating speed data input end pwm of a fan interface P2, the second end of a capacitor C31 is connected with the power ground, and the anode of the diode DZ2 is connected with the power ground; the ground terminal of the blower interface P2 is connected to power ground. The rotating speed data input end PWM of the fan interface P2 is connected with the fan rotating speed data input, the processor U1 outputs PWM with different duty ratios, and the PWM is input to the amplifier U3A after passing through the filter circuit formed by the resistor R13, the resistor R14, the capacitor C14 and the capacitor C15, the amplifier U3A outputs different voltage values to be input to the fan, and the fan intelligently adjusts the rotating speed of the fan according to the received rotating speed data.

In a preferred embodiment of the present invention, the controller further includes a power module, and the power module includes: the negative power supply end of the power supply interface J1 is connected with the power supply ground, the positive power supply end of the power supply interface J1 is respectively connected with the first end of the capacitor C34, the first end of the capacitor C13 and the power supply voltage end IN of the voltage chip U2, and the second end of the capacitor C34 and the second end of the capacitor C13 are respectively connected with the power supply ground; the switch output end SW of the voltage chip U2 is respectively connected with the first end of a capacitor C1 and the first end of an inductor L1, the second end of the capacitor C1 is connected with the first end of a resistor R4, the second end of a resistor R4 is connected with the leading end BST of the voltage chip U2, the second end of the inductor L1 is respectively connected with the first end of the capacitor C11 and the first end of a capacitor C12, an anode of the indicator light LED1, a first end of a capacitor C35 and a first end of a resistor R8 are connected, a second end of the capacitor C11 and a second end of the capacitor C12 are respectively connected with a power ground, a cathode of the indicator light LED1 is connected with a first end of a resistor R2, a second end of the resistor R2 is connected with the power ground, a second end of the resistor R8 is respectively connected with a first end of a resistor R7 and a first end of a resistor R21, a second end of the resistor R21 is connected with the power ground, a second end of the capacitor C35 is connected with a first end of a resistor R23, and a second end of the resistor R23 and a second end of the resistor R7 are respectively connected with a feedback end FB of the voltage chip U2; an enable terminal EN of the voltage chip U2 is respectively connected with a first terminal of the resistor R3 and a first terminal of the capacitor C2, a second terminal of the capacitor C2 is connected with a power ground, and a second terminal of the resistor R3 is connected with a power positive terminal of the power interface J1. The +12V power supply voltage is connected with the power supply interface J1, the power supply interface J1 outputs the +12V power supply voltage, and the +12V power supply voltage outputs a stable +5V power supply after passing through the voltage chip U2.

The utility model discloses an in a preferred embodiment, still include the button test input module on the controller, the button test input module includes: the first terminal of the key K1 is connected to power ground, the second terminal of the key K1 is connected to the first terminal of the resistor R33 and the first terminal of the resistor R34, respectively, the second terminal of the resistor R33 is connected to +5V power, and the second terminal of the resistor R34 is connected to the key data input terminal PD3(HS)/TIM2_ CH2[ ADC _ ETR ] of the processor U1. When the fan is tested, after the key K1 is pressed for a long time, the system enters a test mode, and the fan gear is set by pressing the key K1 for a short time. The gear test of the fan is realized.

In a preferred embodiment of the present invention, the controller further includes a data conversion module, and the data conversion module includes: an enable terminal PD7/TLI [ TIM1_ CH4] of the processor U1 is respectively connected with a first terminal of a resistor R30, a driver output enable terminal DE of a data conversion chip U7 and a receiver output enable terminal RE of a data conversion chip U7, and a second terminal of a resistor R30 is connected with a +5V power supply; the receiver output RO of the data conversion chip U7 is connected to the data input PD6/UART2_ RX of the processor U1, and the driver input DI of the data conversion chip U7 is connected to the data output PD5/UART2_ TX of the processor U1; a power supply voltage terminal VCC of the data conversion chip U7 is respectively connected with a +5V power supply and a first terminal of a capacitor C26, and a second terminal of the capacitor C26 is connected with a power supply ground; the power ground terminal GND of the data conversion chip U7 is connected with the power ground; the data terminal B of the data conversion chip U7 is connected to the first terminal of the resistor R27, the second terminal of the resistor R27 is connected to the first terminal of the resistor R28, the first terminal of the resistor R32, the first terminal of the transient suppression diode Z2 and the first terminal of the fuse F1, the second terminal of the resistor R32 is connected to the power ground, the data terminal A of the data conversion chip U7 is connected to the first terminal of the resistor R29, the second terminal of the resistor R29 is connected to the second terminal of the resistor R28, a first terminal of the resistor R31, a first terminal of the transient suppression diode Z1 and a first terminal of the fuse F2 are connected, a second terminal of the resistor R31 is connected to a +5V power supply, a second terminal of the transient suppression diode Z1 and a second terminal of the transient suppression diode Z2 are respectively connected to a power ground, a second terminal of the fuse F1 is connected to a data first terminal of the data interface P8, and a second terminal of the fuse F2 is connected to a data second terminal of the data interface P8. The data communication is realized by connecting the data interface P8 with a data communication terminal.

The utility model discloses an in a preferred embodiment, still include fan drive module on the controller, fan drive module includes: a driving data terminal [ TIM1_ CH3N ] AIN2/PB2 of the processor U1 is connected with a driving input terminal 1B of the driving chip U5, a driving data terminal [ TIM1_ ETR/AIN3/PB3 of the processor U1 is connected with a driving input terminal 2B of the driving chip U5, a driving data terminal [ I2C _ SCL ] AIN4/PB4 of the processor U1 is connected with a driving input terminal 3B of the driving chip U5, and a driving data terminal [ I2C _ SDA ] AIN5/PB5 of the processor U1 is connected with a driving input terminal 4B of the driving chip U5;

a drive output end 1C of a drive chip U5 is connected with a first drive input end of a fan drive interface P5, a drive output end 2C of a drive chip U5 is connected with a second drive input end of a fan drive interface P5, a drive output end 3C of the drive chip U5 is connected with a third drive input end of a fan drive interface P5, a drive output end 4C of a drive chip U5 is connected with a fourth drive input end of a fan drive interface P5, and a power supply end of the fan drive interface P5 is connected with a +12V power supply;

the common terminal COM of the driver chip U5 is connected to the +12V power supply and the first terminal of the capacitor C24, respectively, and the common ground terminal E of the driver chip U5 is connected to the power ground and the second terminal of the capacitor C24, respectively. The processor U1 drives the fan to work through the fan driving module by connecting the fan driving interface P5 with the input end of the fan.

The utility model discloses an among the preferred embodiment, still include fan rotational speed gear setting module on the controller, fan rotational speed gear setting module includes: a data input end [ TIM1_ CH1N ] AIN0/PB0 of the processor U1 is respectively connected with a first output end of the interface J2, a second output end of the interface J2, a third output end of the interface J2, a fourth output end of the interface J2, a fifth output end of the interface J2, a sixth output end of the interface J2, a seventh output end of the interface J2 and an eighth output end of the interface J2;

a first input end of a interface J2 is connected to a first resistor end of the resistor group RN10 and a first second resistor end of the resistor group RN10, a second input end of the interface J2 is connected to a first third resistor end of the resistor group RN10 and a first fourth resistor end of the resistor group RN10, a third input end of the interface J2 is connected to a first resistor end of the resistor group RN9 and a first second resistor end of the resistor group RN9, and a fourth input end of the interface J2 is connected to a first third resistor end of the resistor group RN9 and a first fourth resistor end of the resistor group RN 9;

the fifth input end of the interface J2 is connected to the second end of the second resistor of the resistor group RN9 and the second end of the third resistor of the resistor group RN9, the sixth input end of the interface J2 is connected to the second first resistor of the resistor group RN9 and the second fourth resistor of the resistor group RN10, the seventh input end of the interface J2 is connected to the second resistor of the resistor group RN10 and the second third resistor of the resistor group RN10, the eighth input end of the interface J2 is connected to the second first resistor of the resistor group RN10 and the +5V power supply, and the second fourth resistor of the resistor group RN9 is connected to ground. Connecting an output first end of the interface J2 with an input first end of the interface J2 through a jumper cap, or connecting an output second end of the interface J2 with an input second end of the interface J2 through a jumper cap, or connecting an output third end of the interface J2 with an input third end of the interface J2 through a jumper cap, or connecting an output fourth end of the interface J2 with an input fourth end of the interface J2 through a jumper cap, or connecting an output fifth end of the interface J2 with an input fifth end of the interface J2 through a jumper cap, or connecting an output sixth end of the interface J2 with an input sixth end of the interface J2 through a jumper cap, or connecting an output seventh end of the interface J2 with an input seventh end of the interface J2 through a jumper cap, or connecting an output eighth end of the interface J2 with an input eighth end of the interface J2 through a jumper cap; different voltage values are input to correspondingly set the maximum rotating speed of the fan.

The utility model discloses an among the preferred embodiment, still include fan rotational speed gear display module on the controller, fan rotational speed gear display module includes: a data terminal PD4(HS)/TIM2_ CH1[ BEEP ] of the processor U1 is connected with a first terminal of a resistor R25, a second terminal of a resistor R25 is connected with a data terminal DIN of a display driving chip U8, a power supply terminal VDD of the display driving chip U8 is respectively connected with a +5V power supply and a first terminal of a capacitor C27, and a power supply ground terminal GND of the display driving chip U8 is respectively connected with a power supply ground and a second terminal of the capacitor C27;

seven-segment data ends A of a display driving chip U8 are connected with seven-segment data ends A of a seven-segment nixie tube LED2, seven-segment data ends B of a display driving chip U8 are connected with seven-segment data ends B of a seven-segment nixie tube LED2, seven-segment data ends C of a display driving chip U8 are connected with seven-segment data ends C of a seven-segment nixie tube LED2, seven-segment data ends D of a display driving chip U8 are connected with seven-segment data ends D of a seven-segment nixie tube LED2, seven-segment data ends E of a display driving chip U8 are connected with seven-segment data ends E of a seven-segment nixie tube LED2, seven-segment data ends F of a display driving chip U8 are connected with seven-segment data ends F of a seven-segment nixie tube LED 9648, seven-segment data ends G of a display driving chip U8 are connected with seven-segment data ends G of a seven-segment nixie tube LED2, data ends H638 of a display driving chip U2 are connected with data ends GR 638, and a common data end DP driving chip DP tube GR is connected with a display driving chip DP 638. During the fan test, the processor U1 inputs the fan rotational speed to the fan rotational speed gear display module, shows the fan rotational speed gear of test on the seven-segment digital tube LED2, the tester of being convenient for tests.

The utility model discloses an in the preferred embodiment, still include display screen data acquisition module on the controller, display screen data acquisition module includes: a display screen data acquisition terminal [ TIM1_ CH2N ] AIN1/PB1 of the processor U1 is respectively connected to a first terminal of a resistor R24, a first terminal of a resistor R26, and a first terminal of a capacitor C23, a second terminal of the resistor R24 is respectively connected to a first terminal of a capacitor C22 and an output terminal of the interface J8, a ground terminal of the interface J8 is connected to a power ground, and a second terminal of the capacitor C22, a second terminal of the capacitor C23, and a second terminal of the resistor R26 are respectively connected to the power ground. The interface J8 is connected with the data output end of the display screen, and the data output end of the display screen outputs 0V-10V level signals to realize the acquisition of the data of the display screen.

The utility model discloses an in a preferred embodiment, still include fan pulse number setting module on the controller, fan pulse number setting module includes: data terminal PG0 of processor U1 is connected to the first resistor first terminal of resistor group RN7 and the first switch first terminal of switch group SW1, data terminal PG1 of processor U1 is connected to the second resistor first terminal of resistor group RN7 and the second switch first terminal of switch group SW1, data terminal PE3/TIM1_ BKIN of processor U1 is connected to the third resistor first terminal of resistor group RN7 and the third switch first terminal of switch group SW1, data terminal PE 6327 (HS)/CLK _ CCO of processor U1 is connected to the fourth resistor first terminal of resistor group RN7 and the fourth switch first terminal of switch group SW1, data terminal PE1(T)/I2 1_ SCL of processor U1 is connected to the third resistor first terminal of resistor group RN1 and the fifth switch first terminal of switch group SW1, and data terminal PE1(T)/I2 _ 1_ SCL of processor U1 is connected to the first terminal of resistor group RN1 and the first terminal of switch group SW1, respectively SDA 1 are connected to the fourth switch group SW 1;

a second end of a first resistor of the resistor group RN7, a second end of a second resistor of the resistor group RN7, a second end of a third resistor of the resistor group RN7, a second end of a fourth resistor of the resistor group RN7, a second end of a third resistor of the resistor group RN8 and a second end of a fourth resistor of the resistor group RN8 are respectively connected with a power ground;

the first switch second terminal of the switch group SW1, the second switch second terminal of the switch group SW1, the third switch second terminal of the switch group SW1, the fourth switch second terminal of the switch group SW1, the fifth switch second terminal of the switch group SW1 and the sixth switch second terminal of the switch group SW1 are respectively connected to the power ground. The setting of the number of pulses of the fan is realized by switching on and switching off the switch of the switch group SW1, and the number of the pulses is 0-63.

To sum up, owing to adopted above-mentioned technical scheme, the utility model discloses can be through the rotational speed of intelligent adaptation fan intelligent regulation fan.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a schematic block diagram of the connection of the present invention.

Fig. 3 is a schematic diagram of the processor circuit connection according to the present invention.

Fig. 4 is the circuit connection schematic diagram of the fan rotation speed acquisition module of the present invention.

Fig. 5 is a schematic diagram of the circuit connection of the second fan rotation speed acquisition module of the present invention.

Fig. 6 is a schematic diagram of the third fan rotation speed acquisition module circuit connection of the present invention.

Fig. 7 is a schematic diagram of the power module circuit connection of the present invention.

Fig. 8 is a schematic diagram of the circuit connection of the key test input module of the present invention.

Fig. 9 is a schematic diagram of the data conversion module circuit connection according to the present invention.

Fig. 10 is a schematic diagram of the circuit connection of the fan driving module of the present invention.

Fig. 11 is the utility model discloses fan rotational speed gear sets up module circuit connection schematic diagram.

Fig. 12 is a schematic diagram of the circuit connection of the second fan rotation speed gear setting module of the present invention.

Fig. 13 is a schematic diagram of the third fan rotation speed gear setting module circuit connection.

Fig. 14 is a circuit connection schematic diagram of the fan rotation speed gear display module of the present invention.

Fig. 15 is the display screen data acquisition module circuit connection schematic diagram of the present invention.

Fig. 16 is a schematic diagram of the circuit connection of the pulse number setting module of the blower according to the present invention.

Fig. 17 is the circuit connection schematic diagram of the SPI interface module of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

The utility model provides a distributed intelligent adaptive power module, as shown in figure 1, comprising a case, wherein a cavity partition is arranged in the case, the cavity partition divides the case into a fan cavity and an air outlet noise reduction cavity, an air passing hole is arranged on the cavity partition, an air inlet communicated with the fan cavity and an air outlet communicated with the air outlet noise reduction cavity are arranged on the case, and the air passing hole and the air outlet are arranged in a staggered manner; still include the fan intracavity is installed an intelligent adaptation fan, and the air current that supplies to come out from intelligent adaptation fan gets into the air-out and falls the chamber of making an uproar.

In a preferred embodiment of the present invention, the intelligent fan comprises a fan and a controller connected to the fan, and the fan and the controller can be integrated together or can be separate modules. The controller comprises a processor U1 and a fan rotating speed acquisition module connected with the processor U1; the fan rotating speed acquisition module is a first fan rotating speed acquisition module; in this embodiment, as shown in fig. 3, the I/0 power ground VSSIO _1 of the processor U1 and the digital power ground VSS of the processor U1 are respectively connected to the first terminal of the capacitor C3 and the power ground, and the second terminal of the capacitor C3 is connected to the voltage regulator capacitor terminal VCAP of the processor U1; digital power supply terminal VDD of processor U1 and I/O power supply terminal VDDIO _1 of processor U1 are connected to the first terminal of capacitor C4, the first terminal of capacitor C5, the first terminal of capacitor C6 and the +5V power supply, respectively, the second terminal of capacitor C4, the second terminal of capacitor C5 and the second terminal of capacitor C6 are connected to power ground, respectively; an analog power supply end VDDA of the processor U1 is respectively connected with a first end of the capacitor C8, a first end of the capacitor C9 and a +5V power supply, and an analog power supply ground end VSSA of the processor U1 is respectively connected with a second end of the capacitor C8, a second end of the capacitor C9 and a power supply ground; an I/O power supply terminal VDDIO _2 of the processor U1 is respectively connected with a first terminal of the capacitor C10 and the +5V power supply, and an I/O power supply ground terminal VSSIO _2 of the processor U1 is respectively connected with a second terminal of the capacitor C10 and the power ground; a restart terminal NRST of the processor U1 is respectively connected with a first terminal of a capacitor C7, a first terminal of a resistor R1 and a third terminal of a restart interface P1, a second terminal of the capacitor C7 is connected with a power ground, a second terminal of a resistor R1 is connected with a +5V power supply, a second terminal of a restart interface P1 is connected with a SWIM data terminal PD1(HS)/SWIM of the processor U1, a first terminal of a restart interface P1 is connected with the +5V power supply, and a fourth terminal of the restart interface P1 is connected with the power ground; in this embodiment, the capacitance values of the capacitor C3, the capacitor C6, the capacitor C7, the capacitor C9 and the capacitor C10 are 0.1uF, the capacitance value of the capacitor C4 is 10uF, the capacitance values of the capacitor C5 and the capacitor C8 are 1uF, the resistance value of the resistor R1 is 10K, and the model of the processor U1 is STM8S005C6T 6.

First fan rotational speed collection module includes: as shown in fig. 2 to 4, a fan rotation speed data input terminal PC4(HS)/TIM1_ CH4 of the processor U1 is respectively connected to a first terminal of a resistor R60 and a collector of a transistor Q7, a second terminal of a resistor R60 is connected to a +5V power supply, an emitter of the transistor Q7 is respectively connected to a power ground and a first terminal of the resistor R46, a second terminal of a resistor R46 and a base of the transistor Q7 are respectively connected to a first terminal of a resistor R5 and a fan rotation speed output terminal speed of the fan interface P2, a second terminal of a resistor R5 is respectively connected to a first terminal of a capacitor C38 and a power output terminal +10V of the fan interface P2, and a second terminal of the capacitor C38 is connected to the power ground. In this embodiment, the resistances of the resistor R60, the resistor R46, and the resistor R5 are 10K, the capacitance of the capacitor C38 is 4.7uF, the fan interface P2 adopts a 5.08 screw connector, and the transistor Q7 is an NPN-type transistor, specifically, a patch Y1.

The utility model discloses an in the preferred embodiment, still include fan rotational speed input module on the controller, this fan rotational speed input module is first fan rotational speed input module, and first rotational speed output module includes: as shown in fig. 2 to 4, a fan rotation speed data output terminal PC2(HS) TIM1_ CH2 of the processor U1 is connected to a first terminal of a resistor R13, a second terminal of a resistor R13 is connected to a first terminal of a resistor R14 and a first terminal of a capacitor C14, a second terminal of the resistor R14 is connected to a first terminal of a capacitor C15 and a non-inverting input terminal of the amplifier U3A, and a second terminal of the capacitor C14 and a second terminal of the capacitor C15 are connected to a power ground; the inverting input end of the amplifier U3A is respectively connected with the first end of a resistor R9 and the first end of a resistor R10, the second end of the resistor R9 is connected with a power ground, the second end of a resistor R10 is respectively connected with the output end of the amplifier U3A and the first end of a resistor R43, the second end of the resistor R43 is respectively connected with the first end of a capacitor C31, the cathode of a diode DZ2 and the fan rotating speed data input end pwm of a fan interface P2, the second end of a capacitor C31 is connected with the power ground, and the anode of the diode DZ2 is connected with the power ground; the ground terminal of the blower interface P2 is connected to power ground. In this embodiment, the resistances of the resistor R9, the resistor R13, and the resistor R14 are 1K, the resistance of the resistor R10 is 3.3K, the resistance of the resistor R43 is 110 Ω, the capacitances of the capacitor C14, the capacitor C15, and the capacitor C31 are 10uF, the model of the amplifier U3A is LM258DRG4, and the diode DZ2 is a 12V voltage regulator.

The utility model discloses an in the preferred embodiment, still include second fan rotational speed collection module on the controller, second fan rotational speed collection module includes: as shown in fig. 2, 3 and 5, the fan speed data input terminal PE5/SPI _ NSS of the processor U1 is respectively connected to the first terminal of the resistor R61 and the collector of the transistor Q8, the second terminal of the resistor R61 is connected to the +5V power supply, the emitter of the transistor Q8 is respectively connected to the power ground and the first terminal of the resistor R47, the second terminal of the resistor R47 and the base of the transistor Q8 are respectively connected to the first terminal of the resistor R22 and the fan speed output terminal speed of the fan interface P3, the second terminal of the resistor R22 is respectively connected to the first terminal of the capacitor C39 and the power output terminal +10V of the fan interface P3, and the second terminal of the capacitor C39 is connected to the power ground. In this embodiment, the resistances of the resistor R61, the resistor R47, and the resistor R22 are 10K, the capacitance of the capacitor C39 is 4.7uF, the fan interface P3 adopts a 5.08 screw connector, and the transistor Q8 is an NPN-type transistor, specifically, a patch Y1.

The utility model discloses an in the preferred embodiment, still include second fan rotational speed input module on the controller, second fan rotational speed input module includes: as shown in fig. 2, 3 and 5, the fan speed data output terminal PC1(HS) TIM1_ CH1/UART2_ CK of the processor U1 is connected to a first terminal of a resistor R19, a second terminal of a resistor R19 is connected to a first terminal of a resistor R20 and a first terminal of a capacitor C20, a second terminal of a resistor R20 is connected to a first terminal of a capacitor C21 and a non-inverting input terminal of the amplifier U3B, and a second terminal of the capacitor C20 and a second terminal of the capacitor C21 are connected to the power ground; power supply terminals of an amplifier U3B are respectively connected with a +12V power supply and a first end of a capacitor C18, a second end of a capacitor C18 is connected with a power ground, a power ground terminal of an amplifier U3B is connected with the power ground, an inverting input terminal of the amplifier U3B is respectively connected with a first end of a resistor R17 and a first end of a resistor R18, a second end of the resistor R17 is connected with the power ground, a second end of the resistor R18 is respectively connected with an output terminal of the amplifier U3B and a first end of a resistor R44, a second end of the resistor R44 is respectively connected with a first end of the capacitor C32, a negative electrode of a diode DZ4 and a fan rotating speed data input terminal pwm of a fan interface P3, a second end of the capacitor C32 is connected with the power ground, and an anode of the diode DZ4 is connected with; the ground terminal of the blower interface P3 is connected to power ground. In this embodiment, the resistances of the resistor R17, the resistor R19, and the resistor R20 are 1K, the resistance of the resistor R18 is 3.3K, the resistance of the resistor R44 is 110 Ω, the capacitances of the capacitor C20, the capacitor C21, and the capacitor C32 are 10uF, the capacitance of the capacitor C18 is 0.1uF, the diode DZ4 is a 12V voltage regulator, the amplifier U3B is LM258DRG4, and the amplifier U3A and the amplifier U3B share one dual operational amplifier.

The utility model discloses an in the preferred embodiment, still include third fan rotational speed collection module on the controller, third fan rotational speed collection module includes: as shown in fig. 2, 3 and 6, a fan speed data input terminal PD2(HS) TIM3_ CH1[ TIM2_ CH3] of the processor U1 is respectively connected to a first terminal of a resistor R62 and a collector of a transistor Q9, a second terminal of the resistor R62 is connected to a +5V power supply, an emitter of a transistor Q9 is respectively connected to a power ground and a first terminal of the resistor R45, a second terminal of the resistor R45 and a base of the transistor Q9 are respectively connected to a first terminal of the resistor R6 and a fan speed output terminal speed of the fan interface P4, a second terminal of the resistor R6 is respectively connected to a first terminal of a capacitor C37 and a power output terminal +10V of the fan interface P4, and a second terminal of the capacitor C37 is connected to the power ground. In this embodiment, the resistances of the resistor R62, the resistor R45, and the resistor R6 are 10K, the capacitance of the capacitor C37 is 4.7uF, the fan interface P4 adopts a 5.08 screw connector, and the transistor Q9 is an NPN-type transistor, specifically, a patch Y1.

The utility model discloses an in the preferred embodiment, still include third fan rotational speed input module on the controller, third fan rotational speed input module includes: as shown in fig. 2, 3 and 6, a fan speed data output terminal PC3(HS) TIM1_ CH3 of the processor U1 is connected to a first terminal of a resistor R15, a second terminal of a resistor R15 is connected to a first terminal of a resistor R16 and a first terminal of a capacitor C16, a second terminal of the resistor R16 is connected to a first terminal of a capacitor C17 and a non-inverting input terminal of the amplifier U3C, and a second terminal of the capacitor C16 and a second terminal of the capacitor C17 are connected to a power ground; power supply ends of an amplifier U3C are respectively connected with a first end of a capacitor C19 and a +12V power supply, a second end of a capacitor C19 is connected with a power supply ground, a power supply ground end of an amplifier U3C is connected with the power supply ground, an inverting input end of an amplifier U3C is respectively connected with a first end of a resistor R11 and a first end of a resistor R12, a second end of a resistor R11 is connected with the power supply ground, a second end of a resistor R12 is respectively connected with an output end of the amplifier U3C and a first end of a resistor R42, a second end of a resistor R42 is respectively connected with a first end of a capacitor C30, a negative electrode of a diode DZ3 and a fan rotating speed data input end pwm of a fan interface P4, a second end of a capacitor C30 is connected with the power supply ground, and an anode of a diode DZ 39; the ground terminal of the blower interface P4 is connected to power ground. In this embodiment, the resistances of the resistor R11, the resistor R15, and the resistor R16 are 1K, the resistance of the resistor R12 is 3.3K, the resistance of the resistor R42 is 110 Ω, the capacitances of the capacitor C16, the capacitor C17, and the capacitor C30 are 10uF, the capacitance of the capacitor C19 is 0.1uF, the diode DZ3 is a 12V voltage regulator, and the amplifier U3C is LM258DRG 4.

In a preferred embodiment of the present invention, the controller further includes a power module, and the power module includes: as shown IN fig. 2 and 7, the negative power terminal of the power interface J1 is connected to the power ground, the positive power terminal of the power interface J1 is connected to the first terminal of the capacitor C34, the first terminal of the capacitor C13 and the power voltage terminal IN of the voltage chip U2, and the second terminal of the capacitor C34 and the second terminal of the capacitor C13 are connected to the power ground; the switch output end SW of the voltage chip U2 is respectively connected with the first end of a capacitor C1 and the first end of an inductor L1, the second end of the capacitor C1 is connected with the first end of a resistor R4, the second end of a resistor R4 is connected with the leading end BST of the voltage chip U2, the second end of the inductor L1 is respectively connected with the first end of the capacitor C11 and the first end of a capacitor C12, an anode of the indicator light LED1, a first end of a capacitor C35 and a first end of a resistor R8 are connected, a second end of the capacitor C11 and a second end of the capacitor C12 are respectively connected with a power ground, a cathode of the indicator light LED1 is connected with a first end of a resistor R2, a second end of the resistor R2 is connected with the power ground, a second end of the resistor R8 is respectively connected with a first end of a resistor R7 and a first end of a resistor R21, a second end of the resistor R21 is connected with the power ground, a second end of the capacitor C35 is connected with a first end of a resistor R23, and a second end of the resistor R23 and a second end of the resistor R7 are respectively connected with a feedback end FB of the voltage chip U2; an enable terminal EN of the voltage chip U2 is respectively connected with a first terminal of the resistor R3 and a first terminal of the capacitor C2, a second terminal of the capacitor C2 is connected with a power ground, and a second terminal of the resistor R3 is connected with a power positive terminal of the power interface J1. In this embodiment, the resistance value of the resistor R2 is 680 Ω, the resistance value of the resistor R4 is 10 Ω, the resistance value of the resistor R3 is 100K, the resistance value of the resistor R7 is 75K, the resistance value of the resistor R8 is 40.2K, the resistance value of the resistor R21 is 7.86K, the resistance value of the resistor R23 is 10K, the capacitance values of the capacitor C12 and the capacitor C34 are 22uF, the capacitance values of the capacitor C11, the capacitor C13, the capacitor C1, the capacitor C2 and the capacitor C35 are 0.1uF, the capacitance value of the inductor L1 is 6.8uH, the model number of the voltage chip U2 is MP1470GJ-Z, and the power interface J1 adopts a 5.08 screw type connector.

The utility model discloses an in the preferred embodiment, still include the button test input module on the controller, this button test input module is the first fan input module of button test, and the first fan input module of button test includes: as shown in fig. 2, 3 and 8, a first terminal of key K1 is connected to power ground, a second terminal of key K1 is connected to a first terminal of resistor R33 and a first terminal of resistor R34, respectively, a second terminal of resistor R33 is connected to +5V power, and a second terminal of resistor R34 is connected to a key data input PD3(HS)/TIM2_ CH2[ ADC _ ETR ] of processor U1. In this embodiment, the resistance of the resistor R33 is 100K, and the resistance of the resistor R34 is 470 Ω.

Still include button test second fan input module on the controller, button test second fan input module includes: as shown in FIGS. 2, 3 and 8, a first terminal of key K2 is coupled to power ground, a second terminal of key K2 is coupled to a first terminal of resistor R35 and a first terminal of resistor R36, respectively, a second terminal of resistor R35 is coupled to +5V power, and a second terminal of resistor R36 is coupled to a key data input PD0(HS)/TIM3_ CH2[ TIM1_ BKIN ] [ CLK _ CCO ] of processor U1. In this embodiment, the resistance of the resistor R35 is 100K, and the resistance of the resistor R36 is 470 Ω.

Still include the third fan input module of button test on the controller, the third fan input module of button test includes: as shown in fig. 2, 3 and 8, a first terminal of key K3 is connected to power ground, a second terminal of key K3 is connected to a first terminal of resistor R37 and a first terminal of resistor R38, respectively, a second terminal of resistor R37 is connected to a +5V power supply, and a second terminal of resistor R38 is connected to a key data input PC7(HS)/SPI _ MISO of processor U1. In this embodiment, the resistance of the resistor R37 is 100K, and the resistance of the resistor R38 is 470 Ω.

In a preferred embodiment of the present invention, the controller further includes a data conversion module, and the data conversion module includes: as shown in fig. 2, 3 and 9, the enable terminal PD7/TLI [ TIM1_ CH4] of the processor U1 is connected to the first terminal of the resistor R30, the driver output enable terminal DE of the data conversion chip U7 and the receiver output enable terminal RE of the data conversion chip U7, respectively, and the second terminal of the resistor R30 is connected to the +5V power supply; the receiver output RO of the data conversion chip U7 is connected to the data input PD6/UART2_ RX of the processor U1, and the driver input DI of the data conversion chip U7 is connected to the data output PD5/UART2_ TX of the processor U1; a power supply voltage terminal VCC of the data conversion chip U7 is respectively connected with a +5V power supply and a first terminal of a capacitor C26, and a second terminal of the capacitor C26 is connected with a power supply ground; the power ground terminal GND of the data conversion chip U7 is connected with the power ground; the data terminal B of the data conversion chip U7 is connected to the first terminal of the resistor R27, the second terminal of the resistor R27 is connected to the first terminal of the resistor R28, the first terminal of the resistor R32, the first terminal of the transient suppression diode Z2 and the first terminal of the fuse F1, the second terminal of the resistor R32 is connected to the power ground, the data terminal A of the data conversion chip U7 is connected to the first terminal of the resistor R29, the second terminal of the resistor R29 is connected to the second terminal of the resistor R28, a first terminal of the resistor R31, a first terminal of the transient suppression diode Z1 and a first terminal of the fuse F2 are connected, a second terminal of the resistor R31 is connected to a +5V power supply, a second terminal of the transient suppression diode Z1 and a second terminal of the transient suppression diode Z2 are respectively connected to a power ground, a second terminal of the fuse F1 is connected to a data first terminal of the data interface P8, and a second terminal of the fuse F2 is connected to a data second terminal of the data interface P8. In this embodiment, the resistance of the resistor R30 is 10K, the resistances of the resistor R27 and the resistor R29 are 100 Ω, the resistance of the resistor R28 is 120 Ω, the resistances of the resistor R31 and the resistor R32 are 10K, the types of the transient suppression diode Z1 and the transient suppression diode Z2 are P0080SA, the current of the fuse F1 and the current of the fuse F2 are limited to 140mA, the data interface P8 is a 485 connector, the capacitance of the capacitor C26 is 0.1uF, and the type of the data conversion chip U7 is SSP 485.

The utility model discloses an in the preferred embodiment, still include fan drive module on the controller, this fan drive module is first fan drive module, and first fan drive module includes: as shown in fig. 2, 3 and 10, the driving data terminal [ TIM1_ CH3N ] AIN2/PB2 of the processor U1 is connected to the driving input terminal 1B of the driving chip U5, the driving data terminal [ TIM1_ ETR/AIN3/PB3 of the processor U1 is connected to the driving input terminal 2B of the driving chip U5, the driving data terminal [ I2C _ SCL ] AIN4/PB4 of the processor U1 is connected to the driving input terminal 3B of the driving chip U5, and the driving data terminal [ I2C _ SDA ] AIN5/PB5 of the processor U1 is connected to the driving input terminal 4B of the driving chip U5;

the common terminal COM of the driver chip U5 is connected to the +12V power supply and the first terminal of the capacitor C24, respectively, and the common ground terminal E of the driver chip U5 is connected to the power ground and the second terminal of the capacitor C24, respectively. In this embodiment, the driver chip U5 is a chip of ULN200xx series, and the capacitance value of the capacitor C24 is 0.1 uF.

The utility model discloses an in a preferred embodiment, still include second fan drive module on the controller, second fan drive module includes: as shown in fig. 2, 3 and 10, the driving data terminals AIN6/PB6 of the processor U1 are connected to the driving input terminal 5B of the driving chip U5, the driving data terminals AIN7/PB7 of the processor U1 are connected to the driving input terminal 6B of the driving chip U5, the driving data terminal (HS) PA6 of the processor U1 is connected to the driving input terminal 2B of the driving chip U6, and the driving data terminal (HS) PA5 of the processor U1 is connected to the driving input terminal 3B of the driving chip U6;

a drive output end 5C of a drive chip U5 is connected with a first drive input end of a fan drive interface P6, a drive output end 6C of a drive chip U5 is connected with a second drive input end of a fan drive interface P6, a drive output end 2C of the drive chip U6 is connected with a third drive input end of a fan drive interface P6, a drive output end 3C of a drive chip U6 is connected with a fourth drive input end of a fan drive interface P6, and a power supply end of the fan drive interface P6 is connected with a +12V power supply;

the common terminal COM of the driver chip U6 is connected to the +12V power supply and the first terminal of the capacitor C25, respectively, and the common ground terminal E of the driver chip U6 is connected to the power ground and the second terminal of the capacitor C25, respectively. In this embodiment, the driver chip U6 is a chip of ULN200xx series, and the capacitance value of the capacitor C25 is 0.1 uF.

The utility model discloses an in a preferred embodiment, still include third fan drive module on the controller, third fan drive module includes: as shown in fig. 2, 3 and 10, the driving data terminal (HS) PA4 of the processor U1 is connected to the driving input terminal 4B of the driving chip U6, and the driving data terminal [ TIM3_ CH1] TIM2_ CH3/PA3 of the processor U1 is connected to the driving input terminal 5B of the driving chip U6; the driving data end OSCOUT/PA2 of the processor U1 is connected to the driving input end 6B of the driving chip U6, and the driving data end OSCIN/PA1 of the processor U1 is connected to the driving input end 7B of the driving chip U6;

a drive output end 4C of a drive chip U6 is connected with a first drive input end of a fan drive interface P7, a drive output end 5C of a drive chip U6 is connected with a second drive input end of a fan drive interface P7, a drive output end 6C of the drive chip U6 is connected with a third drive input end of a fan drive interface P7, a drive output end 7C of a drive chip U6 is connected with a fourth drive input end of a fan drive interface P7, and a power supply end of the fan drive interface P7 is connected with a +12V power supply;

the utility model discloses an in the preferred embodiment, still include fan rotational speed gear setting module on the controller, this fan rotational speed gear setting module sets up the module for first fan rotational speed gear, and first fan rotational speed gear sets up the module and includes: as shown in fig. 2, 3 and 11, the data input terminal [ TIM1_ CH1N ] AIN0/PB0 of the processor U1 is respectively connected to the first output terminal of the interface J2, the second output terminal of the interface J2, the third output terminal of the interface J2, the fourth output terminal of the interface J2, the fifth output terminal of the interface J2, the sixth output terminal of the interface J2, the seventh output terminal of the interface J2 and the eighth output terminal of the interface J2;

the fifth input end of the interface J2 is connected to the second end of the second resistor of the resistor group RN9 and the second end of the third resistor of the resistor group RN9, the sixth input end of the interface J2 is connected to the second first resistor of the resistor group RN9 and the second fourth resistor of the resistor group RN10, the seventh input end of the interface J2 is connected to the second resistor of the resistor group RN10 and the second third resistor of the resistor group RN10, the eighth input end of the interface J2 is connected to the second first resistor of the resistor group RN10 and the +5V power supply, and the second fourth resistor of the resistor group RN9 is connected to ground. In this embodiment, the interface J2 has a model number HDR2x8, and the resistances of the first to fourth resistors in the resistor group RN9 and the resistor group RN10 are 10K. The resistors in the resistor group RN9 are a first resistor, a second resistor, a third resistor and a fourth resistor from right to left in sequence; the resistors in the resistor group RN10 are a first resistor, a second resistor, a third resistor and a fourth resistor in sequence from right to left.

The utility model discloses an among the preferred embodiment, still include second fan rotational speed gear setting module on the controller, second fan rotational speed gear setting module includes: as shown in fig. 2, 3 and 12, the data input terminal AIN8/PE7 of the processor U1 is respectively connected to the first output terminal of the interface J3, the second output terminal of the interface J3, the third output terminal of the interface J3, the fourth output terminal of the interface J3, the fifth output terminal of the interface J3, the sixth output terminal of the interface J3, the seventh output terminal of the interface J3 and the eighth output terminal of the interface J3;

a first input end of a interface J3 is connected to a first resistor end of the resistor group RN12 and a first second resistor end of the resistor group RN12, a second input end of the interface J3 is connected to a first third resistor end of the resistor group RN12 and a first fourth resistor end of the resistor group RN12, a third input end of the interface J3 is connected to a first resistor end of the resistor group RN11 and a first second resistor end of the resistor group RN11, and a fourth input end of the interface J3 is connected to a first third resistor end of the resistor group RN11 and a first fourth resistor end of the resistor group RN 11;

the fifth input end of the interface J3 is connected to the second end of the second resistor of the resistor group RN11 and the second end of the third resistor of the resistor group RN11, the sixth input end of the interface J3 is connected to the second first resistor of the resistor group RN11 and the second fourth resistor of the resistor group RN12, the seventh input end of the interface J3 is connected to the second resistor of the resistor group RN12 and the second third resistor of the resistor group RN12, the eighth input end of the interface J3 is connected to the second first resistor of the resistor group RN12 and the +5V power supply, and the second fourth resistor of the resistor group RN11 is connected to ground. In this embodiment, the interface J3 has a model number HDR2x8, and the resistances of the first to fourth resistors in the resistor group RN11 and the resistor group RN12 are 10K. The resistors in the resistor group RN11 are a first resistor, a second resistor, a third resistor and a fourth resistor from right to left in sequence; the resistors in the resistor group RN12 are a first resistor, a second resistor, a third resistor and a fourth resistor in sequence from right to left.

The utility model discloses an among the preferred embodiment, still include third fan rotational speed gear setting module on the controller, third fan rotational speed gear setting module includes: as shown in fig. 2, 3 and 13, the data input terminal AIN9/PE6 of the processor U1 is respectively connected to the first output terminal of the interface J4, the second output terminal of the interface J4, the third output terminal of the interface J4, the fourth output terminal of the interface J4, the fifth output terminal of the interface J4, the sixth output terminal of the interface J4, the seventh output terminal of the interface J4 and the eighth output terminal of the interface J4;

a first input end of a interface J4 is connected to a first resistor end of the resistor group RN14 and a first second resistor end of the resistor group RN14, a second input end of the interface J4 is connected to a first third resistor end of the resistor group RN14 and a first fourth resistor end of the resistor group RN14, a third input end of the interface J4 is connected to a first resistor end of the resistor group RN13 and a first second resistor end of the resistor group RN13, and a fourth input end of the interface J4 is connected to a first third resistor end of the resistor group RN13 and a first fourth resistor end of the resistor group RN 13;

the fifth input end of the interface J4 is connected to the second end of the second resistor of the resistor group RN13 and the second end of the third resistor of the resistor group RN13, the sixth input end of the interface J4 is connected to the second first resistor of the resistor group RN13 and the second fourth resistor of the resistor group RN14, the seventh input end of the interface J4 is connected to the second resistor of the resistor group RN14 and the second third resistor of the resistor group RN14, the eighth input end of the interface J4 is connected to the second first resistor of the resistor group RN14 and the +5V power supply, and the second fourth resistor of the resistor group RN13 is connected to ground. In this embodiment, the interface J4 has a model number HDR2x8, and the resistances of the first to fourth resistors in the resistor group RN13 and the resistor group RN14 are 10K. The resistors in the resistor group RN13 are a first resistor, a second resistor, a third resistor and a fourth resistor from right to left in sequence; the resistors in the resistor group RN14 are a first resistor, a second resistor, a third resistor and a fourth resistor in sequence from right to left.

The utility model discloses an in the preferred embodiment, still include fan rotational speed gear display module on the controller, this fan rotational speed gear display module is first fan rotational speed gear display module, and first fan rotational speed gear display module includes: as shown in fig. 2, 3 and 14, the data terminal PD4(HS)/TIM2_ CH1[ BEEP ] of the processor U1 is connected to the first terminal of the resistor R25, the second terminal of the resistor R25 is connected to the data terminal DIN of the display driver chip U8, the power terminal VDD of the display driver chip U8 is connected to the +5V power supply and the first terminal of the capacitor C27, and the power ground terminal GND of the display driver chip U8 is connected to the power ground and the second terminal of the capacitor C27, respectively;

seven-segment data ends A of a display driving chip U8 are connected with seven-segment data ends A of a seven-segment nixie tube LED2, seven-segment data ends B of a display driving chip U8 are connected with seven-segment data ends B of a seven-segment nixie tube LED2, seven-segment data ends C of a display driving chip U8 are connected with seven-segment data ends C of a seven-segment nixie tube LED2, seven-segment data ends D of a display driving chip U8 are connected with seven-segment data ends D of a seven-segment nixie tube LED2, seven-segment data ends E of a display driving chip U8 are connected with seven-segment data ends E of a seven-segment nixie tube LED2, seven-segment data ends F of a display driving chip U8 are connected with seven-segment data ends F of a seven-segment nixie tube LED 9648, seven-segment data ends G of a display driving chip U8 are connected with seven-segment data ends G of a seven-segment nixie tube LED2, data ends H638 of a display driving chip U2 are connected with data ends GR 638, and a common data end DP driving chip DP tube GR is connected with a display driving chip DP 638. In this embodiment, the model of the display driver chip U8 is TM3130, the seven-segment nixie tube LED2 is a 0.39-inch common anode nixie tube, the resistance of the resistor R25 is 100 Ω, and the capacitance of the capacitor C27 is 0.1 uF.

The utility model discloses an among the preferred embodiment, still include second fan rotational speed gear display module on the controller, second fan rotational speed gear display module includes: as shown in figure 2 of the drawings, in which, 3 and 14, a seven-segment data end A of a display driving chip U8 is connected with a seven-segment data end A of a seven-segment nixie tube LED3, a seven-segment data end B of a display driving chip U8 is connected with a seven-segment data end B of a seven-segment nixie tube LED3, a seven-segment data end C of a display driving chip U8 is connected with a seven-segment data end C of a seven-segment nixie tube LED3, a seven-segment data end D of a display driving chip U8 is connected with a seven-segment data end D of a seven-segment nixie tube LED3, a seven-segment data end E of a display driving chip U8 is connected with a seven-segment data end E of a seven-segment nixie tube LED3, a seven-segment data end F of a display driving chip U8 is connected with a seven-segment data end F of a seven-segment nixie tube LED3, a seven-segment data end G of a display driving chip U8 is connected with a seven-segment data end G of a seven-segment nixie tube LED3, a data end H of a display driving chip U8 is connected with a data end DP 638, and a common data end DP tube DP 638 is connected. In this embodiment, a 0.39 inch common anode nixie tube is used as the seven-segment nixie tube LED 3.

The utility model discloses an among the preferred embodiment, still include third fan rotational speed gear display module on the controller, third fan rotational speed gear display module includes: as shown in figure 2 of the drawings, in which, 3 and 14, a seven-segment data end A of a display driving chip U8 is connected with a seven-segment data end A of a seven-segment nixie tube LED4, a seven-segment data end B of a display driving chip U8 is connected with a seven-segment data end B of a seven-segment nixie tube LED4, a seven-segment data end C of a display driving chip U8 is connected with a seven-segment data end C of a seven-segment nixie tube LED4, a seven-segment data end D of a display driving chip U8 is connected with a seven-segment data end D of a seven-segment nixie tube LED4, a seven-segment data end E of a display driving chip U8 is connected with a seven-segment data end E of a seven-segment nixie tube LED4, a seven-segment data end F of a display driving chip U8 is connected with a seven-segment data end F of a seven-segment nixie tube LED4, a seven-segment data end G of a display driving chip U8 is connected with a seven-segment data end G of a seven-segment nixie tube LED4, a data end H of a display driving chip U8 is connected with a data end DP 638, and a common data end DP tube DP 638 is connected. In this embodiment, a 0.39 inch common anode nixie tube is used as the seven-segment nixie tube LED 4.

The utility model discloses an in the preferred embodiment, still include display screen data acquisition module on the controller, display screen data acquisition module includes: as shown in fig. 2, 3 and 15, the display screen data acquisition terminal [ TIM1_ CH2N ] AIN1/PB1 of the processor U1 is respectively connected to a first terminal of a resistor R24, a first terminal of a resistor R26 and a first terminal of a capacitor C23, a second terminal of the resistor R24 is respectively connected to a first terminal of a capacitor C22 and an output terminal of an interface J8, a ground terminal of the interface J8 is connected to a power ground, and a second terminal of the capacitor C22, a second terminal of the capacitor C23 and a second terminal of the resistor R26 are respectively connected to the power ground. In this embodiment, the resistances of the resistor R24 and the resistor R26 are 10K, the capacitances of the capacitor C22 and the capacitor C23 are 0.1uF, and the model number adopted by the interface J8 is HDR1x 4.

The utility model discloses an in a preferred embodiment, still include fan pulse number setting module on the controller, fan pulse number setting module includes: as shown in figure 2 of the drawings, in which, 3 and 16, data terminal PG0 of processor U1 is connected to the first terminal of the first resistor of resistor group RN7 and the first terminal of the first switch of switch group SW1, data terminal PG1 of processor U1 is connected to the first terminal of the second resistor of resistor group RN7 and the first terminal of the second switch of switch group SW1, data terminal PE3/TIM1_ BKIN of processor U1 is connected to the first terminal of the third resistor of resistor group RN7 and the first terminal of the third switch of switch group SW1, data terminal PE0(HS)/CLK _ CCO of processor U1 is connected to the first terminal of the fourth resistor of resistor group RN7 and the first terminal of the fourth switch of switch group SW1, data terminal PE1(T)/I2 _ RN 72 of processor U1 is connected to the first terminal of resistor group RN1 and the first terminal of the fifth switch of switch group SW 72, and data terminal PE1(T)/I2 _ RN1 of processor U1 is connected to the first terminal of resistor group RN1 and the first terminal of switch group SW1, and the first terminal of switch group SW 1;

the first switch second terminal of the switch group SW1, the second switch second terminal of the switch group SW1, the third switch second terminal of the switch group SW1, the fourth switch second terminal of the switch group SW1, the fifth switch second terminal of the switch group SW1 and the sixth switch second terminal of the switch group SW1 are respectively connected to the power ground. In the embodiment, the type of the switch group SW1 is DMR-06-V-T/R, and the resistance values of the first to fourth resistors in the resistor group RN7 and the resistor group RN8 are 100K. The switches in the switch group SW1 are a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch from top to bottom in sequence; the resistors in the resistor group RN7 are sequentially a first resistor, a second resistor, a third resistor and a fourth resistor from top to bottom, and the resistors in the resistor group RN8 are sequentially a first resistor, a second resistor, a third resistor and a fourth resistor from top to bottom.

The utility model discloses an in a preferred embodiment, still include SPI interface module on the controller, the SPI interface includes: as shown in fig. 2, 3 and 17, SPI data clock terminal PC5(HS)/SPI _ SCK of processor U1 is connected to the clock terminal of SPI interface J5, SPI data terminal PC6(HS)/SPI _ MOSI of processor U1 is connected to the data terminal of SPI interface J5; the power end of SPI interface J5 links to each other with +5V power, and the power ground terminal of SPI interface J5 links to each other with power ground. In this embodiment, the entire connection of the processor U1 to the SPI interface J5 is not given, but only a partial connection is given.

While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A distributed intelligent adaptive power module comprises a case and is characterized in that a cavity partition is arranged in the case, the cavity partition divides the case into a fan cavity and an air outlet noise reduction cavity, an air passing hole is formed in the cavity partition, an air inlet communicated with the fan cavity and an air outlet communicated with the air outlet noise reduction cavity are formed in the case, and the air passing hole and the air outlet are arranged in a staggered mode; still include the fan intracavity is installed an intelligent adaptation fan, and the air current that supplies to come out from intelligent adaptation fan gets into the air-out and falls the chamber of making an uproar.

2. The distributed smart power module of claim 1 wherein the smart fan includes a fan and a controller coupled to the fan, the controller including a processor U1 and a fan speed acquisition module coupled to the processor U1;

fan rotational speed collection module includes: a fan rotation speed data input terminal PC4(HS)/TIM1_ CH4 of the processor U1 is respectively connected to a first terminal of a resistor R60 and a collector of a transistor Q7, a second terminal of a resistor R60 is connected to a +5V power supply, an emitter of the transistor Q7 is respectively connected to a power ground and a first terminal of the resistor R46, a second terminal of a resistor R46 and a base of the transistor Q7 are respectively connected to a first terminal of a resistor R5 and a fan rotation speed output terminal speed of the fan interface P2, a second terminal of the resistor R5 is respectively connected to a first terminal of a capacitor C38 and a power output terminal +10V of the fan interface P2, and a second terminal of the capacitor C38 is connected to the power ground.

3. The distributed smart power module of claim 2 further comprising a fan speed input module on the controller, the fan speed input module comprising: a fan rotating speed data output end PC2(HS) TIM1_ CH2 of the processor U1 is connected with a first end of a resistor R13, a second end of a resistor R13 is respectively connected with a first end of a resistor R14 and a first end of a capacitor C14, a second end of the resistor R14 is respectively connected with a first end of a capacitor C15 and a non-inverting input end of an amplifier U3A, and a second end of a capacitor C14 and a second end of a capacitor C15 are respectively connected with a power ground; the inverting input end of the amplifier U3A is respectively connected with the first end of a resistor R9 and the first end of a resistor R10, the second end of the resistor R9 is connected with a power ground, the second end of a resistor R10 is respectively connected with the output end of the amplifier U3A and the first end of a resistor R43, the second end of the resistor R43 is respectively connected with the first end of a capacitor C31, the cathode of a diode DZ2 and the fan rotating speed data input end pwm of a fan interface P2, the second end of a capacitor C31 is connected with the power ground, and the anode of the diode DZ2 is connected with the power ground; the grounding end of the fan interface P2 is connected with the power ground;

or/and the controller further comprises a power supply module, wherein the power supply module comprises: the negative power supply end of the power supply interface J1 is connected with the power supply ground, the positive power supply end of the power supply interface J1 is respectively connected with the first end of the capacitor C34, the first end of the capacitor C13 and the power supply voltage end IN of the voltage chip U2, and the second end of the capacitor C34 and the second end of the capacitor C13 are respectively connected with the power supply ground; the switch output end SW of the voltage chip U2 is respectively connected with the first end of a capacitor C1 and the first end of an inductor L1, the second end of the capacitor C1 is connected with the first end of a resistor R4, the second end of a resistor R4 is connected with the leading end BST of the voltage chip U2, the second end of the inductor L1 is respectively connected with the first end of the capacitor C11 and the first end of a capacitor C12, an anode of the indicator light LED1, a first end of a capacitor C35 and a first end of a resistor R8 are connected, a second end of the capacitor C11 and a second end of the capacitor C12 are respectively connected with a power ground, a cathode of the indicator light LED1 is connected with a first end of a resistor R2, a second end of the resistor R2 is connected with the power ground, a second end of the resistor R8 is respectively connected with a first end of a resistor R7 and a first end of a resistor R21, a second end of the resistor R21 is connected with the power ground, a second end of the capacitor C35 is connected with a first end of a resistor R23, and a second end of the resistor R23 and a second end of the resistor R7 are respectively connected with a feedback end FB of the voltage chip U2; an enable terminal EN of the voltage chip U2 is respectively connected with a first terminal of the resistor R3 and a first terminal of the capacitor C2, a second terminal of the capacitor C2 is connected with a power ground, and a second terminal of the resistor R3 is connected with a power positive terminal of the power interface J1.

4. The distributed smart power module of claim 2 further comprising a key test input module on the controller, the key test input module comprising: the first terminal of the key K1 is connected to power ground, the second terminal of the key K1 is connected to the first terminal of the resistor R33 and the first terminal of the resistor R34, respectively, the second terminal of the resistor R33 is connected to +5V power, and the second terminal of the resistor R34 is connected to the key data input terminal PD3(HS)/TIM2_ CH2[ ADC _ ETR ] of the processor U1.

5. The distributed smart power module of claim 2 further comprising a data conversion module on the controller, the data conversion module comprising: an enable terminal PD7/TLI [ TIM1_ CH4] of the processor U1 is respectively connected with a first terminal of a resistor R30, a driver output enable terminal DE of a data conversion chip U7 and a receiver output enable terminal RE of a data conversion chip U7, and a second terminal of a resistor R30 is connected with a +5V power supply; the receiver output RO of the data conversion chip U7 is connected to the data input PD6/UART2_ RX of the processor U1, and the driver input DI of the data conversion chip U7 is connected to the data output PD5/UART2_ TX of the processor U1;

a power supply voltage terminal VCC of the data conversion chip U7 is respectively connected with a +5V power supply and a first terminal of a capacitor C26, and a second terminal of the capacitor C26 is connected with a power supply ground;

the power ground terminal GND of the data conversion chip U7 is connected with the power ground; the data terminal B of the data conversion chip U7 is connected to the first terminal of the resistor R27, the second terminal of the resistor R27 is connected to the first terminal of the resistor R28, the first terminal of the resistor R32, the first terminal of the transient suppression diode Z2 and the first terminal of the fuse F1, the second terminal of the resistor R32 is connected to the power ground, the data terminal A of the data conversion chip U7 is connected to the first terminal of the resistor R29, the second terminal of the resistor R29 is connected to the second terminal of the resistor R28, a first terminal of the resistor R31, a first terminal of the transient suppression diode Z1 and a first terminal of the fuse F2 are connected, a second terminal of the resistor R31 is connected to a +5V power supply, a second terminal of the transient suppression diode Z1 and a second terminal of the transient suppression diode Z2 are respectively connected to a power ground, a second terminal of the fuse F1 is connected to a data first terminal of the data interface P8, and a second terminal of the fuse F2 is connected to a data second terminal of the data interface P8.

6. The distributed smart power module of claim 2 further comprising a fan drive module on the controller, the fan drive module comprising: a driving data terminal [ TIM1_ CH3N ] AIN2/PB2 of the processor U1 is connected with a driving input terminal 1B of the driving chip U5, a driving data terminal [ TIM1_ ETR/AIN3/PB3 of the processor U1 is connected with a driving input terminal 2B of the driving chip U5, a driving data terminal [ I2C _ SCL ] AIN4/PB4 of the processor U1 is connected with a driving input terminal 3B of the driving chip U5, and a driving data terminal [ I2C _ SDA ] AIN5/PB5 of the processor U1 is connected with a driving input terminal 4B of the driving chip U5;

the common terminal COM of the driver chip U5 is connected to the +12V power supply and the first terminal of the capacitor C24, respectively, and the common ground terminal E of the driver chip U5 is connected to the power ground and the second terminal of the capacitor C24, respectively.

7. The distributed intelligent adaptive power module according to claim 2, further comprising a fan speed gear setting module on the controller, the fan speed gear setting module comprising: a data input end [ TIM1_ CH1N ] AIN0/PB0 of the processor U1 is respectively connected with a first output end of the interface J2, a second output end of the interface J2, a third output end of the interface J2, a fourth output end of the interface J2, a fifth output end of the interface J2, a sixth output end of the interface J2, a seventh output end of the interface J2 and an eighth output end of the interface J2;

the fifth input end of the interface J2 is connected to the second end of the second resistor of the resistor group RN9 and the second end of the third resistor of the resistor group RN9, the sixth input end of the interface J2 is connected to the second first resistor of the resistor group RN9 and the second fourth resistor of the resistor group RN10, the seventh input end of the interface J2 is connected to the second resistor of the resistor group RN10 and the second third resistor of the resistor group RN10, the eighth input end of the interface J2 is connected to the second first resistor of the resistor group RN10 and the +5V power supply, and the second fourth resistor of the resistor group RN9 is connected to ground.

8. The distributed smart power module of claim 2 further comprising a fan speed gear display module on the controller, the fan speed gear display module comprising: a data terminal PD4(HS)/TIM2_ CH1[ BEEP ] of the processor U1 is connected with a first terminal of a resistor R25, a second terminal of a resistor R25 is connected with a data terminal DIN of a display driving chip U8, a power supply terminal VDD of the display driving chip U8 is respectively connected with a +5V power supply and a first terminal of a capacitor C27, and a power supply ground terminal GND of the display driving chip U8 is respectively connected with a power supply ground and a second terminal of the capacitor C27;

seven-segment data ends A of a display driving chip U8 are connected with seven-segment data ends A of a seven-segment nixie tube LED2, seven-segment data ends B of a display driving chip U8 are connected with seven-segment data ends B of a seven-segment nixie tube LED2, seven-segment data ends C of a display driving chip U8 are connected with seven-segment data ends C of a seven-segment nixie tube LED2, seven-segment data ends D of a display driving chip U8 are connected with seven-segment data ends D of a seven-segment nixie tube LED2, seven-segment data ends E of a display driving chip U8 are connected with seven-segment data ends E of a seven-segment nixie tube LED2, seven-segment data ends F of a display driving chip U8 are connected with seven-segment data ends F of a seven-segment nixie tube LED 9648, seven-segment data ends G of a display driving chip U8 are connected with seven-segment data ends G of a seven-segment nixie tube LED2, data ends H638 of a display driving chip U2 are connected with data ends GR 638, and a common data end DP driving chip DP tube GR is connected with a display driving chip DP 638.

9. The distributed smart power module of claim 2 further comprising a display screen data acquisition module on the controller, the display screen data acquisition module comprising: a display screen data acquisition terminal [ TIM1_ CH2N ] AIN1/PB1 of the processor U1 is respectively connected to a first terminal of a resistor R24, a first terminal of a resistor R26, and a first terminal of a capacitor C23, a second terminal of the resistor R24 is respectively connected to a first terminal of a capacitor C22 and an output terminal of the interface J8, a ground terminal of the interface J8 is connected to a power ground, and a second terminal of the capacitor C22, a second terminal of the capacitor C23, and a second terminal of the resistor R26 are respectively connected to the power ground.

10. The distributed intelligent adaptive power module according to claim 2, further comprising a fan pulse number setting module on the controller, wherein the fan pulse number setting module comprises: data terminal PG0 of processor U1 is connected to the first resistor first terminal of resistor group RN7 and the first switch first terminal of switch group SW1, data terminal PG1 of processor U1 is connected to the second resistor first terminal of resistor group RN7 and the second switch first terminal of switch group SW1, data terminal PE3/TIM1_ BKIN of processor U1 is connected to the third resistor first terminal of resistor group RN7 and the third switch first terminal of switch group SW1, data terminal PE 6327 (HS)/CLK _ CCO of processor U1 is connected to the fourth resistor first terminal of resistor group RN7 and the fourth switch first terminal of switch group SW1, data terminal PE1(T)/I2 1_ SCL of processor U1 is connected to the third resistor first terminal of resistor group RN1 and the fifth switch first terminal of switch group SW1, and data terminal PE1(T)/I2 _ 1_ SCL of processor U1 is connected to the first terminal of resistor group RN1 and the first terminal of switch group SW1, respectively SDA 1 are connected to the fourth switch group SW 1;

the first switch second terminal of the switch group SW1, the second switch second terminal of the switch group SW1, the third switch second terminal of the switch group SW1, the fourth switch second terminal of the switch group SW1, the fifth switch second terminal of the switch group SW1 and the sixth switch second terminal of the switch group SW1 are respectively connected to the power ground.