CN212572585U

CN212572585U - Industrial dual-serial-port Ethernet DTU system

Info

Publication number: CN212572585U
Application number: CN202021955323.3U
Authority: CN
Inventors: 黄海; 文勇
Original assignee: Chengdu Bogao Intelligent New Energy Technology Co ltd
Current assignee: Sichuan Zhiyuan Nengcheng Power Sales Co.,Ltd.
Priority date: 2020-09-09
Filing date: 2020-09-09
Publication date: 2021-02-19
Anticipated expiration: 2030-09-09

Abstract

The utility model discloses an industrial double serial port Ethernet DTU system, which is provided with a main controller circuit, a power supply system, a 232 interface, a 485 interface, an encryption chip circuit, a FLASH circuit and an Ethernet circuit, wherein the main controller circuit is respectively connected with the power supply system, the 232 interface, the 485 interface, the encryption chip circuit, the FLASH circuit and the Ethernet circuit; the interface support device supports two interfaces of 232 and 485, the two interfaces are completely independent on application and can be respectively accessed into a public network, the problem that the interface of the traditional Ethernet DTU is single is solved, and the interface can be independently networked, namely the traditional 232 Ethernet DTU and the 485 Ethernet DTU are integrated.

Description

Industrial dual-serial-port Ethernet DTU system

Technical Field

The utility model belongs to the technical field of the internet of things technique and specifically relates to two serial ports ethernet DTU systems of industry.

Background

In the internet of things era of everything interconnection, cloud is a crucial link of everything interconnection in data just meeting the wave of new capital construction proposed by the country. Ethernet is the most stable way of accessing public data networks, and is a necessary feature for industrial fields, and only ethernet is supported in more industrial fields, so ethernet is very important in industrial communication. On the other hand, at the device side, the common industrial interfaces are 232 interface and 485 interface, and if the data of the device is to be transmitted to the public network, an intermediate data conversion device, namely an ethernet data transmission device, is needed.

The conventional ethernet DTU has the following disadvantages:

1. the conventional ethernet DTU has a single interface, and in an industrial field, a common bus has 232 and 485 interfaces, but the conventional ethernet DTU usually supports only one interface, so in the field, a user has to purchase the ethernet DTUs with two different interfaces, otherwise, a conversion head needs to be purchased, and the use is troublesome.

2. In a traditional ethernet DTU, the DTU is only responsible for forwarding data, that is, serial port data is collected and forwarded to the ethernet, but neglects the support of some specific application scenarios, which results in more time and labor consumption when a user uses the ethernet DTU.

3. The traditional Ethernet DTU does not protect data, the data is very dangerous if not protected, if the data transmitted by the field equipment is intercepted, the data can be used by other people, and even the operation of the field equipment can be controlled maliciously.

4. The conventional Ethernet DTU does not have a data storage function, data only flows and is not stored, so that important data is lost, and the system can not play the role seriously or the data analysis is inaccurate.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a design two serial ports ethernet DTU systems of industry, support two kinds of interfaces 232 and 485, two kinds of interfaces are completely independent above using, can insert the public network respectively, have solved the single problem of interface of traditional ethernet DTU to can independently network, be equivalent to integrated a traditional 232 ethernet DTU and a 485 ethernet DTU.

The utility model discloses a following technical scheme realizes: the industrial dual-serial-port Ethernet DTU system and the method are provided with a main controller circuit, a power supply system, a 232 interface, a 485 interface, an encryption chip circuit, a FLASH circuit and an Ethernet circuit, wherein the main controller circuit is respectively connected with the power supply system, the 232 interface, the 485 interface, the encryption chip circuit, the FLASH circuit and the Ethernet circuit.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: and the main controller circuit is also connected with a watchdog circuit. The watchdog circuit comprises a chip U2 and a chip U2

The legs are connected by a resistor R7

Of pins, chip U2

The legs are connected by a resistor R8

A pin, a VCC pin of the chip U2 is connected to a 3.3V power supply, a VCC pin of the chip U2 is grounded through a capacitor C9, the VCC pin of the chip U2 is grounded through a resistor R9 and a resistor R12 which are mutually connected in series, the common terminal of the resistor R9 and the resistor R12 is connected with a PFI pin of the chip U2, and the common terminal of the chip U2 is connected with a PFI pin of the chip U2

The pin is connected with the NRST pin of the main control chip U4 through a resistor R10, and the WDI pin of the chip U2 is connected with the PC0 pin of the main control chip U4 through a resistor R11.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: and the main controller circuit is also connected with an LED circuit. The LED circuit comprises a first LED branch consisting of a resistor R46 connected with a light emitting diode D8 in series, a second LED branch consisting of a resistor R47 connected with a light emitting diode D9 in series, a third LED branch consisting of a resistor R48 connected with a light emitting diode D10 in series, a fourth LED branch consisting of a resistor R49 connected with a light emitting diode D11 in series, a fifth LED branch consisting of a resistor R50 connected with a light emitting diode D12 in series, and a sixth LED branch consisting of a resistor R51 connected with a light emitting diode D13 in series, the first LED branch is connected between a 3.3V power supply and the ground, the second LED branch is connected between the 3.3V power supply and a PB6 pin of a main control chip U4, the third LED branch is connected between the 3.3V power supply and a PB7 pin of a main control chip U4, the fourth LED branch is connected between the 3.3V power supply and a PC13 pin of the main control chip U4, the fifth LED branch is connected between the 3.3V power supply and a PC14-OSC32_ IN pin of the main control chip U4, and the sixth LED branch is connected between the 3.3V power supply and a PC15-OSC32_ OUT pin of the main control chip U4.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: the main controller circuit is provided with a main control chip U4, a crystal oscillator circuit and a reset circuit, wherein the crystal oscillator circuit is connected between a PDO-OSC _ IN pin and a PDO-OSC _ OUT pin of the main control chip U4, the reset circuit is arranged on an NRST pin of the main control chip U4, the encryption chip circuit is connected to a PA11 pin, a PA10 pin and a PA15 pin of the main control chip U4, and the FLASH circuit is connected to a PB4 pin, a PB3 pin and a PC12 pin of the main control chip U4; the VBAT pin of the main control chip U4 is grounded through a capacitor C18 and a capacitor C19 which are connected in parallel, and 3.3V voltage is connected to the VBAT pin; the VDDA pin of the main control chip U4 is connected with the VSSA pin of the main control chip U4 through a capacitor C21 and a capacitor C22 which are connected in parallel, the VDDA pin is connected with 3.3V voltage, and the VSSA pin is grounded; the PB2 pin of the main control chip U4 is grounded through a resistor R27, a capacitor C27 is connected between the VDD _1 pin and the VSS _1 pin of the main control chip U4, the VDD _1 pin is connected with 3.3V voltage, and the VSS _1 pin is grounded; a capacitor C20 is connected between a VDD _2 pin and a VSS _2 pin of the main control chip U4, the VDD _2 pin is connected with 3.3V voltage, and the VSS _2 pin is grounded; a capacitor C15 is connected between a VDD _3 pin and a VSS _3 pin of the main control chip U4, the VDD _3 pin is connected with 3.3V voltage, the VSS _3 pin is grounded, and a resistor R15 is connected between the VSS _3 pin and a BOOT0 pin of the main control chip U4.

The 232 interface comprises an interface chip U, a capacitor C is connected between a VCC pin and a GND pin of the interface chip U, the VCC pin of the interface chip U is connected with a 3.3V power supply, a capacitor C is connected between a C + pin and a C-pin of the interface chip U, a V + pin of the interface chip U is grounded through the capacitor C, the capacitor C is connected between the C + pin and the C-pin of the interface chip U, a V-pin of the interface chip U is grounded through the capacitor C, a T2 pin of the interface chip U is connected with a PC pin of a main control chip U through a resistor R, an R2OUT pin of the interface chip U is connected with the PC pin of the main control chip U through a resistor R, the interface chip U is also connected with a DB female head JP, a T2OUT pin of the 232 interface is connected with a2 pin of the DB female head JP, an R2 pin of the 232 interface is connected with a3 pin of the DB female head JP, and 5 pin, 10 pin and 11 pins of;

the 485 interface comprises a chip U8 and a chip U9, the 485 interface is also connected with a 5.08 terminal P2, a pin A of the chip U8 is connected with a pin D of the chip U9, a pin GND of the chip U8 is grounded, and a pin Y of the chip U8 is connected with a pin Y of the chip U9

A VCC pin of the chip U8 is connected to a 3.3V power supply; the 3.3V power supply is connected to the R pin of the U9 chip through a resistor R37 and connected to the U9 chip through a resistor R38

The pin and the DE pin are connected into the pin A of the chip U9 through a resistor R45, and are connected into the pin B of the chip U9 through a capacitor C39 and a resistor R39 which are connected in series; a 3.3V power supply is connected to a VCC pin of a chip U9, a common connection end of a capacitor C39 and a resistor R39 is grounded, a resistor R41 is connected between an A pin and a B pin of the chip U9, a DE pin of the chip U9 is grounded through a capacitor C40, a TVS tube D5 is connected between the A pin and the B pin of a chip U9, a TVS tube D7 is connected between the A pin and the ground of a chip U9, a TVS tube D6 is connected between the B pin of the chip U9 and the ground, the A pin of a chip U9 is connected with a2 pin of a 5.08 terminal P2 through a PTC resistor R43 and a resistor R44 which are connected in series, the B pin of the chip U9 is connected with a1 pin of a 5.08 terminal P2 through a resistor R35 and a PTC resistor R36 which are connected in series, a3 pin of a 5.08 terminal P2 is grounded, and a 4 pin of a 5.08 terminal P686; the R pin of the chip U9 is connected with the PA10 pin of the main control chip U4 through a resistor R40, and the D pin of the chip U9 is connected with the resistorR42 is connected with the PA9 pin of the main control chip U4.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: the Ethernet circuit is provided with a PHY circuit and a network port, the network port is connected with the PHY circuit, the PHY circuit is connected with a main controller circuit, the PHY circuit comprises a PHY interface chip U3 and a PHY interface chip peripheral circuit, the network port comprises an interface J2 and an interface J2 peripheral circuit, an interface J2 is connected with a PHY interface chip U3, a PHY interface chip U3 is connected with the main controller circuit, an X3 pin, a COL/RMII pin, a TXEN pin, a TXD3 pin, a TXDD 3 pin, a TXCLK/50M _ CLKI pin, a RXCCLK/50M _ CLKO pin, a RXDD PB 72 pin, a RXDD 3 pin, a RXDDV pin, a CRS/PDV/HEN pin, a CRS/LEOD pin, a RXER INTR _32, a MDPB PB pin, a PB 72 pin, a MDPC pin, a PC pin, a PMD 3 pin, a PC pin 3 pin, a PC pin, a pin 3 pin, a pin, PA0-WAKEUP pin, PB10 pin, PC1 pin, PA2 pin; the RD-pin, the RD + pin, the TD-pin, the TD + pin and the YELLOW LED + pin of the interface J2 are respectively connected with the MDI _ RN pin, the MDI _ RP pin, the MDI _ TN pin, the MDI _ TP pin and the LED3/PHY _ AD3 pin of the PHY interface chip U3, and the GREEN LED-pin of the interface J2 is connected with the LED0/PHY _ AD0 pin of the PHY interface chip U3 through a resistor R30.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: the PHY interface chip peripheral circuit comprises a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R26, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C16, a capacitor C25, a capacitor C26, a COL/RMII pin bias circuit of the PHY interface chip U20 formed by the resistor R20 and the resistor R20, a CRS/LEDMOD pin configuration circuit of the PHY interface chip U20 formed by the resistor R20 and the resistor R20, a TTER/SE pin of the PHY interface chip U20 is connected with a 3.3V power supply through the resistor R20, a REGOUT pin of the PHY interface chip U20 is connected with the capacitor C20 and the capacitor C20 in parallel with the PHY interface chip, a resistor R20, a resistor, a capacitor, a resistor, a capacitor, the common terminal of the resistor R13 and the capacitor C16 is connected with a RESET _ N pin of the PHY interface chip U3, a TEST _ ON pin of the PHY interface chip U3 is connected with a 3.3V power supply through a resistor R16, an MDIO pin of the PHY interface chip U3 is connected with a 3.3V power supply through a resistor R17, an RXDV/CRS _ DV/FX _ HEN pin of the PHY interface chip U3 is grounded through a resistor R19, the 3.3V power supply is filtered through a capacitor C25 and a capacitor C26 which are connected in parallel with each other and then connected with a VDD _ IO pin of the PHY interface chip U3, an LED0/PHY _ AD0 pin and a VDD _ IO pin of the PHY interface chip U638 are grounded through a resistor 686R 8, and the resistor R26 is respectively connected with the LED0/PHY _ AD0 pin and the VDD _ IO pin of.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: the interface J2 peripheral circuit comprises a capacitor C29, a capacitor C30, a capacitor C32, a capacitor C33 and a resistor R31, two CT pins of the interface J2 are grounded through the capacitor C29 and the capacitor C30 respectively, a CHS GND pin of the interface J2 is grounded through the capacitor C32 and a capacitor C33 node which are connected in parallel, a YELLOW LED-pin of the interface J2 is grounded through the resistor R31, and a GREEN LED + pin of the interface J2 is connected with a 3.3V power supply.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: the power supply system comprises a PTC resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, an inductor L1, a power supply chip U1 and a power supply terminal J1, wherein one end of the power supply terminal J1 is connected with an IN pin of the power supply chip U1 through the PTC resistor R1 and the diode D1 which are connected IN series with each other, the diode D1, the capacitor C1 and the capacitor C1 are connected IN parallel between the IN pin and the GND pin of the power supply chip U1, the resistor R1 is connected with the IN pin and the EN pin of the power supply chip U1, the resistor R1 is connected IN parallel with the FB pin of the power supply chip U1, the resistor FB pin and the GND of the power supply chip U1, the resistor FB pin, the resistor R1 are connected IN series with the resistor FB pin of the power supply, the diode D4 is respectively connected with the SW pin and the GND pin of the power chip U1, the capacitor C4 is respectively connected with the SW pin and the BST pin of the power chip U1, the inductor L1 and the diode D1 which are mutually connected in series are connected with the SW pin and the BST pin of the power chip U1, the capacitor C1, the capacitor C2 and the capacitor C3 which are mutually connected in parallel form the output of a power system, the capacitor C1, the capacitor C2 and the capacitor C3 which are mutually connected in parallel are respectively connected with the common end of the inductor L1 and the diode D1 and the GND pin of the power chip U1, and the common end of the power terminal J1 is connected with the GND pin of the power chip U1.

Further for better realizing the utility model discloses, adopt the following mode of setting very much: the encryption chip circuit comprises an encryption chip U5, a VCC pin of an encryption chip U5 is connected to a 3.3V power supply, a capacitor C23 is connected between a VCC pin and a GND pin of the encryption chip U5, and an IO pin, a CLK pin and a RST pin of the encryption chip U5 are respectively connected to a PA11 pin, a PA10 pin and a PA15 pin of a main control chip U4;

the FLASH circuit comprises a FLASH chip U6 and a FLASH chip U6

The pin is grounded through a resistor R29, and the pin of the FLASH chip U6

The pin is grounded through a resistor R32, the GND pin of the FLASH chip U6 and the VCC pin of the FLASH chip U6 are connected to a 3.3V power supply, a capacitor C31 is connected between the VCC pin of the FLASH chip U6 and the ground, and the 3.3V power supply is connected to the FLASH chip U6 through a resistor R28

And a DO pin, a DI pin and a CLK pin of the FLASH chip U6 are respectively connected with a PB4 pin, a PC12 pin and a PB3 pin of the main control chip U4.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

the utility model discloses support two kinds of interfaces 232 and 485, two kinds of interfaces are completely independent on using, can insert the public network respectively, and 232 interfaces adopt the DB9 interface that industrial field used commonly, and the user's of being convenient for use, 485 interfaces adopt binding post, and convenience of customers inserts more 485 equipment. The problem that the interface of the traditional Ethernet DTU is single is solved, and the traditional Ethernet DTU can be independently networked, namely the traditional 232 Ethernet DTU and the 485 Ethernet DTU are integrated.

The utility model discloses to the industrial field, done more functions of easy-to-use, support modbus gateway, equipment can initiatively send modbus data frame, even the user does not understand the modbus agreement and also can easily use; the method supports a networked cloud platform, so that a user does not need to care about the transmission protocols such as mqtt and the like, and can transmit data to the platform for use only by simple configuration; support modbus protocol conversion, support register packets, and the like. The problem that a user is inconvenient to use an Ethernet DTU is solved.

The utility model strictly protects data, users can select an encryption mode and configure a secret key at the same time, thereby preventing the data from being stolen; the system is prevented from being damaged, the encryption chip is arranged, data is prevented from being stolen from the source, meanwhile, the safety of the system is guaranteed, and the system is not afraid of being used as pirate by other people.

The utility model discloses in, the user can dispose the data threshold value, possesses data monitoring analysis function, when data appear unusually, can with data storage to the internal memory, if the network state is unusual, can wait to go out data transfer when the network normally works to ensure the reliability of data.

The utility model discloses can be applied to electric power thing networking direction, it can be used to real-time supervision electric power data, owing to support the reason of MODBUS gateway, so use very conveniently at electric power direction, gather the real-time cloud server that reaches after the data, supply the cloud platform to do data analysis.

The utility model discloses can be applied to agricultural thing networking direction, it can be used to real-time all kinds of sensor data of forwardding to the cloud platform, owing to support serial ports heartbeat package, so can the data of initiative acquisition sensor, perhaps directly forwardding the data of sensor to the cloud platform, when the order is issued from the platform, the utility model discloses can forward the controller, for example control irrigation, fertilization and so on.

The utility model discloses can be applied to building control direction, can be used to carry out real-time data collection to the water pipe at key position, electric wire etc. and forward. Because the environment of a building is complex and the traffic volume is large, it is very suitable to use ethernet as a medium for data interaction.

The utility model discloses can be applied to wisdom water supply direction, can be used for retransmitting the cloud platform with water flow sensor's data is real-time, because water supply system generally all in very complicated outdoor environment, so use the ethernet to come as data transmission can be more stable.

Drawings

Fig. 1 is a block diagram of the present invention.

Fig. 2 is a connection diagram of the main controller circuit, the encryption chip circuit, the FLASH circuit, the crystal oscillator circuit, the reset circuit diagram and the P1 according to the present invention.

Fig. 3 is a circuit diagram of the power supply system of the present invention.

Fig. 4 is a circuit diagram of the watchdog of the present invention.

Fig. 5 is a 232 interface circuit diagram according to the present invention.

Fig. 6 is a 485 interface circuit diagram according to the present invention.

Fig. 7 is a diagram of the PHY circuit and the network interface according to the present invention.

Fig. 8 is a circuit diagram of the LED of the present invention.

Detailed Description

The present invention will be described in further detail with reference to examples, but the present invention is not limited thereto.

To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention are combined to clearly and completely describe the technical solutions of the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention.

In the description of the present invention, it is to be understood that the terms and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience of description and simplified description, and do not indicate or imply that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrated. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

It is worth noting that: in the present application, when it is necessary to apply the known technology or the conventional technology in the field, the applicant may have the case that the known technology or/and the conventional technology is not specifically described in the text, but the technical means is not specifically disclosed in the text, and the present application is considered to be not in compliance with the twenty-sixth clause of the patent law.

Example 1:

as shown in fig. 1 to 8, the industrial dual-serial-port ethernet DTU system is provided with a main controller circuit, a power supply system, a 232 interface, a 485 interface, an encryption chip circuit, a FLASH circuit, and an ethernet circuit, wherein the main controller circuit is respectively connected with the power supply system, the 232 interface, the 485 interface, the encryption chip circuit, the FLASH circuit, and the ethernet circuit; the main controller circuit is also connected with a watchdog circuit; and the main controller circuit is also connected with an LED circuit.

As an optimized setting scheme, the industrial dual-serial-port Ethernet DTU system comprises a main controller circuit, a 232 interface, a 485 interface, a FLASH circuit, a power supply system, an encryption chip circuit, a key, a PHY circuit, a network port and an LED circuit, wherein the 232 interface and the 485 interface are respectively realized by using a 232 conversion chip and a 485 conversion chip and are respectively hung on two independent serial ports to realize a dual-channel Ethernet DTU. The Ethernet interface part (PHY circuit and network port) is realized by using the built-in MAC of the MCU and the externally-hung PHY chip, and has the advantages of high speed and good controllability. And the high-performance industrial double-serial-port server is completed by matching with external watchdog circuits, FLASH circuits, encryption chip circuits and other functional units. Data can enter a DTU system through a 232 interface or a 485 interface, set partial data is backed up through data analysis and processing inside the MCU, effective data is encrypted, the data is finally sent out from an Ethernet interface and sent to an external network, the data flow direction is bidirectional, and if the data enters the DTU from the Ethernet, the data can be sent out from the 232 interface or the 485 interface.

Example 2:

this embodiment is further optimized on the basis of the above-mentioned embodiment, and the same parts as the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: what is needed isThe watchdog circuit comprises a chip U2 and a chip U2

The legs are connected by a resistor R7

Of pins, chip U2

The legs are connected by a resistor R8

The pin is connected with the NRST pin of the main control chip U4 through a resistor R10, the WDI pin of the chip U2 is connected with the PC0 pin of the main control chip U4 through a resistor R11, and SP706TEN-L/TR is preferably adopted as the chip U2.

Example 3:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the LED circuit comprises a first LED branch consisting of a resistor R46 connected IN series with a light emitting diode D8, a second LED branch consisting of a resistor R47 connected IN series with a light emitting diode D9, a third LED branch consisting of a resistor R48 connected IN series with a light emitting diode D10, a fourth LED branch consisting of a resistor R49 connected IN series with a light emitting diode D11, a fifth LED branch consisting of a resistor R50 connected IN series with a light emitting diode D12, and a sixth LED branch consisting of a resistor R51 connected IN series with a light emitting diode D13, the first LED branch is connected between a 3.3V power supply and ground, the second LED branch is connected between the 3.3V power supply and a PB6 pin of a main control chip U4, the third LED branch is connected between the 3.3V power supply and a PB7 pin of a main control chip U4, the fourth LED branch is connected between the 3.3V power supply and a pin 13 pin of the main control chip U4, the fifth PC branch is connected between the 3.3V power supply and a PC branch 14-IN 2 pin of a main control chip U4, and the sixth LED branch are connected between the main control chip OUT 15, preferably, all resistors in the LED circuit are resistors of the same type, all light emitting diodes are LED lamps of the same type, the anode of each LED lamp is connected with the corresponding resistor, and the other end of each resistor is connected with a 3.3V power supply.

Example 4:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the main controller circuit is provided with a main control chip U4, a crystal oscillator circuit and a reset circuit, wherein the crystal oscillator circuit is connected between a PDO-OSC _ IN pin and a PDO-OSC _ OUT pin of the main control chip U4, the reset circuit is arranged on an NRST pin of the main control chip U4, the encryption chip circuit is connected to a PA11 pin, a PA10 pin and a PA15 pin of the main control chip U4, and the FLASH circuit is connected to a PB4 pin, a PB3 pin and a PC12 pin of the main control chip U4; the VBAT pin of the main control chip U4 is grounded through a capacitor C18 and a capacitor C19 which are connected in parallel, and 3.3V voltage is connected to the VBAT pin; the VDDA pin of the main control chip U4 is connected with the VSSA pin of the main control chip U4 through a capacitor C21 and a capacitor C22 which are connected in parallel, the VDDA pin is connected with 3.3V voltage, and the VSSA pin is grounded; the PB2 pin of the main control chip U4 is grounded through a resistor R27, a capacitor C27 is connected between the VDD _1 pin and the VSS _1 pin of the main control chip U4, the VDD _1 pin is connected with 3.3V voltage, and the VSS _1 pin is grounded; a capacitor C20 is connected between a VDD _2 pin and a VSS _2 pin of the main control chip U4, the VDD _2 pin is connected with 3.3V voltage, and the VSS _2 pin is grounded; a capacitor C15 is connected between a VDD _3 pin and a VSS _3 pin of the main control chip U4, the VDD _3 pin is connected with 3.3V voltage, the VSS _3 pin is grounded, and a resistor R15 is connected between the VSS _3 pin and a BOOT0 pin of the main control chip U4; the crystal oscillator circuit comprises a crystal oscillator Y1, a capacitor C17 is connected between a pin 1 and a pin 2 of the crystal oscillator Y1, the pin 1 of the crystal oscillator Y1 is connected with a PD0-OSC _ IN pin of a main control chip U4, the pin 2 of the crystal oscillator Y1 is grounded, a capacitor C14 is connected between a pin 3 and a pin 4 of the crystal oscillator Y1, the pin 3 of the crystal oscillator Y1 is connected with a PD1-OSC _ OUT pin of the main control chip U4, and the pin 4 of the crystal oscillator Y1 is grounded. The preferred main control chip U4 adopts STM32F107RBT6, and crystal oscillator Y1 is XTAL; the main control chip U4 is also connected with a terminal P1, a pin 3 and a pin 1 of the terminal P1 are respectively connected with a pin PA12 and a pin PA14 of the main control chip U4, a pin 4 of the terminal P1 is connected with a 3.3V power supply, and a pin 2 of the terminal P1 is grounded;

example 5:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the Ethernet circuit is provided with a PHY circuit and a network port, the network port is connected with the PHY circuit, the PHY circuit is connected with a main controller circuit, the PHY circuit comprises a PHY interface chip U3 and a PHY interface chip peripheral circuit, the network port comprises an interface J2 and an interface J2 peripheral circuit, an interface J2 is connected with a PHY interface chip U3, a PHY interface chip U3 is connected with the main controller circuit, an X3 pin, a COL/RMII pin, a TXEN pin, a TXD3 pin, a TXDD 3 pin, a TXCLK/50M _ CLKI pin, a RXCCLK/50M _ CLKO pin, a RXDD PB 72 pin, a RXDD 3 pin, a RXDDV pin, a CRS/PDV/HEN pin, a CRS/LEOD pin, a RXER INTR _32, a MDPB PB pin, a PB 72 pin, a MDPC pin, a PC pin, a PMD 3 pin, a PC pin 3 pin, a PC pin, a pin 3 pin, a pin, PA0-WAKEUP pin, PB10 pin, PC1 pin, PA2 pin; the RD-pin, the RD + pin, the TD-pin, the TD + pin and the YELLOW LED + pin of the interface J2 are respectively connected with the MDI _ RN pin, the MDI _ RP pin, the MDI _ TN pin, the MDI _ TP pin and the LED3/PHY _ AD3 pin of the PHY interface chip U3, and the GREEN LED-pin of the interface J2 is connected with the LED0/PHY _ AD0 pin of the PHY interface chip U3 through a resistor R30. Preferably, the PHY interface chip U3 uses IP101GRI, and the interface J2 uses HR 913550A.

Example 6:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the PHY interface chip peripheral circuit comprises a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R26, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C16, a capacitor C25, a capacitor C26, a COL/RMII pin bias circuit of the PHY interface chip U20 formed by the resistor R20 and the resistor R20, a CRS/LEDMOD pin configuration circuit of the PHY interface chip U20 formed by the resistor R20 and the resistor R20, a TTER/SE pin of the PHY interface chip U20 is connected with a 3.3V power supply through the resistor R20, a REGOUT pin of the PHY interface chip U20 is connected with the capacitor C20 and the capacitor C20 in parallel with the PHY interface chip, a resistor R20, a resistor, a capacitor, a resistor, a capacitor, the common terminal of the resistor R13 and the capacitor C16 is connected with a RESET _ N pin of the PHY interface chip U3, a TEST _ ON pin of the PHY interface chip U3 is connected with a 3.3V power supply through a resistor R16, an MDIO pin of the PHY interface chip U3 is connected with a 3.3V power supply through a resistor R17, an RXDV/CRS _ DV/FX _ HEN pin of the PHY interface chip U3 is grounded through a resistor R19, the 3.3V power supply is filtered through a capacitor C25 and a capacitor C26 which are connected in parallel with each other and then connected with a VDD _ IO pin of the PHY interface chip U3, an LED0/PHY _ AD0 pin and a VDD _ IO pin of the PHY interface chip U638 are grounded through a resistor 686R 8, and the resistor R26 is respectively connected with the LED0/PHY _ AD0 pin and the VDD _ IO pin of.

Example 7:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the interface J2 peripheral circuit comprises a capacitor C29, a capacitor C30, a capacitor C32, a capacitor C33 and a resistor R31, two CT pins of the interface J2 are grounded through the capacitor C29 and the capacitor C30 respectively, a CHS GND pin of the interface J2 is grounded through the capacitor C32 and a capacitor C33 node which are connected in parallel, a YELLOW LED-pin of the interface J2 is grounded through the resistor R31, and a GREEN LED + pin of the interface J2 is connected with a 3.3V power supply.

Example 8:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the 232 interface comprises an interface chip U, a capacitor C is connected between a VCC pin and a GND pin of the interface chip U, the VCC pin of the interface chip U is connected with a 3.3V power supply, a capacitor C is connected between a C + pin and a C-pin of the interface chip U, a V + pin of the interface chip U is grounded through the capacitor C, the capacitor C is connected between the C + pin and the C-pin of the interface chip U, a V-pin of the interface chip U is grounded through the capacitor C, a T2 pin of the interface chip U is connected with a PC pin of a main control chip U through a resistor R, an R2OUT pin of the interface chip U is connected with the PC pin of the main control chip U through a resistor R, the interface chip U is also connected with a DB female head JP, a T2OUT pin of the 232 interface is connected with a2 pin of the DB female head JP, an R2 pin of the 232 interface is connected with a3 pin of the DB female head JP, and 5 pin, 10 pin and 11 pins of; preferably, the interface chip U7 adopts MAX 3232;

The pin and the DE pin are connected into the pin A of the chip U9 through a resistor R45, and are connected into the pin B of the chip U9 through a capacitor C39 and a resistor R39 which are connected in series; the 3.3V power supply is connected to a VCC pin of a chip U9, a common connection end of a capacitor C39 and a resistor R39 is grounded, a resistor R41 is connected between an A pin and a B pin of the chip U9, a DE pin of the chip U9 is grounded through a capacitor C40, a TVS tube D5 is connected between the A pin and the B pin of the chip U9, a TVS tube D7 is connected between the A pin of the chip U9 and the ground, a TVS tube D6 is connected between the B pin of the chip U9 and the ground, the A pin of the chip U9 is connected with a2 pin of a 5.08 terminal P2 through a PTC resistor R43 and a resistor R44 which are connected in series, the B pin of the chip U9 is connected with a1 pin of a 5.08 terminal P2 through a resistor R35 and a PTC resistor R36 which are connected in series, and the B pin of the 5.08 terminalThe 3 pin is grounded, and the 4 pin of the 5.08 terminal P2 is connected with VCC; the R pin of the chip U9 is connected with the PA10 pin of the main control chip U4 through a resistor R40, and the D pin of the chip U9 is connected with the PA9 pin of the main control chip U4 through a resistor R42. Preferably, SN74AHC1G04DBVR is adopted for the chip U8, MAX3458 is adopted for the chip U9, SMBS 6.8CA is adopted for the TVS tube D5, the TVS tube D6 and the TVS tube D7, and SCF010-1206R is adopted for the PTC resistor R36 and the PTC resistor R43.

Example 9:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the power supply system comprises a PTC resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, an inductor L1, a power supply chip U1 and a power supply terminal J1, wherein one end of the power supply terminal J1 is connected with an IN pin of the power supply chip U1 through the PTC resistor R1 and the diode D1 which are connected IN series with each other, the diode D1, the capacitor C1 and the capacitor C1 are connected IN parallel between the IN pin and the GND pin of the power supply chip U1, the resistor R1 is connected with the IN pin and the EN pin of the power supply chip U1, the resistor R1 is connected IN parallel with the FB pin of the power supply chip U1, the resistor FB pin and the GND of the power supply chip U1, the resistor FB pin, the resistor R1 are connected IN series with the resistor FB pin of the power supply, the diode D4 is respectively connected with the SW pin and the GND pin of the power chip U1, the capacitor C4 is respectively connected with the SW pin and the BST pin of the power chip U1, the inductor L1 and the diode D1 which are mutually connected in series are connected with the SW pin and the BST pin of the power chip U1, the capacitor C1, the capacitor C2 and the capacitor C3 which are mutually connected in parallel form the output of a power system, the capacitor C1, the capacitor C2 and the capacitor C3 which are mutually connected in parallel are respectively connected with the common end of the inductor L1 and the diode D1 and the GND pin of the power chip U1, and the common end of the power terminal J1 is connected with the GND pin of the power chip U1.

Preferably, the power chip U1 adopts MP2456GJ-Z, the cathode of the diode D4 is connected to the SW pin of the power chip U1, the anode of the diode D1 is connected to the inductor L1, the inductor L1 adopts an inductor with a magnetic core, the PTC resistor R1 adopts SC30-135, the capacitor C1 and the capacitor C2 both adopt electrolytic capacitors, the anode is connected to the 3.3V power supply, the capacitor C5 and the capacitor C6 both adopt electrolytic capacitors, the anode is connected to the IN pin of the power chip U1, the anode of the diode D2 is connected to the PTC resistor R1, the diode D3 adopts SMCJ28, and the cathode of the diode D3 is connected to the IN pin of the power chip U1.

Example 10:

this embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same portions as those in the above-mentioned technical solution will not be described herein again, as shown in fig. 1 to 8, the following setting modes are particularly adopted for further better realizing the present invention: the encryption chip circuit comprises an encryption chip U5, a VCC pin of an encryption chip U5 is connected to a 3.3V power supply, a capacitor C23 is connected between a VCC pin and a GND pin of the encryption chip U5, and an IO pin, a CLK pin and a RST pin of the encryption chip U5 are respectively connected to a PA11 pin, a PA10 pin and a PA15 pin of a main control chip U4; preferably, the encryption chip U5 adopts LKT 2100D;

the FLASH circuit comprises a FLASH chip U6 and a FLASH chip U6

The pin is grounded through a resistor R29, and the pin of the FLASH chip U6

The DO pin, the DI pin and the CLK pin of the FLASH chip U6 are respectively connected to the PB4 pin, the PC12 pin and the PB3 pin of the main control chip U4, and preferably, the FLASH chip U6 uses W25Q128 FVSIG.

Preferably, as shown in table 1, the present invention is a component type selection list in practical implementation.

However, the utility model discloses the lectotype and the parameter setting of various components and parts can be decided according to actual conditions the utility model discloses in do not only prescribe a limit to.

TABLE 1

The utility model discloses a theory of operation does:

the utility model discloses a power supply system's power chip U1 has chooseed the MP2456GJ-Z chip of MPS to come as the conversion chip of power, and it has 500 mA's maximum output current, 1.45 MHz's highest switching frequency, and the encapsulation is very little simultaneously, is fit for overall arrangement in more limited circuit board space, and the input voltage scope is great, can bear at 4.5V to 50V all, so this kind of power is fit for the complex environment at industrial field very much.

The utility model discloses the leading cause that increases outside watchdog circuit is the stability of further reinforcing system, when the system normal operating, can be at the periodic level change of PC0 foot, when the watchdog chip received the level change, just can monitor current system operating condition normally, if the normal operating condition who does not detect the system always, so see how the dog chip draws low RESET foot, let the system RESET, the operation of restarting.

The utility model discloses a net gape adopts the RJ45 interface, is used for connecting the net twine, inserts the ethernet, the utility model discloses the net gape seat of selection is the HR913550A of chinese benevolence, and this kind of seat is inside to have imbedded the network transformer, has reduced the BOM number, supports 1.5 KV's voltage isolation moreover, has two green LED state display lamps of yellow, especially adapted the design theory of this invention.

The main controller circuit of the utility model is the core unit of the system, STM32F107RBT6 of ST is selected, the MCU is selected because if the industrial dual serial port Ethernet DTU system needs to be accessed into the Ethernet, the equipment must contain MAC and PHY, two unit parts, aiming at MAC and PHY all have various combinations, even one MCU contains all three components, but the price is very expensive relatively, the utility model is not suitable for positioning, if MCU of external MAC is selected, the expandability and controllability of the system can be greatly reduced, because the realization of the protocol stack is external, and the communication speed can be greatly reduced, the MCU containing MAC is selected to be the best choice, in the industrial reliable chip, STM32F107RBT6 is a chip with high cost performance, the RAM of 64KB and FLASH of 128KB are supported to the maximum, 4 SPI ports are supported, watchdog, 7 timers, etc., external resources just enough for the present invention.

Because the combination of MCU + MAC is selected when MCU is selected, a PHY chip is externally hung, the PHY chip selects IC + IP101GRI, and is an industrial Ethernet chip, the domestic use amount is very large, the price is lower than that of most PHY chips, and the selection of the PHY chip is more suitable for cost consideration.

The utility model discloses chooseed for use domestic LKT2100D, it is an 8 encryption chips of a section, based on 8051 kernel safety chip platform, embedded LKCOS intelligence operating system who brave core ann company independently researched and developed. The method has the safety characteristics of detection prevention, software and hardware attack resistance and the like. The files in the chip are managed in a grading mode, the keys are stored and used in a classifying mode, the use permission can be divided according to the actual requirements of users, in the system, the data of the MCU are protected, all the data of the users are protected, and therefore the pirate system is prevented, and the safety of the data of the users is improved.

The utility model discloses chooseed for use the SPI-FLASH of Huabang (W25Q128FVSIG), first effect is the backup data that is used for saving communication in-process, can read out when needs use backup data. The second function is to store web pages, because the DTU is Ethernet, the browser is supported to access the DTU, and the browser can open the built-in web pages of the DTU so as to do work such as basic configuration.

Usually 232 chips all are the 5V power supply, the utility model discloses choose for use 3.3V's 232 chips, the leading cause is the power of unified system, and lifting system stability when practicing thrift the cost, DB 9's female head is chooseed for use to 232 external interface is for the convenient equipment that inserts standard 232 mouths such as PLC.

The 485 chip also is the 3.3V chip of chooseing for use, and the reason is the same with the chip of 232 mouths for use the principle, chooses for use the terminal interface, mainly is for the convenient more 485 equipment that inserts, and the terminal also can be used as the power supply and use, if need not the adapter power supply, makes things convenient for external power supply, is favorable to industrial field's wiring more and walks the line, and SMB6.8CA has been chooseed for use in the protection of interface for prevent external high pressure such as thunderbolt from burning out inside components and parts.

The LED circuit is mainly used for prompting the running state and the data state of the system, and when the network cable is not connected, all the indicator lamps are fully turned on to prompt that the current state is unavailable and the network cable needs to be inserted; when data are circulated, the data indicator lamp flickers to show that data are being interacted at the moment; when the key is pressed down, the indicator lights are sequentially lightened to prompt a user of the current key function and the like.

Compared with the traditional Ethernet DTU, the utility model discloses mainly be for convenience of customers's use to and solve some data transmission's most fundamental problem. Firstly, the utility model is designed for the industrial field, the working environment can be very harsh, the industrial grade is selected on the selection of components, the long-time stable operation is ensured, compared with the traditional Ethernet DTU, the utility model adds the design of multiple watchdog, and the stability of the product is improved to the greatest extent; secondly, the utility model is provided with two interfaces which are most commonly used in the industrial field, and compared with the traditional single interface, the utility model has more practicability; thirdly, the utility model is equipped with an encryption system, which ensures the safety of user data and system, and compared with the traditional Ethernet DTU, the utility model is safer and more reliable, and further increases the reliability of the system; fourth, be equipped with data analysis function, carry out most basic judgement to user data, if the data appears unusually, then can save data, for traditional ethernet DTU, the utility model discloses not only the transmission of output, moreover can data analysis and storage, the great reliability that has increased data.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention in any form, and all the technical matters of the present invention are within the protection scope of the present invention to any simple modification and equivalent changes made by the above embodiments.

Claims

1. Industry double serial ports ethernet DTU system, its characterized in that: the intelligent encryption device is provided with a main controller circuit, a power supply system, a 232 interface, a 485 interface, an encryption chip circuit, a FLASH circuit and an Ethernet circuit, wherein the main controller circuit is respectively connected with the power supply system, the 232 interface, the 485 interface, the encryption chip circuit, the FLASH circuit and the Ethernet circuit.

2. The industrial dual-serial-port Ethernet DTU system of claim 1, wherein: and the main controller circuit is also connected with a watchdog circuit.

3. The industrial dual-serial-port Ethernet DTU system of claim 1, wherein: and the main controller circuit is also connected with an LED circuit.

4. The industrial dual-serial-port Ethernet DTU system of claim 1, wherein: the main controller circuit is provided with a main control chip U4, a crystal oscillator circuit and a reset circuit, wherein the crystal oscillator circuit is connected between a PDO-OSC _ IN pin and a PDO-OSC _ OUT pin of the main control chip U4, the reset circuit is arranged on an NRST pin of the main control chip U4, the encryption chip circuit is connected to a PA11 pin, a PA10 pin and a PA15 pin of the main control chip U4, and the FLASH circuit is connected to a PB4 pin, a PB3 pin and a PC12 pin of the main control chip U4; the VBAT pin of the main control chip U4 is grounded through a capacitor C18 and a capacitor C19 which are connected in parallel, and 3.3V voltage is connected to the VBAT pin; the VDDA pin of the main control chip U4 is connected with the VSSA pin of the main control chip U4 through a capacitor C21 and a capacitor C22 which are connected in parallel, the VDDA pin is connected with 3.3V voltage, and the VSSA pin is grounded; the PB2 pin of the main control chip U4 is grounded through a resistor R27, a capacitor C27 is connected between the VDD _1 pin and the VSS _1 pin of the main control chip U4, the VDD _1 pin is connected with 3.3V voltage, and the VSS _1 pin is grounded; a capacitor C20 is connected between a VDD _2 pin and a VSS _2 pin of the main control chip U4, the VDD _2 pin is connected with 3.3V voltage, and the VSS _2 pin is grounded; a capacitor C15 is connected between a VDD _3 pin and a VSS _3 pin of the main control chip U4, the VDD _3 pin is connected with 3.3V voltage, the VSS _3 pin is grounded, and a resistor R15 is connected between the VSS _3 pin and a BOOT0 pin of the main control chip U4.

5. The industrial dual-serial-port Ethernet DTU system of claim 4, wherein: the Ethernet circuit is provided with a PHY circuit and a network port, the network port is connected with the PHY circuit, the PHY circuit is connected with a main controller circuit, the PHY circuit comprises a PHY interface chip U3 and a PHY interface chip peripheral circuit, the network port comprises an interface J2 and an interface J2 peripheral circuit, an interface J2 is connected with a PHY interface chip U3, a PHY interface chip U3 is connected with the main controller circuit, an X3 pin, a COL/RMII pin, a TXEN pin, a TXD3 pin, a TXDD 3 pin, a TXCLK/50M _ CLKI pin, a RXCCLK/50M _ CLKO pin, a RXDD PB 72 pin, a RXDD 3 pin, a RXDDV pin, a CRS/PDV/HEN pin, a CRS/LEOD pin, a RXER INTR _32, a MDPB PB pin, a PB 72 pin, a MDPC pin, a PC pin, a PMD 3 pin, a PC pin 3 pin, a PC pin, a pin 3 pin, a pin, PA0-WAKEUP pin, PB10 pin, PC1 pin, PA2 pin; the RD-pin, the RD + pin, the TD-pin, the TD + pin and the YELLOW LED + pin of the interface J2 are respectively connected with the MDI _ RN pin, the MDI _ RP pin, the MDI _ TN pin, the MDI _ TP pin and the LED3/PHY _ AD3 pin of the PHY interface chip U3, and the GREEN LED-pin of the interface J2 is connected with the LED0/PHY _ AD0 pin of the PHY interface chip U3 through a resistor R30.

6. The industrial dual-serial-port Ethernet DTU system of claim 5, wherein: the PHY interface chip peripheral circuit comprises a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R26, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C16, a capacitor C25, a capacitor C26, a COL/RMII pin bias circuit of the PHY interface chip U20 formed by the resistor R20 and the resistor R20, a CRS/LEDMOD pin configuration circuit of the PHY interface chip U20 formed by the resistor R20 and the resistor R20, a TTER/SE pin of the PHY interface chip U20 is connected with a 3.3V power supply through the resistor R20, a REGOUT pin of the PHY interface chip U20 is connected with the capacitor C20 and the capacitor C20 in parallel with the PHY interface chip, a resistor R20, a resistor, a capacitor, a resistor, a capacitor, the common terminal of the resistor R13 and the capacitor C16 is connected with a RESET _ N pin of the PHY interface chip U3, a TEST _ ON pin of the PHY interface chip U3 is connected with a 3.3V power supply through a resistor R16, an MDIO pin of the PHY interface chip U3 is connected with a 3.3V power supply through a resistor R17, an RXDV/CRS _ DV/FX _ HEN pin of the PHY interface chip U3 is grounded through a resistor R19, the 3.3V power supply is filtered through a capacitor C25 and a capacitor C26 which are connected in parallel with each other and then connected with a VDD _ IO pin of the PHY interface chip U3, an LED0/PHY _ AD0 pin and a VDD _ IO pin of the PHY interface chip U638 are grounded through a resistor 686R 8, and the resistor R26 is respectively connected with the LED0/PHY _ AD0 pin and the VDD _ IO pin of.

7. The industrial dual-serial-port Ethernet DTU system of claim 5, wherein: the interface J2 peripheral circuit comprises a capacitor C29, a capacitor C30, a capacitor C32, a capacitor C33 and a resistor R31, two CT pins of the interface J2 are grounded through the capacitor C29 and the capacitor C30 respectively, a CHS GND pin of the interface J2 is grounded through the capacitor C32 and a capacitor C33 node which are connected in parallel, a YELLOW LED-pin of the interface J2 is grounded through the resistor R31, and a GREEN LED + pin of the interface J2 is connected with a 3.3V power supply.

8. The industrial dual-serial-port Ethernet DTU system of claim 4, wherein: the 232 interface comprises an interface chip U, a capacitor C is connected between a VCC pin and a GND pin of the interface chip U, the VCC pin of the interface chip U is connected with a 3.3V power supply, a capacitor C is connected between a C + pin and a C-pin of the interface chip U, a V + pin of the interface chip U is grounded through the capacitor C, the capacitor C is connected between the C + pin and the C-pin of the interface chip U, a V-pin of the interface chip U is grounded through the capacitor C, a T2 pin of the interface chip U is connected with a PC pin of a main control chip U through a resistor R, an R2OUT pin of the interface chip U is connected with the PC pin of the main control chip U through a resistor R, the interface chip U is also connected with a DB female head JP, the T2OUT pin of the 232 interface is connected with a2 pin of the DB female head JP, the R2 pin of the 232 interface is connected with a3 pin of the DB female head JP, and 5 pin, 10 pin and 11 pin;

The pin and the DE pin are connected into the pin A of the chip U9 through a resistor R45, and are connected into the pin B of the chip U9 through a capacitor C39 and a resistor R39 which are connected in series; a 3.3V power supply is connected to a VCC pin of a chip U9, a common connection end of a capacitor C39 and a resistor R39 is grounded, a resistor R41 is connected between an A pin and a B pin of the chip U9, a DE pin of the chip U9 is grounded through a capacitor C40, a TVS tube D5 is connected between the A pin and the B pin of a chip U9, a TVS tube D7 is connected between the A pin and the ground of a chip U9, a TVS tube D6 is connected between the B pin of the chip U9 and the ground, the A pin of a chip U9 is connected with a2 pin of a 5.08 terminal P2 through a PTC resistor R43 and a resistor R44 which are connected in series, the B pin of the chip U9 is connected with a1 pin of a 5.08 terminal P2 through a resistor R35 and a PTC resistor R36 which are connected in series, a3 pin of a 5.08 terminal P2 is grounded, and a 4 pin of a 5.08 terminal P686; the R pin of the chip U9 is connected with the PA10 pin of the main control chip U4 through a resistor R40, and the D pin of the chip U9 is connected with the PA9 pin of the main control chip U4 through a resistor R42.

9. The industrial dual-serial-port Ethernet DTU system according to any one of claims 1-7, characterized in that: the power supply system comprises a PTC resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, an inductor L1, a power supply chip U1 and a power supply terminal J1, wherein one end of the power supply terminal J1 is connected with an IN pin of the power supply chip U1 through the PTC resistor R1 and the diode D1 which are connected IN series with each other, the diode D1, the capacitor C1 and the capacitor C1 are connected IN parallel between the IN pin and the GND pin of the power supply chip U1, the resistor R1 is connected with the IN pin and the EN pin of the power supply chip U1, the resistor R1 is connected IN parallel with the FB pin of the power supply chip U1, the resistor FB pin and the GND of the power supply chip U1, the resistor FB pin, the resistor R1 are connected IN series with the resistor FB pin of the power supply, the diode D4 is respectively connected with the SW pin and the GND pin of the power chip U1, the capacitor C4 is respectively connected with the SW pin and the BST pin of the power chip U1, the inductor L1 and the diode D1 which are mutually connected in series are connected with the SW pin and the BST pin of the power chip U1, the capacitor C1, the capacitor C2 and the capacitor C3 which are mutually connected in parallel form the output of a power system, the capacitor C1, the capacitor C2 and the capacitor C3 which are mutually connected in parallel are respectively connected with the common end of the inductor L1 and the diode D1 and the GND pin of the power chip U1, and the common end of the power terminal J1 is connected with the GND pin of the power chip U1.

10. The industrial dual-serial-port Ethernet DTU system according to any one of claims 4-7, wherein: the encryption chip circuit comprises an encryption chip U5, a VCC pin of an encryption chip U5 is connected to a 3.3V power supply, a capacitor C23 is connected between a VCC pin and a GND pin of the encryption chip U5, and an IO pin, a CLK pin and a RST pin of the encryption chip U5 are respectively connected to a PA11 pin, a PA10 pin and a PA15 pin of a main control chip U4;

the FLASH circuit comprises a FLASH chip U6 and a FLASH chip U6

The pin is grounded through a resistor R29, and the pin of the FLASH chip U6

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