CN212572579U

CN212572579U - FPGA-based error code detector

Info

Publication number: CN212572579U
Application number: CN202021440064.0U
Authority: CN
Inventors: 王圣
Original assignee: Beijing Xinrui Chuangtong Electronic Technology Co ltd
Current assignee: Beijing Xinrui Chuangtong Electronic Technology Co ltd
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2021-02-19
Anticipated expiration: 2030-07-21

Abstract

The utility model discloses an error code detector based on FPGA, include: the power supply is electrically connected with the FPGA module to supply power to the FPGA module, and the FPGA module is respectively in communication connection with the nixie tube, the configuration system, the control button, the clock and the LED indicator lamp. In this way, the utility model discloses error code detector based on FPGA is through adopting FPGA to accomplish the design of error code ware, for the method that singlechip and the special chip of error code test combined together, can promote test speed, and the sexual valence relative altitude has extensive market prospect in error code detector's based on FPGA's popularization.

Description

FPGA-based error code detector

Technical Field

The utility model relates to the field of communication, especially, relate to an error code detector based on FPGA.

Background

In a communication system, multiple reasons such as machine faults, signal fading, interference and the like can cause the error code received by a receiving end, even cause system performance deterioration and even communication interruption, and the result can be expressed in the form of the error code.

The code pattern of the sending end of the foreign detector is relatively more, the testing speed is optional, and the foreign detector has a good man-machine interaction interface and good performance indexes, is mainly suitable for large and medium enterprises and testing occasions with relatively high requirements on technical indexes, and is generally not suitable for small enterprises and teaching experiments due to high price, complex operation and difficult maintenance. The domestic products are relatively simple to operate, but the rate of processing signals is generally several Mb/s or hundreds Mb/s, the rate is relatively low, the error rate detectors reaching the giga rate are very few, and the sending code pattern is single. At present, the technology of optical communication access networks is continuously improved, the transmission rate is also continuously improved, and the applications of optical transmission modules are more and more, such as 1.25Gb/s, 2.5Gb/s, and 3.125Gb/s optical modules, the requirements on the performance of communication equipment are also higher and higher, and the detection of the reliability of a communication system is more and more important.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the main technical problem who solves provides an error code detector based on FPGA, through adopting FPGA to accomplish the design of error code ware, for the method that singlechip and the special chip of error code test combined together, can promote test speed, compare with foreign high-end product in addition, more have the advantage of price/performance ratio, have extensive market prospect in FPGA based error code detector's popularization.

In order to solve the technical problem, the utility model provides an error code detector based on FPGA, include: the power supply is electrically connected with the FPGA module to supply power to the FPGA module, and the FPGA module is respectively in communication connection with the nixie tube, the configuration system, the control button, the clock and the LED indicator lamp.

In a preferred embodiment of the present invention, the FPGA module uses an EP1C3T144C8 chip.

The utility model has the advantages that: the utility model discloses error code detector based on FPGA is through adopting FPGA to accomplish the design of error code ware, for the method that singlechip and the special chip of error code test combined together, can promote test speed, compares with high-end product abroad in addition, has the advantage of price/performance ratio more, has extensive market prospect in FPGA based error code detector's popularization.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained without inventive work, wherein:

fig. 1 is a schematic structural diagram of a preferred embodiment of the error detector based on the FPGA of the present invention;

fig. 2 is a schematic diagram of the basic principle of error code testing of a preferred embodiment of the error code detector based on the FPGA of the present invention;

fig. 3 is a schematic diagram of the bit-by-bit comparison process of a preferred embodiment of the error detector based on the FPGA of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely below, and it should be apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1-3, an embodiment of the present invention includes:

an FPGA-based error detector, comprising: the device comprises a power supply, an FPGA module, a nixie tube, a configuration system, a control button, a clock and an LED indicator light.

The power supply is electrically connected with the FPGA module to supply power to the FPGA module, and the FPGA module is respectively in communication connection with the nixie tube, the configuration system, the control button, the clock and the LED indicator lamp.

Preferably, the FPGA module adopts an EP1C3T144C8 chip.

As shown in fig. 2, the system under test includes a modem, a transmission medium, a switching device, etc., and is a generalized channel, and the performance of the whole system can be known by detecting errors. The cause of errors is not only noise interference and intersymbol interference of the lines, but also possibly caused by the transceiver equipment and other parts of the system. The code pattern generator and the error code detector are respectively a sending device and a receiving device of the error code tester, and need to be matched for use in actual use. The function of the code pattern generator is to generate various sequences required by the test, then send the sequences to the tested device, and insert certain error codes into the sending codes while sending the sequences. The test code generated by the transmitting device must be a standard test signal that can replace the data in the actual line well. And the receiving equipment receives the data sent back by the tested system and carries out preprocessing. The error code detector is used for generating local data the same as that of the sending end, receiving the data sent back by the tested system, starting local signals for comparison, comparing the local code group with the receiving code group bit by bit, outputting error code pulse signals, counting the number of error code pulses and forming a corresponding error code rate.

The bit-by-bit alignment process is shown in fig. 3, and the comparison method is to perform bit-by-bit alignment on the symbols. And comparing the received sequence with a local sequence generated by the tester by using an exclusive-OR gate, if the two sequences are the same, outputting 0 by using the exclusive-OR gate, and if the two sequences are different, outputting 1 by using the exclusive-OR gate, and simultaneously recording 1 error code. The design adopts a bit-by-bit comparison mode, received data are firstly stored in a register, then a synchronous signal is extracted through the received data, local data and the received data are controlled to be compared bit by bit, and a corresponding error rate is obtained.

The utility model discloses error code detector's beneficial effect based on FPGA is:

by adopting the FPGA to complete the design of the error code device, compared with a method of combining a single chip microcomputer and a chip special for error code test, the method can improve the test speed, and has the advantage of cost performance compared with foreign high-end products.

The above only is the embodiment of the present invention, not limiting the patent scope of the present invention, all of which utilize the equivalent structure or equivalent flow transformation made by the content of the specification of the present invention, or directly or indirectly applied to other related technical fields, all included in the same way in the patent protection scope of the present invention.

Claims

1. An FPGA-based error detector, comprising: the power supply is electrically connected with the FPGA module to supply power to the FPGA module, and the FPGA module is respectively in communication connection with the nixie tube, the configuration system, the control button, the clock and the LED indicator lamp.

2. The FPGA-based error detector of claim 1, wherein said FPGA module employs an EP1C3T144C8 chip.