CN212569768U

CN212569768U - Data acquisition system based on FPGA

Info

Publication number: CN212569768U
Application number: CN202021440047.7U
Authority: CN
Inventors: 管世蕊
Original assignee: Beijing Xinrui Chuangtong Electronic Technology Co ltd
Current assignee: Beijing Xinrui Chuangtong Electronic Technology Co ltd
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2021-02-19
Anticipated expiration: 2030-07-21

Abstract

The utility model discloses a data acquisition system based on FPGA, include: the device comprises a top layer controller module, an I2C control configuration module, an I2S time sequence interface module, a clock frequency division module, an I2C time sequence interface module, a WM8731 module, an I2S data conversion module, a FIFO cache module and an SRAM controller module, wherein the I2S time sequence interface module and the I2C time sequence interface module are respectively in communication connection with the WM8731 module, and the WM8731 module is respectively in communication connection with the I2S data conversion module and the SRAM controller module. In this way, the utility model discloses data acquisition system based on FPGA is through adopting audio encoding and decoding controller based on FPGA, and the interference killing feature is strong, data transmission is reliable, development cycle is shorter, the debugging is easy, has extensive market prospect in data acquisition system's based on FPGA's popularization.

Description

Data acquisition system based on FPGA

Technical Field

The utility model relates to the field of communication, especially, relate to a data acquisition system based on FPGA.

Background

The data acquisition and control system is closed-loop control for real-time acquisition, test and feedback control of various physical quantities in the production process or scientific experiments, and plays an important role in many fields such as industrial control, military electronic equipment, medical monitoring and the like. Among them, the data acquisition part is particularly important. In recent years, embedded digital audio products are gaining favor from more and more consumers. In a conventional data acquisition system, a single chip or a DSP is usually used as a controller to control the ADC, a memory and other peripheral circuits, so that the acquisition speed and efficiency are reduced.

In the consumer electronics products such as MP3 and mobile phones, the requirements of people for these personal terminals have not been limited to simple speech and simple word processing, the audio processing function has become an indispensable important component, and the high quality sound effect is an important trend in the current development.

SUMMERY OF THE UTILITY MODEL

The utility model provides a technical problem of main solution provides a data acquisition system based on FPGA, through adopting audio frequency coding and decoding controller based on FPGA, the design utilizes hardware description language to program on FPGA and realizes the control to required chip, accomplish the recording playback function, provide control signal to audio frequency coding and decoding chip WM8731 through I2C bus, and realize WM 8731's data transmission through I2S bus, the interference killing feature is strong, data transmission is reliable, the development cycle is shorter, the debugging is easy, be convenient for computer storage and processing, there is extensive market prospect in FPGA-based data acquisition system's popularization.

In order to solve the technical problem, the utility model provides a data acquisition system based on FPGA, include: the system comprises a top layer controller module, an I2C control configuration module, an I2S time sequence interface module, a clock frequency division module, an I2C time sequence interface module, a WM8731 module, an I2S data conversion module, an FIFO cache module and an SRAM controller module, wherein the top layer controller module is respectively in communication connection with the I2C control configuration module, the I2S time sequence interface module and the clock frequency division module, the clock frequency division module is in communication connection with the I2S time sequence interface module, the I2C control configuration module is in communication connection with the I2C time sequence interface module, the I2S time sequence interface module and the I2C time sequence interface module are respectively in communication connection with the WM8731 module, the WM8731 module is respectively in communication connection with the I2S data conversion module and the SRAM controller module, the I2S data conversion module is in communication connection with the FIFO cache module, and the FIFO module is in communication connection with the SRAM controller cache module.

In a preferred embodiment of the present invention, during recording, audio data is inputted from MIC or Line In, and a/D conversion is performed by the WM8731 module, and serial data is outputted from the I2S timing interface module via the FIFO buffer module to the SRAM controller module, thereby storing a voice signal.

In a preferred embodiment of the present invention, during playback, the data in the SRAM controller module is transferred to the WM8731 module by the FIFO buffer module via the I2S data transfer module, and then D/a conversion is performed by the WM8731 module, and output is performed via Line Out.

In a preferred embodiment of the present invention, the SRAM controller module IS an IS61WV1024ALL chip.

The utility model has the advantages that: the utility model discloses data acquisition system based on FPGA is through adopting audio frequency coding and decoding controller based on FPGA, the design utilizes hardware description language programming to realize the control to required chip on FPGA, accomplish recording playback function, provide control signal to audio frequency coding and decoding chip WM8731 through I2C bus, and realize WM 8731's data transmission through I2S bus, the interference killing feature is strong, data transmission is reliable, development cycle is shorter, the debugging is easy, there is extensive market prospect in data acquisition system's based on FPGA popularization.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained without inventive work, wherein:

fig. 1 is a schematic structural diagram of a preferred embodiment of the data acquisition system based on FPGA of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely below, and it should be apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1, an embodiment of the present invention includes:

an FPGA-based data acquisition system comprising: the device comprises a top layer controller module, an I2C control configuration module, an I2S time sequence interface module, a clock frequency division module, an I2C time sequence interface module, a WM8731 module, an I2S data conversion module, a FIFO cache module and an SRAM controller module.

The top layer controller module is respectively in communication connection with the I2C control configuration module, the I2S time sequence interface module and the clock frequency division module, the clock frequency division module is in communication connection with the I2S time sequence interface module, the I2C control configuration module is in communication connection with the I2C time sequence interface module, the I2S time sequence interface module is respectively in communication connection with the I2C time sequence interface module and the WM8731 module, the WM8731 module is respectively in communication connection with the I2S data conversion module and the SRAM controller module, the I2S data conversion module is in communication connection with the FIFO cache module, and the FIFO cache module is in communication connection with the SRAM controller module.

Preferably, during recording, audio data is input from MIC or Line In, a/D conversion is performed by the WM8731 module, and output serial data is transmitted to the SRAM controller module by the I2S timing interface module via the FIFO buffer module to store a voice signal.

Preferably, during playback, data in the SRAM controller module is transmitted to the WM8731 module by the FIFO cache module through the I2S data conversion module, and then is subjected to D/A conversion by the WM8731 module and is output through the Line Out.

Preferably, the SRAM controller module adopts an IS61WV1024ALL chip.

The FPGA has the advantages of high clock frequency of the FPGA, small internal delay, high speed and high efficiency, all control logics are completed by hardware, and meanwhile, the FPGA has very strong hardware description languages and simulation tools, so that the correctness of results is conveniently checked.

The system is an audio coding and decoding chip controller based on FPGA, and is used for controlling a voice chip WM 8731. In the whole system, a standard MIC, a Line-out interface, two switch keys and two button keys are used.

The digital voice integrated circuit is combined with the embedded microprocessor, so that the miniaturization and low power consumption of the system are realized, the product development cost is reduced, the design flexibility is improved, the digital voice integrated circuit has the characteristics of small volume, convenience in expansion and the like, and the digital voice integrated circuit has wide development prospects, such as a computer voice clock, a voice type digital multimeter, a mobile phone telephone charge inquiry system, a queuing machine, a monitoring system voice alarm, a bus station reporter and the like.

The utility model discloses data acquisition system based on FPGA's beneficial effect is:

the audio coding and decoding controller based on the FPGA is adopted, the needed chip is controlled by programming on the FPGA through a hardware description language, the recording and playing functions are completed, a control signal is provided for the audio coding and decoding chip WM8731 through an I2C bus, and data transmission of the WM8731 is realized through an I2S bus, so that the anti-interference capability is strong, the data transmission is reliable, the development period is short, and the debugging is easy.

The above only is the embodiment of the present invention, not limiting the patent scope of the present invention, all of which utilize the equivalent structure or equivalent flow transformation made by the content of the specification of the present invention, or directly or indirectly applied to other related technical fields, all included in the same way in the patent protection scope of the present invention.

Claims

1. An FPGA-based data acquisition system, comprising: the system comprises a top layer controller module, an I2C control configuration module, an I2S time sequence interface module, a clock frequency division module, an I2C time sequence interface module, a WM8731 module, an I2S data conversion module, an FIFO cache module and an SRAM controller module, wherein the top layer controller module is respectively in communication connection with the I2C control configuration module, the I2S time sequence interface module and the clock frequency division module, the clock frequency division module is in communication connection with the I2S time sequence interface module, the I2C control configuration module is in communication connection with the I2C time sequence interface module, the I2S time sequence interface module and the I2C time sequence interface module are respectively in communication connection with the WM8731 module, the WM8731 module is respectively in communication connection with the I2S data conversion module and the SRAM controller module, the I2S data conversion module is in communication connection with the FIFO cache module, and the FIFO module is in communication connection with the SRAM controller cache module.

2. The FPGA-based data acquisition system as claimed in claim 1, wherein during recording, audio data is input from MIC or LineIn, A/D conversion is performed by the WM8731 module, and output serial data is transmitted to the SRAM controller module by the I2S sequential interface module through the FIFO buffer module to store voice signals.

3. The FPGA-based data acquisition system of claim 1, wherein during playback, data in the SRAM controller module is transmitted from the FIFO cache module to the WM8731 module via the I2S data transfer module, then is D/A converted by the WM8731 module, and is output via Line Out.

4. The FPGA-based data collection system of claim 1, wherein said SRAM controller module employs an IS61WV1024ALL chip.