CN212542444U

CN212542444U - Semiconductor structure

Info

Publication number: CN212542444U
Application number: CN202020971128.3U
Authority: CN
Inventors: 张钦福; 林昭维; 朱家仪; 童宇诚; 赖惠先
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-06-01
Filing date: 2020-06-01
Publication date: 2021-02-12
Anticipated expiration: 2030-06-01

Abstract

The utility model discloses a semiconductor structure, which comprises a substrate, there is a fin-shaped structure on the substrate, and shallow trench isolation structure is located in the substrate, wherein shallow trench isolation structure has a ladder form top surface to have first top surface and be higher than the second top surface of first top surface, and a grid structure, stride across the part shallow trench isolation structure and part fin-shaped structure, wherein the grid structure has a ladder form bottom surface.

Description

Semiconductor structure

Technical Field

The present invention relates to a semiconductor structure, and more particularly to a shallow trench isolation structure having a step shape and a gate structure located above the shallow trench isolation structure.

Background

As semiconductor devices are developed toward higher densities, the size of the devices within a unit area is continuously decreasing. Semiconductor components are widely used in the electronics industry due to their small size, versatility and/or low manufacturing cost. The semiconductor device is classified into a semiconductor device that stores logic data, a semiconductor logic device that operates, processes, and the like the logic data, or a hybrid semiconductor device that has both the function of a semiconductor storage device and the function of a semiconductor logic device and/or other semiconductor devices.

In recent years, as Field Effect Transistors (FETs) continue to shrink in size, the development of conventional planar field effect transistor devices has faced the limit of process. To overcome the process limitations, it is becoming a mainstream trend to replace planar transistor devices with non-planar (non-planar) field effect transistor devices, such as Fin field effect transistor (Fin FET) devices. The three-dimensional structure of the finfet device can increase the contact area between the gate and the fin structure, thereby further increasing the control of the gate on the carrier channel region, thereby reducing the Drain Induced Barrier Lowering (DIBL) effect faced by the small-sized device and suppressing the Short Channel Effect (SCE). Furthermore, since the finfet device has a wider channel width for the same gate length, a doubled drain driving current can be obtained. Furthermore, the threshold voltage (threshold voltage) of the transistor element can also be adjusted by adjusting the work function of the gate.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a semiconductor structure, including the substrate, there is a fin-shaped structure on the above-mentioned substrate, and shallow trench isolation structure is located above-mentioned substrate, and wherein above-mentioned shallow trench isolation structure has a ladder form top surface to have first top surface and be higher than the second top surface of above-mentioned first top surface, and a grid structure, stride over above-mentioned shallow trench isolation structure of part and above-mentioned fin-shaped structure of part, wherein above-mentioned grid structure has a ladder form bottom surface.

Optionally, wherein the second top surface is lower than a top surface of the fin structure.

Optionally, the gate structure includes a pad layer, a conductive layer and a mask layer stacked in sequence from bottom to top.

Optionally, the pad layer has a stepped cross-sectional structure, and the stepped cross-sectional structure has three different levels.

Optionally, wherein a bottom surface of the conductive layer is lower than a top surface of the fin structure.

Optionally, the hard mask layer of the gate structure includes a stepped top surface.

Optionally, a lowest bottom surface of the gate structure is flush with the first top surface of the shallow trench isolation structure.

Optionally, the substrate further comprises a second gate structure located on the substrate, wherein the second gate structure is not located above the shallow trench isolation structure.

Optionally, wherein the second gate structure has a flat top surface.

The utility model is characterized in that, the etching parameter when adjusting the preparation shallow trench isolation structure forms the shallow trench isolation structure with echelonment profile structure. The applicant finds that the stepped shallow trench isolation structure has higher structural strength, and a dummy gate structure is easily formed on the boundary of the shallow trench isolation structure and the fin-shaped structure. When the virtual grid structure is formed on the step-shaped top surface subsequently, the fin-shaped structure and the grid structure can be protected, and the quality of the component is improved.

Drawings

The accompanying drawings, which form a part of the specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention without unduly limiting the scope of the invention. In the drawings:

fig. 1-3 are schematic diagrams illustrating steps for forming a semiconductor structure according to a preferred embodiment of the present invention;

fig. 4 is a schematic view of a semiconductor structure according to another preferred embodiment of the present invention.

Wherein the figures include the following reference numerals:

100 substrate

101 fin structure

102 trench

104 insulating layer

105 liner layer

106 shallow trench isolation structure

110 patterned mask

111 silicon oxide layer

112 silicon nitride layer

113 silicon oxide layer

120 virtual grid structure

121 gate dielectric layer

122 gate conductive layer

123 mask layer

124 spacer

130 grid structure

131 gate dielectric layer

132 gate conductive layer

133 mask layer

134 spacer

S1 Top surface

S2 Top surface

S3 Top surface

Detailed Description

Sufficient detail has been disclosed below to enable one skilled in the art to practice it. Further, some object structures and operation flows known to those skilled in the art are not described in detail. Of course, other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the embodiments described herein.

Likewise, the embodiments of the drawings are merely schematic and some details are not drawn to scale completely for clarity of description. Moreover, for the purpose of simplicity and clarity, when various embodiments have similar features, the same reference numbers will be used for similar features.

Referring to fig. 1 to 3, steps for forming a semiconductor structure according to a preferred embodiment of the present invention are schematically illustrated. First, as shown in fig. 1, a substrate 100 is provided. The substrate 100 is a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate. In an embodiment of the bulk silicon process, the fin structure 101 is preferably formed by a sidewall pattern transfer (SIT) technique, which includes forming a plurality of patterned sacrificial layers (not shown) on the substrate 100 through a photolithography and etching process, sequentially performing a deposition process and an etching process to form a spacer (not shown) on the sidewall of each patterned sacrificial layer, subsequently removing the patterned sacrificial layers, and performing an etching process through the spacer covering, so that the spacer pattern is transferred to a patterned mask 110 of a single-layer or multi-layer structure, such as a composite structure composed of a silicon oxide (silicon oxide) layer 111, a silicon nitride (silicon nitride) layer 112, and a silicon oxide layer 113. Thereafter, an etching process is performed to transfer the pattern of the patterned mask 110 to the underlying substrate 100, thereby forming a plurality of trenches 102 and defining the fin structures 101. In another embodiment, a fin cut process (fin cut) may be performed to form the desired fin structure 101, such as fin structures 101 that are parallel to each other.

In another embodiment, the fin structure 101 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 100, and then using an epitaxial process to grow a semiconductor layer (not shown) comprising silicon or silicon germanium (sige) on the substrate 100 exposed outside the patterned mask layer to form the corresponding fin structure. Alternatively, in other embodiments (not shown), such as those including a silicon-on-insulator substrate, patterned mask 110 may be used to etch a semiconductor layer (not shown) of substrate 100, stopping on a bottom oxide layer (not shown) below the semiconductor layer to form the fin structures.

Next, as shown in fig. 2, an insulating material layer (not shown) is formed on the substrate 100 globally, preferably by using a Flow Chemical Vapor Deposition (FCVD) process, followed by a Chemical Mechanical Polishing (CMP) and an etch back process, so as to form an insulating layer 104, such as silicon monoxide, in the trench 102. It is noted that, in the above-mentioned manufacturing process, since the area occupied by the groove 102 is larger on the entire substrate 100, after the insulating layer 104 fills the groove 102, the insulating layer 104 near the central portion of the groove 102 is etched faster through CMP and etch-back, and the insulating layer 104 near the fin-shaped structure 101 in the groove 102 is etched at a slower rate, which tends to result in a structure in which the top surface of the insulating layer 104 at the center of the groove 102 is lower than the top surface of the insulating layer 104 at the periphery. The above phenomenon may also be referred to as a dishing (debossing) phenomenon.

In the preferred embodiment, the insulating layer 104 in the recess 102 is etched by adjusting the process etching parameters to form a Shallow Trench Isolation (STI) structure 106 with a step-shaped top surface as shown in fig. 2. It is noted that the sti structure 106 in this embodiment has two top surfaces with different heights, which are respectively defined as the top surface S1 and the top surface S2, wherein the top surface S1 is lower than the top surface S2, and preferably, the top surface S1 and the top surface S2 are horizontal surfaces. Therefore, the shallow trench isolation structure 106 of the preferred embodiment has a stepped top surface. In addition, the top surface of the fin structure 101 may be defined as the top surface S3, and in the present embodiment, the top surfaces S1 and S2 are both lower than the top surface S3. Therefore, a stepped region having at least three levels (i.e., top surface S1, top surface S2, and top surface S3) with different heights is formed at the edge of the sti 106 near the fin 101.

According to the experimental results of the applicant, the sti structures generated under the dishing phenomenon generally have a circular-arc-shaped recessed top surface, and the etching parameters are deliberately adjusted in the preferred embodiment such that the surface of the sti structure has a step shape, and the angle of each step-shaped planar portion is close to horizontal (i.e. the top surface S1 and the top surface S2 are both substantially parallel to the horizontal plane), while there may be a vertical or inclined side between the two top surfaces S1 and S2. In addition to the above adjustment of the etching parameters, the actual manufacturing method can also be used to perform an etch-back process several times to achieve a shallow trench isolation structure with a step-shaped top surface, which is not described herein again.

It is noted that, in one embodiment, during the cmp and etch back processes, a portion of the patterned mask 110 (e.g., the silicon nitride layer 112 and the silicon oxide layer 113) may be selectively removed according to the structural characteristics of the subsequently formed tri-gate transistor device or dual-gate fin transistor device, but not limited thereto. In other embodiments, patterned mask 110 may be selectively completely retained or completely removed. In another embodiment, a dielectric layer may be further formed on the entire surface of the substrate 100 and the fin structure 101 as a liner layer 105 before the insulating layer 104 is formed. The pad layer 105 has a single-layer or multi-layer structure, and is preferably made of a dielectric material such as silicon oxide or a suitable high dielectric constant material. The liner layer 105 is formed by, for example, an In Situ Steam Generation (ISSG) technique to form a liner layer 105 uniformly distributed on the surface of the fin structure 101 and the trench 102, as shown in fig. 2, but not limited thereto. In other embodiments, the liner layer 105 may alternatively be formed by an Atomic Layer Deposition (ALD) process, or may alternatively comprise other dielectric materials.

Next, as shown in fig. 3, after the patterned mask 110 (silicon oxide layer 111) is completely removed, at least one dummy gate structure 120 crossing the fin structure 101 and a gate structure 130 on the fin structure 101 are formed. In the present embodiment, the process of forming the dummy gate structure 120 may be integrated with commonly used gate processes. For example, a gate process may be performed to sequentially form a gate dielectric material layer (not shown), such as an insulating material including silicon oxide, and a gate layer (not shown) on the fin structure 101, and then pattern the gate layer and the gate dielectric material layer, so as to form a plurality of gate structures 130, including the gate dielectric layer 131, the gate conductive layer 172 and the mask layer 173, on the fin structure 101, as shown in fig. 3. The dummy gate structure 120 includes a gate dielectric layer 121, a gate conductive layer 122, and a mask layer 123. In one embodiment, the gate conductive layer 122 of the dummy gate structure 120 is, for example, a polysilicon gate, but the material is not limited thereto, and may be determined according to the actual requirement. Subsequently,

spacers

124 and 134 surrounding the dummy gate structure 120 and the gate structure 130 may be formed, wherein the

spacers

124 and 134 may be, for example, silicon nitride, silicon oxynitride (silicon oxynitride), silicon carbide nitride (silicon carbide), or the like.

It should be noted that, since the sti structure 106 has a step-shaped top surface (the top surface S1 and the top surface S2), when the dummy gate structure 120 is completed, the dummy gate structure 120 also has a step-shaped structure as viewed in cross section because the dummy gate structure spans the step-shaped region. For example, the dummy gate structure 120 spans the top surface S1, the top surface S2, and the top surface S3, so the dummy gate structure 120 has a stepped bottom surface and a stepped top surface. The detailed view includes a step-shaped gate dielectric layer 121, a step-shaped gate conductive layer 122 and a step-shaped mask layer 123, wherein the cross-sectional structures of the gate dielectric layer 121, the gate conductive layer 122 and the mask layer 123 have three different levels. As shown in fig. 3, the bottom surface of the gate conductive layer 122 (which is flush with the top surface S1) is lower than the top surface of the fin structure 101 (i.e., the top surface S3), and the lowest bottom surface of the dummy gate structure 120 is flush with the top surface S1 of the sti structure 106. The applicants have found that the dummy gate structure 120 having a stepped bottom surface can be stably combined with the stepped top surface of the sti structure 106, thereby enhancing the structural strength of the device in this area and protecting the surrounding fin structure 101 and the gate structure 130 formed above the fin structure 101.

On the other hand, in the preferred embodiment, the gate structure 130 is entirely located above the fin structure 101, but not located on the sti structure 106, and thus does not cover the stepped region. Therefore, the gate structure 130 has a flat bottom surface and a flat top surface.

As shown in fig. 3, the dummy gate structure 120 of the present embodiment has a portion covering the fin structure 101. That is, the dummy gate structure 120 and the spacer 133 are used to cover the etched edge of the fin structure 101, so as to prevent the fin structure 101 from being affected by the subsequent processes, such as the source/drain epitaxial growth process, which may cause structural deformation, current leakage or damage to the overall electrical performance.

The following description will mainly detail differences of the embodiments, and will not repeat the description of the same parts. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate the comparison between the embodiments.

Fig. 4 is a schematic view of a semiconductor structure according to another preferred embodiment of the present invention. As shown in fig. 4, the position of the dummy gate structure 120 can be adjusted, and in the preferred embodiment, the spacer 124 of the dummy gate structure 120 is located above the interface between the insulating layer 104 of the sti structure 106 and the fin structure 101. In the preferred embodiment, the spacer 124 is still located on the fin-shaped structure 101 (the spacer 124 does not cross over the insulating layer 104), however, in other preferred embodiments of the present invention, the spacer 124 may cross over the fin-shaped structure 101 and the insulating layer 104 at the same time, which also falls within the scope of the present invention.

To sum up, the utility model is characterized in that, the etching parameter when adjusting the preparation shallow trench isolation structure forms the shallow trench isolation structure that has echelonment section structure. The applicant finds that the stepped shallow trench isolation structure has higher structural strength, and a dummy gate structure is easily formed on the boundary of the shallow trench isolation structure and the fin-shaped structure. The dummy gate structure 120 is formed on the top surface of the step shape to protect the fin structure and the gate structure, thereby improving the quality of the device.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a substrate having a fin structure thereon;

the shallow trench isolation structure is positioned in the substrate, and has a stepped top surface, a first top surface and a second top surface higher than the first top surface; and

a gate structure spanning a portion of the shallow trench isolation structure and a portion of the fin structure, wherein the gate structure has a stepped bottom surface.

2. The semiconductor structure of claim 1, wherein the second top surface is lower than a top surface of the fin structure.

3. The semiconductor structure of claim 1, wherein the gate structure comprises a liner layer, a conductive layer and a mask layer stacked in sequence from bottom to top.

4. The semiconductor structure of claim 3, wherein the pad layer has a stepped cross-sectional structure as viewed in cross-section, and the stepped cross-sectional structure has three different levels.

5. The semiconductor structure of claim 3, wherein a bottom surface of the conductive layer is lower than a top surface of the fin structure.

6. The semiconductor structure of claim 3, wherein the hard mask layer of the gate structure comprises a stepped top surface.

7. The semiconductor structure of claim 1, wherein a lowest bottom surface of the gate structure is flush with the first top surface of the shallow trench isolation structure.

8. The semiconductor structure of claim 1, further comprising a second gate structure on the substrate, wherein the second gate structure is not located above the shallow trench isolation structure.

9. The semiconductor structure of claim 8, wherein the second gate structure has a planar top surface.

10. The semiconductor structure of claim 1, wherein the gate structure further comprises spacers on both sides of the gate structure.

11. The semiconductor structure of claim 10, wherein the spacer is located on an interface of the shallow trench isolation structure and the fin structure.