CN212518786U

CN212518786U - Filter capacitor discharge circuit and conversion circuit

Info

Publication number: CN212518786U
Application number: CN202021736963.5U
Authority: CN
Inventors: 沈逸伦; 黄于芸
Original assignee: Hong Kong Shangxinchuang Technology Co ltd
Current assignee: Agco Microelectronics Shenzhen Co ltd
Priority date: 2020-08-19
Filing date: 2020-08-19
Publication date: 2021-02-09
Anticipated expiration: 2030-08-19

Abstract

The utility model discloses a filter capacitor discharge circuit and converting circuit, filter capacitor discharge circuit include high-voltage terminal, signal preparation circuit, low pass filter, range detector, timing unit and switch unit. The signal preparation circuit receives a detection signal corresponding to the alternating voltage by the high-voltage end and generates a voltage signal according to the detection signal. The low pass filter provides a filtering signal according to the voltage signal, and the range detector checks whether the voltage distance between the voltage signal and the filtering signal is less than a default value. The timing unit starts timing to generate a timing result when the voltage distance is smaller than a default value, and the switch unit is conducted to enable the filter capacitor to discharge through the switch unit when the timing result exceeds a preset time or preset time.

Description

Filter capacitor discharge circuit and conversion circuit

Technical Field

The present invention relates to a discharge circuit and a conversion circuit, and more particularly to a filter capacitor discharge circuit and a conversion circuit for discharging EMI filter capacitors.

Background

Since the electronic products nowadays pay attention to the quality of the input voltage (i.e. ac voltage) received by the conversion circuit, the front end of the conversion circuit usually employs an emi (electromagnetic interference) filter to reduce the emi. Among other things, EMI filters typically include a capacitor, commonly referred to as a filter capacitor or an X capacitor, coupled to the input of the conversion circuit. When the plug at the input of the converter circuit is removed from the socket and the ac voltage input is interrupted, the voltage across the filter capacitor is not released, so that it may continue to maintain the high voltage. If the high voltage is not consumed by the internal resistance for a long time, the high voltage still continues to be electrified, so that when a user touches the plug of the conversion circuit, the user may be in doubt of electric shock, thereby causing safety risk.

How to design a filter capacitor discharge circuit, a conversion circuit and an operation method for discharging the filter capacitor so as to discharge the filter capacitor when the plug of the conversion circuit is unplugged and the input of an alternating voltage is interrupted, and not to influence the working efficiency of the conversion circuit during operation is a major subject to be researched by the authors of the present application.

SUMMERY OF THE UTILITY MODEL

The utility model provides a filter capacitor discharge circuit, including a high-voltage terminal, a low pass filter, a scope detector, timing unit and switch unit. The high-voltage end is coupled with the filter capacitor of the input end, and the input end receives alternating-current voltage. The signal preparation circuit is coupled to the high-voltage terminal and is used for generating a voltage signal representing the alternating-current voltage. The low-pass filter provides a filtering signal according to the voltage signal. The range detector compares the voltage signal and the filtered signal to check whether the voltage distance between the voltage signal and the filtered signal is less than a predetermined value. When the voltage distance is smaller than the default value, the timing unit starts timing to generate a timing result. When the timing result exceeds the preset times or preset time, the timing unit enables the switch unit to be conducted, and the filter capacitor is discharged through the switch unit.

Wherein, the range detector includes: a range generating circuit for generating an upper limit voltage and a lower limit voltage according to the filtering signal; and a comparison circuit for checking whether the voltage signal falls between the upper limit voltage and the lower limit voltage, and providing an enable signal to the timing unit according to the checking result.

Wherein the range generation circuit includes: an adding unit for adding a first reference voltage to the filtered signal to generate the upper limit voltage; and a subtraction unit for subtracting a second reference voltage from the filtered signal to generate the lower limit voltage.

Wherein, this comparison circuit includes: a first comparing unit for comparing the upper limit voltage with the voltage signal to provide a first comparison signal; a second comparing unit for comparing the lower limit voltage with the voltage signal to provide a second comparison signal; and a logic unit for providing the enable signal according to the first comparison signal and the second comparison signal.

Wherein, the range detector includes: a range generating circuit for generating an upper limit voltage and a lower limit voltage according to the voltage signal; and a comparison circuit for checking whether the filtering signal falls between the upper limit voltage and the lower limit voltage, and providing an enable signal to the timing unit according to the checking result.

Wherein the range generation circuit includes: an adding unit for adding a first reference voltage to the voltage signal to generate the upper limit voltage; and a subtraction unit for subtracting a second reference voltage from the voltage signal to generate the lower limit voltage.

Wherein, this comparison circuit includes: a first comparing unit for comparing the upper limit voltage with the filtering signal to provide a first comparison signal; a second comparison unit for comparing the lower limit voltage with the filtering signal to provide a second comparison signal; and a logic unit for providing the enable signal representing the checking result according to the first comparison signal and the second comparison signal.

The timing unit generates a pulse number according to the counting of a frequency signal, and when the pulse number is greater than or equal to a preset number, the timing unit judges that the timing result exceeds the preset time, so that the switch unit is switched on.

The utility model provides a conversion circuit, include: a filter capacitor, a detection circuit and a filter capacitor discharge circuit. The filter capacitor receives the alternating voltage from the input end, the detection circuit detects the alternating voltage to provide a detection signal, and the filter capacitor discharge circuit receives the detection signal through the high-voltage end. Utility model

The utility model discloses a main purpose and efficiency lie in, use filter capacitor discharge circuit to pull out at converting circuit's plug and when the interrupt alternating voltage input, whether the voltage distance between voltage signal that corresponds alternating voltage and the filter signal that corresponds alternating voltage through the inspection is less than the default and decides whether switch on the switch unit, in order to reach the scheduled time after the interrupt alternating voltage input, release the energy that remains among the filter capacitor, in order to accord with the safety standard, and avoid the efficiency of the risk of personnel's electric shock.

In order to further understand the technology, means and functions of the present invention adopted to achieve the predetermined purpose, please refer to the following detailed description and accompanying drawings of the present invention, which are believed to provide a further and specific understanding of the objects, features and characteristics of the present invention, however, the attached drawings are provided for reference and illustration purposes only and are not intended to limit the present invention.

Drawings

FIG. 1 is a block diagram of a conversion circuit with a filter capacitor discharge circuit according to the present invention;

fig. 2 is a block diagram of the filter capacitor discharge circuit of the present invention;

FIG. 3A is a block diagram of a range detector according to a first embodiment of the present invention;

FIG. 3B is a schematic diagram of a first embodiment of a range detector of the present invention with an AC voltage waveform;

FIG. 3C is a schematic diagram of a first embodiment of the range detector with the AC voltage removed;

FIG. 4A is a block diagram of a range detector according to a second embodiment of the present invention;

FIG. 4B is a schematic diagram of a second embodiment of the range detector of the present invention with a waveform of AC voltage;

FIG. 4C is a schematic diagram of a second embodiment of the range detector of the present invention with the AC voltage removed;

fig. 5A is a flowchart illustrating an operation method of discharging the filter capacitor according to the present invention;

fig. 5B is a flowchart of a range detection operation method according to a first embodiment of the present invention; and

fig. 5C is a flowchart illustrating a second embodiment of the range detection method according to the present invention.

Wherein, the reference numbers:

100 … conversion circuit

100-1 … input terminal

C … filter capacitor

10 … detection circuit

D1 … first diode

D2 … second diode

R … resistor

20 … conversion unit

22 … rectifier circuit

Q … power switch

30 … control unit

32 … filter capacitor discharge circuit

32-1 … high pressure end

322 … signal preparation circuit

324 … low-pass filter

326. 326' … range detector

3262. 3262' … Range Generation Circuit

AU … addition unit

SU … subtraction unit

3264 … comparator circuit

OP1 … first comparison unit

OP2 … second comparison unit

LG … logic cell

328 … timing unit

330 … switch unit

332 … high-voltage start NMOS transistor

200 … load

Vac … AC voltage

Vdc … DC voltage

Vo … output voltage

Upper limit voltage of Vu, Vu' …

Lower limit voltage of Vl, Vl' …

V1 … first reference voltage

V2 … second reference voltage

Ss … detection signal

Sv … Voltage Signal

Sf … filtered signal

Se … enable signal

Sc … control signal

CLK … frequency signal

S1 … first comparison signal

S2 … second comparison signal

Distance of X … voltage

t1, t2 … time

Detailed Description

The technical content and the detailed description of the present invention are described below with reference to the drawings:

fig. 1 is a block diagram of a conversion circuit with a filter capacitor discharge circuit according to the present invention. The input terminal 100-1 of the converting circuit 100 receives the ac voltage Vac, and converts the ac voltage Vac into an output voltage Vo to supply power to the load 200. The converting circuit 100 includes a filter capacitor C, a detecting circuit 10, a converting unit 20 and a control unit 30. The filter capacitor C is coupled to the input terminal 100-1 and filters the ac voltage Vac. The detection circuit 10 detects the ac voltage Vac, and provides a detection signal Ss to the control unit 30 according to the ac voltage Vac. The control unit 30 controls the converting unit 20 to convert the ac voltage Vac into the output voltage Vo, and controls whether the filter capacitor C is discharged or not (indicated by a dotted line) according to the received detection signal Ss.

Further, the control unit 30 includes a filter capacitance discharge circuit 32. The filter capacitor discharging circuit 32 receives the detection signal Ss through the high voltage terminal 32-1, and determines whether to discharge the filter capacitor C according to the detection signal Ss. When the filter capacitor discharging circuit 32 determines that the ac voltage Vac exists according to the detection signal Ss, the filter capacitor discharging circuit 32 does not discharge the filter capacitor C, so as to maintain the stable operation of the converting circuit 100. When the filter capacitor discharging circuit 32 determines that the ac voltage Vac does not exist (for example, but not limited to, the plug is unplugged) according to the detection signal Ss, the filter capacitor discharging circuit 32 discharges the filter capacitor C to discharge the energy remaining in the filter capacitor C, so as to meet the safety regulations and avoid the risk of electric shock of personnel.

Referring to fig. 1, the detection circuit 10 includes a first diode D1, a second diode D2, and a resistor R. The first diode D1 and the second diode D2 rectify the ac voltage Vac into the detection signal Ss of continuous half-sine wave, and the resistor R limits the current on the path of the detection circuit 10, so as to prevent the control unit 30 from being damaged due to the excessive current flowing through the high voltage terminal 32-1. It should be noted that, in an embodiment of the present invention, the structure of the detection circuit 10 is not limited, and for example, the detection circuit (e.g., a full-bridge rectification structure) that can rectify the ac voltage Vac into the continuous or discontinuous half-sine wave detection signal Ss should be included in the scope of the present embodiment.

The conversion unit 20 is exemplified by a flyback converter (flyback converter). The converting unit 20 converts the ac voltage Vac into the dc voltage Vdc through the rectifying circuit 22, and the control unit 30 controls switching of the power switch Q (i.e., the main switch of the flyback converter) to convert the dc voltage Vdc into the output voltage Vo. However, in an embodiment of the present invention, the converting unit 20 is not limited to the flyback converter, and any converting device having a dc power converting function should be included in the scope of the present embodiment. In an embodiment of the present invention, the power supply mode of the control unit 30 and the feedback detection and control mode of the control unit 30 to the conversion unit 20 may be techniques known to those skilled in the art, and are not described herein again.

Fig. 2 is a block diagram of the filter capacitor discharge circuit of the present invention, and fig. 1 is also included in the present invention. The filter capacitor discharging circuit 32 includes a high voltage terminal 32-1, a signal preparation circuit 322, a low pass filter 324, a range detector 326, a timing unit 328, a switch unit 330, and a high voltage start (HV start) NMOS transistor 332. The switch unit 330 mainly functions to discharge the filter capacitor C, so that the coupling position thereof is only required to discharge the filter capacitor C (indicated by a dotted line). Fig. 2 merely illustrates that when the switch unit 330 is turned on, the filter capacitor C can be discharged by the high-voltage-enabled NMOS transistor 332 and the detection circuit 10, but the coupling position of the switch unit 330 and the filter capacitor C is not limited thereto. In another embodiment, the switching unit 330 may directly discharge the filter capacitor C.

The signal preparation circuit 322 receives the detection signal Ss through the high voltage terminal 32-1, and generates a voltage signal Sv representing the ac voltage Vac according to the detection signal Ss. The signal preparing circuit 322 is, for example but not limited to, a voltage dropping circuit, and mainly converts the received high voltage detecting signal Ss into a low voltage signal Sv tolerable by the control unit 30. The signal preparation circuit 322 may be a voltage divider circuit formed by a resistor external to the control unit 30, or may be a voltage divider or step-down circuit formed by an integrated circuit device (including but not limited to a resistor, a transistor, etc.) inside the control unit 30.

The low pass filter 324 receives the voltage signal Sv and provides a filtered signal Sf according to the voltage signal Sv. The low pass filter 324 may be a first, second or third order low pass filter, and the higher order filter has a corresponding filtering effect closer to the ideal.

The range detector 326 receives the voltage signal Sv and the filtered signal Sf, compares the voltage signal Sv and the filtered signal Sf, and provides an enable signal Se to the timing unit 328 according to the comparison result. Specifically, the range detector 326 checks whether the voltage distance between the voltage signal Sv and the filtered signal Sf is smaller than a predetermined value. When the voltage distance between the voltage signal Sv and the filtering signal Sf is smaller than the default value, the voltage value representing the voltage signal Sv is close to the voltage value of the filtering signal Sf. The reason for this may be that the voltage value of the alternating voltage Vac is rising or falling, or the plug is removed. When the voltage value of the ac voltage Vac is rising or falling, the time for the voltage distance between the voltage signal Sv and the filtered signal Sf to be less than the default value is generally short, and when the plug is removed, the time for the voltage distance between the voltage signal Sv and the filtered signal Sf to be less than the default value is generally long. Therefore, whether the plug is removed or not can be judged by the characteristic so as to determine whether to discharge the filter capacitor C or not.

The timing unit 328 receives the enable signal Se and the clock signal CLK, and provides the control signal Sc to the switch unit 330 according to the enable signal Se and the clock signal CLK. When the voltage distance between the voltage signal Sv and the filtering signal Sf is smaller than the predetermined value (known from the enable signal Se), the timing unit 328 starts to count according to the clock signal CLK to generate a pulse number, and determines whether to control the switch unit 330 to be turned on according to the pulse number. For example, when the number of pulses is greater than or equal to a predetermined number, it means that the plug is removed. At this time, the timing unit 328 controls the switch unit 330 to be turned on by the control signal Sc, so that the energy remaining in the filter capacitor C is discharged by the turn-on of the switch unit 330. In another embodiment, the timing unit 328 is triggered by the enable signal Se to start generating a ramp signal, and when the ramp signal is higher than a predetermined value, the timing result is determined to exceed a predetermined time, that is, the plug is removed, and the switch unit 330 is started to discharge the filter capacitor C.

The predetermined time, the predetermined number of times, or the predetermined value may be preset by the filter capacitor discharging circuit 32, and may be adjusted according to actual requirements. In one embodiment, the predetermined time is approximately hundreds of microseconds (us).

Please refer to fig. 3A, which is a block diagram of a range detector according to a first embodiment of the present invention, and fig. 1-2 are combined together. The range detector 326 includes a range generation circuit 3262 and a comparison circuit 3264. The range generating circuit 3262 receives the filter signal Sf, and generates an upper limit voltage Vu corresponding to an upper limit of the voltage distance and a lower limit voltage Vl corresponding to a lower limit of the voltage distance according to the filter signal Sf. The comparing circuit 3264 checks whether the voltage signal Sv falls between the upper limit voltage Vu and the lower limit voltage Vl, and provides an enable signal Se to the timing unit 328 according to the checking result. When the voltage signal Sv falls between the upper limit voltage Vu and the lower limit voltage Vl, the voltage distance between the representative voltage signal Sv and the filtered signal Sf is smaller than a default value (the voltage difference between the upper limit voltage Vu and the lower limit voltage Vl represents the voltage distance).

Specifically, range generation circuit 3262 includes an addition unit AU and a subtraction unit SU, and the addition unit AU and the subtraction unit SU are coupled between low pass filter 324 and comparison circuit 3264. The addition unit AU is used for adding the filtered signal Sf to the first reference voltage V1 to generate the upper limit voltage Vu, and the subtraction unit SU is used for subtracting the second reference voltage V2 from the filtered signal Sf to generate the lower limit voltage Vl. The voltage values of the first reference voltage V1 and the second reference voltage V2 may be the same or different, and in practice, the voltage distance can be adjusted by adjusting the voltage values of the first reference voltage V1 and the second reference voltage V2.

The comparison circuit 3264 includes a first comparison unit OP1, a second comparison unit OP2, and a logic unit LG.

The first comparison unit OP1 compares the upper limit voltage Vu with the voltage signal Sv to provide a first comparison signal S1.

The second comparing unit OP2 compares the lower limit voltage Vl with the voltage signal Sv to provide a second comparison signal S2. The logic unit LG may be an AND gate (AND) that provides an enable signal Se to the timing unit 328 according to the first comparison signal S1 AND the second comparison signal S2.

When the first comparison signal S1 and the second comparison signal S2 are both at the first level, the voltage distance between the representative voltage signal Sv and the filtered signal Sf is smaller than the predetermined value, and the comparison circuit 3264 uses the enable signal Se to notify the timing unit 328 to start counting, so that the timing unit 328 starts counting the clock signal CLK. It should be noted that, in an embodiment of the present invention, the first comparing unit OP1 and the second comparing unit OP2 are comparators, but not limited thereto. In other words, a comparison unit (for example, but not limited to, a comparison unit formed by a voltage division circuit) capable of comparing two input signals to generate a comparison result accordingly is included in the scope of the present embodiment. In addition, in an embodiment of the present invention, the logic unit LG is not limited to be formed by using an AND gate (AND). For example, a logic unit LG (for example, but not limited to, a NAND gate (NAND gate)) capable of converting the levels of the output signals according to the conversion of two input signals into the same level is included in the scope of the present embodiment.

Please refer to fig. 3B for a schematic diagram of a waveform of the range detector with ac voltage according to the first embodiment of the present invention, and fig. 3C for a schematic diagram of a waveform of the range detector with ac voltage removed according to the first embodiment of the present invention, which is combined with fig. 1-3A and fig. 3A-3C. The high voltage terminal 32-1 receives the detection signal Ss of the continuous half sine wave, and the signal preparation circuit 322 steps down the detection signal Ss to the voltage signal Sv. The low pass filter 324 filters the voltage signal Sv to generate a filtered signal Sf, and the range generation circuit 3262 generates an upper limit (i.e., an upper limit voltage Vu) corresponding to the voltage distance X according to the filtered signal Sf and the first reference voltage V1, and generates a lower limit (i.e., a lower limit voltage Vl) corresponding to the voltage distance X according to the filtered signal Sf and the second reference voltage V2. In fig. 3B, when the voltage level of the voltage signal Sv is rising or falling, it will fall between the upper limit voltage Vu and the lower limit voltage Vl for a short time, so that the voltage distance X between the voltage signal Sv and the filtered signal Sf is smaller than the default value. At this time, the logic unit LG notifies the timing unit 328 to start timing according to the above, so that the timing unit 328 starts counting the clock signal CLK. Since the time during which the voltage value of the voltage signal Sv falls between the upper limit voltage Vu and the lower limit voltage Vl is short in the situation where the voltage value of the voltage signal Sv is rising or falling with the ac voltage Vac, the number of pulses accumulated by the timing unit 328 is not greater than or equal to the predetermined number of times (or the accumulated time is not greater than or equal to the predetermined time). Therefore, in this situation, the control signal Sc provided by the timing unit 328 maintains the switch unit 330 to be turned off and open, and the filter capacitor C is not drained.

In fig. 3C, at time t1, the plug is removed. At this time, the ac voltage Vac is cut off, so that the voltage signal Sv interrupts the variation of the half-sine wave and is substantially maintained at the constant value (the constant value is the energy still stored in the filter capacitor C) which is slowly decreased. At this time, since the half-string wave variation of the voltage signal Sv is interrupted, the voltage value of the voltage signal Sv filtered by the low-pass filter 324 (i.e., the filtered signal Sf) starts to approach the voltage signal Sv maintained at the constant value. Therefore, the voltage value of the voltage signal Sv is brought between the upper limit voltage Vu and the lower limit voltage Vl (i.e., the range of the upper limit voltage Vu and the lower limit voltage Vl is close to the voltage value of the voltage signal Sv), resulting in the voltage distance X being smaller than the default value. For convenience of illustration, the present embodiment shows that the voltage signal Sv happens to be between the upper limit voltage Vu and the lower limit voltage Vl when the plug is removed (time t 1). At time t1, the logic unit LG notifies the timing unit 328 to start timing, so that the timing unit 328 starts counting the clock signal CLK, and the voltage distance X is always smaller than the default value because the voltage signal Sv is maintained at a constant value, so the timing unit 328 continues counting the clock signal CLK. At time t2, when the timing unit 328 determines that the number of pulses is greater than or equal to the predetermined number of times or the time counted by the timing unit 328 is greater than or equal to the predetermined time (i.e., from time t1 to time t2), the timing unit 328 controls the switch unit 330 to turn on by the control signal Sc, so as to discharge the energy remaining in the filter capacitor C.

Please refer to fig. 4A, which is a block diagram of a second embodiment of the range detector of the present invention, and fig. 1-2 are combined together. The range detector 326' of fig. 4A is identical and similar to the range detector 326 of fig. 3A, and will not be repeated in light of the previous teachings. The difference between fig. 4A and fig. 3A is that: the filtered signal Sf is just interchanged with the voltage signal Sv. Briefly, the range detector 326 in fig. 3A generates the upper limit voltage Vu and the lower limit voltage Vl based on the filtered signal Sf, and then checks whether the voltage signal Sv is between the upper limit voltage Vu and the lower limit voltage Vl. The range detector 326 ' in fig. 4A generates the upper limit voltage Vu ' and the lower limit voltage Vl ' based on the voltage signal Sv, and then checks whether the filtered signal Sf is located between the upper limit voltage Vu ' and the lower limit voltage Vl '.

The addition unit AU is used for adding the voltage signal Sv to the first reference voltage V1 to generate the upper limit voltage Vu ', and the subtraction unit SU is used for subtracting the second reference voltage V2 from the voltage signal Sv to generate the lower limit voltage Vl'. The first comparing unit OP1 receives the upper limit voltage Vu 'and the filtered signal Sf, and compares the upper limit voltage Vu' and the filtered signal Sf to provide a first comparison signal S1. The second comparing unit OP2 receives the lower limit voltage Vl 'and the filtered signal Sf, and compares the lower limit voltage Vl' with the filtered signal Sf to provide a second comparison signal S2. It should be noted that the circuits and control methods not mentioned in fig. 4A are the same as those in fig. 3A, and are not described herein again.

Please refer to fig. 4B for a waveform diagram of the range detector according to the second embodiment of the present invention with ac voltage, and fig. 4C for a waveform diagram of the range detector according to the second embodiment of the present invention with ac voltage removed, which is combined with fig. 1-4A and fig. 4A-4C. The range generating circuit 3262 ' generates an upper limit voltage Vu ' corresponding to an upper limit of the voltage distance X (i.e., the first reference voltage V1) and a lower limit voltage Vl ' corresponding to a lower limit of the voltage distance X (i.e., the second reference voltage V2) according to the voltage signal Sv. In fig. 4B, when the voltage value of the filtered signal Sf is rising or falling, it will fall between the upper limit voltage Vu 'and the lower limit voltage Vl' for a short time, so that the voltage distance X between the voltage signal Sv and the filtered signal Sf is smaller than the default value. Since the time during which the voltage value of the filter signal Sf falls between the upper limit voltage Vu 'and the lower limit voltage Vl' is short in the situation where the voltage value of the filter signal Sf is rising or falling with the ac voltage Vac, the number of pulses accumulated by the timing unit 328 is not greater than or equal to the predetermined number (or the accumulated time is not greater than or equal to the predetermined time). Therefore, in this situation, the control signal Sc provided by the timing unit 328 does not turn on the switch unit 330, so that the energy remaining in the filter capacitor C is discharged.

In fig. 4C, at time t1, the plug is removed. At this time, the ac voltage Vac is cut off, so that the voltage signal Sv interrupts the variation of the half-sine wave and is substantially maintained at the constant value (the constant value is the energy still stored in the filter capacitor C) which is slowly decreased. At this time, since the half-string wave variation of the voltage signal Sv is interrupted, the upper limit voltage Vu 'and the lower limit voltage Vl' generated according to the voltage signal Sv are also maintained at constant values. At this time, the voltage signal Sv filtered by the low-pass filter 324 (i.e., the filtered signal Sf) gradually approaches the voltage signal Sv maintained at the constant value. Therefore, the voltage value of the voltage signal Sv is brought between the upper limit voltage Vu 'and the lower limit voltage Vl' (i.e., the voltage value of the filtered signal Sf is brought close to the range of the upper limit voltage Vu 'and the lower limit voltage Vl'), resulting in the voltage distance X being smaller than the default value. For convenience of illustration, the embodiment shows that the filtering signal Sf happens to be between the upper limit voltage Vu 'and the lower limit voltage Vl' when the plug is removed (time t 1). It should be noted that the waveforms and control methods not mentioned in fig. 4B and 4C are the same as those in fig. 3B and 3C, and are not described herein again.

Fig. 5A is a flow chart of an operation method of discharging the filter capacitor according to the present invention, and fig. 1 to 4C are combined. Referring to the flowchart shown in fig. 5A, the operation method of discharging the filter capacitor C at the input terminal 100-1 of the converter circuit 100 mainly when the ac voltage Vac is powered off includes providing a voltage signal Sv representing the ac voltage Vac according to the ac voltage Vac (S100). The detection circuit 10 detects the ac voltage Vac to obtain a detection signal Ss indicative of the ac voltage Vac, and the signal preparation circuit 322 processes (steps down) the detection signal Ss to obtain a voltage signal Sv. The voltage signal Sv is then low-pass filtered to generate a filtered signal Sf (S120). The low pass filter 324 receives the voltage signal Sv and provides a filtered signal Sf according to the voltage signal Sv. Then, the range detector 326 checks whether the voltage distance X between the voltage signal Sv and the filtered signal Sf is smaller than a predetermined value, and provides an enable signal Se to the timing unit 328 according to the result (S140).

Then, when the voltage distance X is smaller than the default value, the timing is started to generate a timing result (S160). The timing unit 328 generates the number of pulses according to the count of the clock signal CLK. When the voltage distance between the voltage signal Sv and the filtered signal Sf is smaller than the predetermined value (known from the enable signal Se), the timing unit 328 starts to count according to the clock signal CLK to generate the pulse number. Finally, when the timing result exceeds a predetermined time (for example, the number of pulses exceeds a predetermined number of times, or the duration of receiving a plurality of pulses exceeds a predetermined time), which indicates that the plug is removed, the timing unit 328 controls the switch unit 330 to turn on through the control signal Sc, so as to discharge the filter capacitor C (S180).

Please refer to fig. 5B for a flowchart of a first embodiment of the operation method for range detection of the present invention, and fig. 5C for a flowchart of a second embodiment of the operation method for range detection of the present invention, which are combined with fig. 1 to 5A. In fig. 5B, the step (S140) includes steps (S200), (S220) and (S240). The addition unit AU adds the filtered signal Sf to the first reference voltage V1 to generate the upper limit voltage Vu, and the subtraction unit SU subtracts the second reference voltage V2 from the filtered signal Sf to generate the lower limit voltage Vl (S200). The first comparing unit OP1 compares the upper limit voltage Vu with the voltage signal Sv to provide a first comparison signal S1, and the second comparing unit OP2 compares the lower limit voltage Vl with the voltage signal Sv to provide a second comparison signal S2 (S220). The logic unit LG receives the first comparison signal S1 and the second comparison signal S2, checks whether the voltage signal Sv falls between the upper limit voltage Vu and the lower limit voltage Vl, and provides an enable signal Se whether to start timing according to the check result (S240). When the first comparison signal S1 and the second comparison signal S2 are both at the first level, the voltage distance between the representative voltage signal Sv and the filtered signal Sf is smaller than the predetermined value, and the enabling signal Se notifies the timing unit 328 to start counting, so that the timing unit 328 starts counting the clock signal CLK.

In fig. 5C, the step (S140) includes steps (S300), (S320) and (S340). The addition unit AU adds the voltage signal Sv to the first reference voltage V1 to generate the upper limit voltage Vu ', and the subtraction unit SU subtracts the second reference voltage V2 from the voltage signal Sv to generate the lower limit voltage Vl' (S300). The first comparing unit OP1 compares the upper limit voltage Vu 'with the filtered signal Sf to provide a first comparison signal S1, and the second comparing unit OP2 compares the lower limit voltage Vl' with the filtered signal Sf to provide a second comparison signal S2 (S320). Step (S340) is the same as or similar to step (S240) in fig. 5B, and can be understood according to the previous teaching, and will not be repeated.

The above detailed description and drawings of the embodiments are not intended to limit the present invention, but should not be construed as limiting the scope of the present invention, and all the scope of the present invention is defined by the appended claims, and all the embodiments that combine the spirit of the present invention and similar changes therein are intended to be encompassed by the present invention, and any changes and modifications that can be easily conceived by those skilled in the art are intended to be encompassed by the scope of the present invention.

Of course, the present invention can have other embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, and these corresponding changes and modifications should fall within the protection scope of the claims of the present invention.

Claims

1. A filter capacitor discharge circuit, comprising:

a high voltage terminal coupled to a filter capacitor of an input terminal, the input terminal receiving an alternating voltage;

a signal preparation circuit coupled to the high voltage terminal for generating a voltage signal representing the AC voltage;

a low-pass filter for providing a filter signal according to the voltage signal;

a range detector for comparing the voltage signal with the filtered signal to check whether a voltage distance between the voltage signal and the filtered signal is less than a default value;

a timing unit, which starts timing to generate a timing result when the voltage distance is less than the default value; and

and the timing unit enables the switch unit to be conducted when the timing result exceeds a preset time, so that the filter capacitor is discharged through the switch unit.

2. The filter capacitor discharge circuit of claim 1, wherein the range detector comprises:

a range generating circuit for generating an upper limit voltage and a lower limit voltage according to the filtering signal; and

a comparison circuit for checking whether the voltage signal falls between the upper limit voltage and the lower limit voltage and providing an enable signal to the timing unit according to the checking result.

3. The filter capacitor discharge circuit of claim 2, wherein the range generation circuit comprises:

an adding unit for adding a first reference voltage to the filtered signal to generate the upper limit voltage; and

a subtraction unit for subtracting a second reference voltage from the filtered signal to generate the lower limit voltage.

4. The filter capacitor discharge circuit of claim 2, wherein the comparison circuit comprises:

a first comparing unit for comparing the upper limit voltage with the voltage signal to provide a first comparison signal;

a second comparing unit for comparing the lower limit voltage with the voltage signal to provide a second comparison signal; and

a logic unit for providing the enable signal according to the first comparison signal and the second comparison signal.

5. The filter capacitor discharge circuit of claim 1, wherein the range detector comprises:

a range generating circuit for generating an upper limit voltage and a lower limit voltage according to the voltage signal; and

a comparison circuit for checking whether the filtering signal falls between the upper limit voltage and the lower limit voltage and providing an enable signal to the timing unit according to the checking result.

6. The filter capacitor discharge circuit of claim 5, wherein the range generation circuit comprises:

an adding unit for adding a first reference voltage to the voltage signal to generate the upper limit voltage; and

a subtraction unit for subtracting a second reference voltage from the voltage signal to generate the lower limit voltage.

7. The filter capacitor discharge circuit of claim 5, wherein the comparison circuit comprises:

a first comparing unit for comparing the upper limit voltage with the filtering signal to provide a first comparison signal;

a second comparison unit for comparing the lower limit voltage with the filtering signal to provide a second comparison signal; and

a logic unit for providing the enable signal representing the checking result according to the first comparison signal and the second comparison signal.

8. The filter capacitor discharging circuit of claim 1, wherein the timing unit generates a pulse number according to a count of a frequency signal, and when the pulse number is greater than or equal to a predetermined number of times, the timing unit determines that the timing result exceeds the predetermined time, and turns on the switch unit.

9. A conversion circuit, comprising:

a filter capacitor, which receives an AC voltage from an input terminal;

a detection circuit for detecting the AC voltage and providing a detection signal; and

the filter capacitor discharge circuit of claim 1, wherein the high voltage terminal receives the detection signal.