CN212486838U - Light emitting diode driving apparatus and light emitting diode driver - Google Patents
Light emitting diode driving apparatus and light emitting diode driver Download PDFInfo
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- CN212486838U CN212486838U CN202021672768.0U CN202021672768U CN212486838U CN 212486838 U CN212486838 U CN 212486838U CN 202021672768 U CN202021672768 U CN 202021672768U CN 212486838 U CN212486838 U CN 212486838U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The utility model relates to a emitting diode drive apparatus with embedded cascade emitting diode driver of clock, a serial communication port contains: and the first-stage light emitting diode driver receives the initial data signal and outputs a first data signal, and the Nth-stage light emitting diode driver receives the N-1 th data signal and outputs an Nth data signal. The nth stage led driver includes: a clock data recovery circuit for generating a recovered clock signal and a recovered data signal based on the N-1 th data signal; and a first transmitter outputting an Nth data signal according to the recovered clock signal and the recovered data signal.
Description
Technical Field
The utility model relates to a light-emitting diode (LED) driving device.
Background
Typically, a cascaded LED driver transmission interface is used in LED display systems. In a cascaded LED driver transmission interface, in addition to using a data signal line in any two adjacent LED drivers for data transmission, a common clock signal line is used and coupled to each of the cascaded LED drivers. However, the common clock signal line may cause large parasitic capacitance and limit the speed of data transfer. Furthermore, skew between the common clock signal and the data signal in each of the cascaded LED drivers may cause another problem and further limit the speed of data transmission.
Nothing herein is to be construed as an admission that any of the prior art forms part of the present invention.
SUMMERY OF THE UTILITY MODEL
As the demand for high resolution and better performance of LED display systems has increased in recent years, the need for more creative techniques to increase the speed of data transmission by using clock embedded cascaded LED driver transmission interfaces has increased.
The utility model provides a LED drive apparatus with embedded cascade LED driver of clock, LED drive apparatus can carry out data transmission under the condition that does not have public clock signal line, and consequently avoids the restriction to data transmission's speed that leads to because of the skew between the data signal in great parasitic capacitance and the public clock signal that comes from public clock signal line and each in cascading the LED driver.
In an embodiment of the present invention, the LED driving apparatus is characterized by including: a plurality of led drivers, wherein a first led driver receives an initial data signal and outputs a first data signal, an nth led driver receives an N-1 th data signal and outputs an nth data signal, and N is a positive integer, wherein the nth led driver comprises: a clock data recovery circuit for generating a recovered clock signal and a recovered data signal according to the N-1 th data signal; and a first transmitter outputting the Nth data signal according to the recovered clock signal and the recovered data signal.
In an embodiment of the present invention, the LED driver is characterized by comprising: a clock data recovery circuit receiving the data signal to generate a recovered clock signal and a recovered data signal; a data memory for storing the recovered data signal; and a transmitter outputting a next-stage data signal according to the recovered clock signal and the recovered data signal.
In summary, in the LED driving apparatus provided by the present invention, the cost of chip packaging and the complexity of printed circuit board wiring are reduced by transmitting data signals between each of the LED drivers without a common clock signal, and thus the transmission speed of the data signals is increased.
In order that the foregoing may be more readily understood, several embodiments are described in detail below with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a Light Emitting Diode (LED) driving apparatus according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an LED driver in an LED driving apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of an LED driver in an LED driving apparatus according to another embodiment of the present invention.
Fig. 4 is a schematic diagram of an LED driver in an LED driving apparatus according to another embodiment of the present invention.
Fig. 5 is a schematic diagram of a clock data recovery circuit in an LED driving apparatus according to an embodiment of the present invention.
Fig. 6A to 6B are schematic diagrams of a phase-locked loop circuit and a delay-locked loop circuit in an LED driving apparatus according to an embodiment of the present invention.
Description of the reference numerals
100: a light emitting diode driving device;
101. 101a, 101b, 101 c: a light emitting diode driver;
102: a controller;
103: a light emitting diode;
201: an equalizer;
202. 202 a: a clock data recovery circuit;
203: a register;
204: a transmitter;
403: a first-in first-out circuit;
405: a phase-locked loop circuit or a delay-locked loop circuit;
405 a: a phase-locked loop circuit;
405 b: a delay locked loop circuit;
406: a crystal oscillator;
501: a phase discriminator;
502: a frequency discriminator;
507: a voltage controlled oscillator or voltage controlled delay line;
508: a decision circuit;
data _ 1: a first data signal;
data _ 2: a second data signal;
data _ N: an Nth data signal;
data _ in: an equalized data signal;
data _ out: recovering the data signal through sampling;
CLK: inputting a clock signal;
DIN: recovering the data signal;
GCLK: a gray scale control clock signal;
SCLK: recovering the clock signal;
SCLK 1: the clock signal is read first in first out.
Detailed Description
Embodiments of the present invention are described below with reference to the drawings.
Fig. 1 is a schematic diagram of an LED driving apparatus 100 according to an embodiment of the present invention. The LED driving apparatus 100 includes a plurality of LED drivers 101, a controller 102, and a plurality of LEDs 103. The plurality of LED drivers 101 includes cascaded N-stage LED drivers from LED driver 1 to LED driver N, and N is a positive number. The controller 102 outputs an initial data signal to the first stage LED driver 1, the first stage LED driver 1 receives the initial data signal and outputs a first data signal data _1 to the second stage LED driver 2, and the N-1 th stage LED driver N-1 receives the N-2 th data signal data _ (N-2) and outputs the N-1 th data signal data _ (N-1) to the N-th stage LED driver N.
Fig. 2 is a schematic diagram of an LED driver 101a in the LED driving apparatus 100 according to an embodiment of the present invention. As shown in fig. 1 and 2, the nth stage LED driver N includes an Equalizer (EQ) 201, a Clock Data Recovery (CDR) circuit 202, a first register 203, and a first transmitter 204. The EQ 201 in the LED driver N receives the N-1 th data signal data _ (N-1) and generates an equalized data signal data _ in to the CDR circuit 202, the N-1 th data signal data _ (N-1) including the previous stage display data signal and the previous stage clock signal encoded in the first encoding format. The CDR circuit 202 receives the equalized data signal data _ in and generates a gray-scale control clock signal GCLK, a recovery clock signal SCLK, and a recovery data signal DIN according to a first phase difference between the equalized data signal data _ in and the recovery clock signal SCLK. The gray scale of the LED display is controlled using a gray scale control clock signal GCLK. The first register 203 is a data memory for storing the recovered data signal. The recovered clock signal SCLK and the recovered data signal DIN are input to the first register 203 to generate a first sampled recovered data signal data _ out. The first transmitter 204 in the LED driver N receives the first sampled recovered data signal data _ out and outputs an nth data signal data _ N including a next stage display data signal and a next stage clock signal encoded in a first encoding format according to the recovered clock signal SCLK and the recovered data signal DIN.
The plurality of LEDs 103 include N-level LEDs from the LED1 to the LED N corresponding to the LED drivers 1 to N, respectively, and the nth-level LED driver N drives the nth-level LED N according to the gray scale control clock signal GCLK and the recovery data signal DIN in the LED driver N. The LED drivers 1 to N may have the same circuit configuration.
As shown in fig. 2, the first register 203 receives the recovered data signal DIN and the recovered clock signal SCLK to sample the recovered data signal DIN at the clock signal edge of the recovered clock signal SCLK to generate a first sampled recovered data signal data _ out according to the sampled value of the recovered data signal DIN and the clock signal edge of the recovered clock signal SCLK, and the first transmitter 204 in the LED driver N receives the first sampled recovered data signal data _ out and outputs an nth data signal data _ N according to the first sampled recovered data signal data _ out, the data signal data _ N including a next-stage display data signal and a next-stage clock signal encoded in a first encoding format.
Fig. 3 is a schematic diagram of an LED driver 101b in an LED driving apparatus 100 according to another embodiment of the present invention. Compared to the LED driver 101a of fig. 2, the LED driver 101b further comprises a second register 203 and a second emitter 204. The second register 203 in the LED driver N receives the error signal and the recovery clock signal SCLK from the nth stage LED N to sample the error signal at the clock signal edge of the recovery clock signal SCLK to generate a sampled error signal according to the sampled value of the error signal and the clock signal edge of the recovery clock signal SCLK.
The second transmitter 204 in the LED driver N receives the sampled error signal and outputs an error readback signal to the controller 102 according to the sampled error signal, the error readback signal indicating a defect in the nth level LED N, where the first and second transmitters 204, 204 may share the same transmitter.
Fig. 4 is a schematic diagram of an LED driver 101c in an LED driving apparatus 100 according to another embodiment of the present invention. Compared to the LED driver 101a of fig. 2, the LED driver 101c further comprises a phase-locked loop (PLL) circuit or a delay-locked loop (DLL) circuit 405 and a crystal oscillator (XTAL OSC)406, and the first register 203 in the LED driver 101a is replaced by a First In First Out (FIFO) circuit 403 in the LED driver 101 c.
The FIFO circuit 403 is a data memory for storing the restored data signal. The FIFO circuit 403 receives the recovered data signal DIN, the recovered clock signal SCLK, and the FIFO read clock signal SCLK1 to sample the recovered data signal DIN at the clock signal edge of the recovered clock signal SCLK to generate the second sampled recovered data signal data _ out according to the sampled value of the recovered data signal DIN and the clock signal edge of the FIFO read clock signal SCLK 1.
Fig. 6A to 6B are schematic diagrams of a PLL circuit 405a and a DLL circuit 405B in the LED driving device 100 according to an embodiment of the present invention. The FIFO read clock signal SCLK1 is generated by either the PLL circuit 405a or the DLL circuit 405 b. XTAL OSC 406 generates an input clock signal CLK to PLL circuit 405a, and PLL circuit 405a receives the input clock signal CLK to generate a FIFO sense clock signal SCLK1 according to a second phase difference between the input clock signal CLK and FIFO sense clock signal SCLK1, and PLL circuit 405a includes a frequency divider.
In another embodiment of the present invention, XTAL OSC 406 generates an input clock signal CLK to DLL circuit 405b, and DLL circuit 405b receives the input clock signal CLK to generate a FIFO read clock signal SCLK1 according to a third phase difference between the input clock signal CLK and FIFO read clock signal SCLK 1.
Fig. 5 is a schematic diagram of a CDR circuit 202a in the LED driving apparatus 100 according to an embodiment of the present invention. CDR circuit 202a in LED driver N includes: a phase detector 501 receiving the N-1 th data signal data _ (N-1) and the recovery clock signal SCLK to generate a phase detection signal according to a first phase difference between the N-1 th data signal data _ (N-1) and the recovery clock signal SCLK; a frequency discriminator 502 receiving the N-1 th data signal data _ (N-1) and the recovery clock signal SCLK to generate a frequency discriminated signal according to a frequency difference between the N-1 th data signal data _ (N-1) and the recovery clock signal SCLK; a voltage-controlled oscillator (VCO) 507 or a voltage-controlled delay line (VCDL) 507 for generating a recovered clock signal SCLK according to the phase and frequency discrimination signals; and a decision circuit 508 receiving the N-1 th data signal data _ (N-1) and the recovery clock signal SCLK to generate a recovery data signal DIN according to the N-1 th data signal data _ (N-1) and the recovery clock signal SCLK.
As with the LED drivers 101a to 101c respectively depicted in fig. 2 to 4, the CDR circuit 202 in the LED driver N further generates a gray scale control clock signal GCLK according to the recovered clock signal SCLK to control the gray scale of the nth-stage LED N.
According to the above embodiments, an LED driving apparatus 100 having a clock-embedded cascade LED driver is introduced, which LED driving apparatus 100 is capable of data transmission without a common clock signal line, and thus avoids limitation of speed of data transmission due to a large parasitic capacitance from the common clock signal line and skew between the common clock signal and a data signal in each of the cascade LED drivers. With the LED driving apparatus 100, the cost of chip packaging and the complexity of printed circuit board wiring are reduced by transmitting a data signal between each of the LED drivers without a common clock signal, and thus the transmission speed of the data signal is increased.
While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.
Claims (24)
1. A light emitting diode driving apparatus, comprising:
a plurality of led drivers, wherein a first led driver receives an initial data signal and outputs a first data signal, an nth led driver receives an N-1 th data signal and outputs an nth data signal, and N is a positive integer, wherein the nth led driver comprises:
a clock data recovery circuit for generating a recovered clock signal and a recovered data signal according to the N-1 th data signal; and
a first transmitter to output the Nth data signal according to the recovered clock signal and the recovered data signal.
2. The light emitting diode driving apparatus according to claim 1, wherein the nth-stage light emitting diode driver comprises:
an equalizer receiving said N-1 data signal and generating an equalized data signal to said clock data recovery circuit; and
a first register to receive the recovered data signal and the recovered clock signal to sample the recovered data signal at a clock signal edge of the recovered clock signal to generate a first sampled recovered data signal based on sampled values of the recovered data signal and the clock signal edge of the recovered clock signal,
wherein the first transmitter receives the first sampled recovered data signal and outputs the Nth data signal in accordance with the first sampled recovered data signal.
3. The light emitting diode driving apparatus according to claim 2, wherein the nth-stage light emitting diode driver comprises:
a second register to receive an error signal and the recovered clock signal to sample the error signal at a clock signal edge of the recovered clock signal to generate a sampled error signal based on the sampled value of the error signal and the clock signal edge of the recovered clock signal, wherein the error signal is from an nth stage light emitting diode; and
a second transmitter to receive the sampled error signal and to output an error readback signal to a controller as a function of the sampled error signal, wherein the error readback signal indicates a defect in the Nth level light emitting diode.
4. The light emitting diode driving apparatus according to claim 1, wherein the nth-stage light emitting diode driver comprises:
an equalizer receiving said N-1 data signal and generating an equalized data signal to said clock data recovery circuit;
a first-in first-out circuit receiving the recovered data signal, the recovered clock signal, and a first-in first-out read clock signal to sample the recovered data signal at a clock signal edge of the recovered clock signal to generate a second sampled recovered data signal based on the sampled value of the recovered data signal and the clock signal edge of the first-in first-out read clock signal; and
a reference clock generator generating the first-in first-out read clock signal,
wherein the first transmitter receives the second sampled recovered data signal and outputs the Nth data signal in accordance with the second sampled recovered data signal.
5. The light emitting diode driving apparatus of claim 4, wherein the reference clock generator comprises:
a crystal oscillator generating an input clock signal; and
a phase locked loop circuit receiving the input clock signal to generate the first-in first-out read clock signal according to a second phase difference between the input clock signal and the first-in first-out read clock signal, wherein the phase locked loop circuit includes a frequency divider.
6. The light emitting diode driving apparatus of claim 4, wherein the reference clock generator comprises:
a crystal oscillator generating an input clock signal; and
a delay locked loop circuit receiving the input clock signal to generate the first-in first-out read clock signal according to a third phase difference between the input clock signal and the first-in first-out read clock signal.
7. The light-emitting diode driving apparatus according to claim 1, wherein the clock data recovery circuit comprises:
a phase detector receiving the N-1 th data signal and the recovered clock signal to generate a phase detected signal according to a first phase difference between the N-1 th data signal and the recovered clock signal;
a frequency discriminator receiving the N-1 th data signal and the recovered clock signal to generate a frequency discriminated signal according to a frequency difference between the N-1 th data signal and the recovered clock signal;
a voltage controlled oscillator generating the recovered clock signal according to the phase discrimination signal and the frequency discrimination signal; and
a decision circuit receiving the N-1 th data signal and the recovered clock signal to generate the recovered data signal based on the N-1 th data signal and the recovered clock signal.
8. The light emitting diode driving apparatus of claim 1, wherein the clock data recovery circuit further generates a gray scale control clock signal to control a gray scale of the nth-stage light emitting diode according to the recovered clock signal.
9. The LED driving apparatus according to claim 1, wherein the N-1 th data signal received by the Nth stage LED driver comprises an N-1 th display data signal and an N-1 th clock signal encoded in a first encoding format.
10. The LED driving apparatus according to claim 9, wherein the Nth data signal outputted from the Nth stage LED driver comprises an Nth display data signal and an Nth clock signal encoded in the first encoding format.
11. A light emitting diode driver, comprising:
a clock data recovery circuit receiving the data signal to generate a recovered clock signal and a recovered data signal;
a data memory for storing the recovered data signal; and
a transmitter for outputting a next-stage data signal according to the recovered clock signal and the recovered data signal.
12. The led driver of claim 11, wherein the data memory is a register.
13. The led driver of claim 11, wherein the data memory is a first-in-first-out circuit.
14. The led driver of claim 12, wherein the register receives the recovered data signal and the recovered clock signal to sample the recovered data signal at a clock signal edge of the recovered clock signal to generate a first sampled recovered data signal based on the sampled value of the recovered data signal and the clock signal edge of the recovered clock signal, wherein the transmitter receives the first sampled recovered data signal and outputs the next stage data signal based on the first sampled recovered data signal.
15. The led driver of claim 14, wherein the register receives an error signal and the recovered clock signal to sample the error signal at a clock signal edge of the recovered clock signal to generate a sampled error signal based on the sampled value of the error signal and the clock signal edge of the recovered clock signal, wherein the error signal is from a corresponding led of the led driver.
16. The led driver of claim 15, wherein the transmitter receives the sampled error signal and outputs an error readback signal to a controller based on the sampled error signal, wherein the error readback signal indicates a defect in the led.
17. The led driver of claim 13, wherein the fifo receives the recovered data signal, the recovered clock signal, and a fifo read clock signal to sample the recovered data signal at clock signal edges of the recovered clock signal to generate a second sampled recovered data signal based on sampled values of the recovered data signal and clock signal edges of the fifo read clock signal.
18. The led driver of claim 17, wherein the first-in, first-out readout clock signal is generated by a reference clock generator, wherein the transmitter receives the second sampled recovered data signal and outputs the next stage data signal according to the second sampled recovered data signal.
19. The led driver of claim 18, wherein the reference clock generator comprises:
a crystal oscillator generating an input clock signal; and
a phase locked loop circuit receiving the input clock signal to generate the first-in first-out read clock signal according to a first phase difference between the input clock signal and the first-in first-out read clock signal, wherein the phase locked loop circuit includes a frequency divider.
20. The led driver of claim 18, wherein the reference clock generator comprises:
a crystal oscillator generating an input clock signal; and
a delay locked loop circuit receiving the input clock signal to generate the first-in first-out read clock signal according to a second phase difference between the input clock signal and the first-in first-out read clock signal.
21. The led driver of claim 11, wherein the clock data recovery circuit comprises:
a phase detector receiving a previous-stage data signal and the recovered clock signal to generate a phase-detected signal according to a third phase difference between the previous-stage data signal and the recovered clock signal;
a frequency discriminator receiving the previous-stage data signal and the recovered clock signal to generate a frequency discriminated signal according to a frequency difference between the previous-stage data signal and the recovered clock signal;
a voltage controlled oscillator generating the recovered clock signal according to the phase discrimination signal and the frequency discrimination signal; and
a decision circuit receiving the previous stage data signal and the recovered clock signal to generate the recovered data signal based on the previous stage data signal and the recovered clock signal.
22. The led driver of claim 11, wherein the clock data recovery circuit further generates a gray scale control clock signal to control the gray scale of the corresponding led of the led driver according to the recovered clock signal.
23. The led driver of claim 11, wherein the data signals received by the led driver comprise display data signals and clock signals encoded in a first encoding format.
24. The led driver of claim 23, wherein the next-level data signal output by the led driver comprises a next-level display data signal and a next-level clock signal encoded in the first encoding format.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962885830P | 2019-08-13 | 2019-08-13 | |
| US62/885,830 | 2019-08-13 | ||
| US16/841,686 US20210049952A1 (en) | 2019-08-13 | 2020-04-07 | Light-emitting diode driving apparatus |
| US16/841,686 | 2020-04-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212486838U true CN212486838U (en) | 2021-02-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021672768.0U Withdrawn - After Issue CN212486838U (en) | 2019-08-13 | 2020-08-12 | Light emitting diode driving apparatus and light emitting diode driver |
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| CN (1) | CN212486838U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112399663A (en) * | 2019-08-13 | 2021-02-23 | 联咏科技股份有限公司 | Light emitting diode driving apparatus and light emitting diode driver |
| US11545081B2 (en) | 2019-08-13 | 2023-01-03 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus and light-emitting diode driver |
-
2020
- 2020-08-12 CN CN202021672768.0U patent/CN212486838U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112399663A (en) * | 2019-08-13 | 2021-02-23 | 联咏科技股份有限公司 | Light emitting diode driving apparatus and light emitting diode driver |
| US11545081B2 (en) | 2019-08-13 | 2023-01-03 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus and light-emitting diode driver |
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