CN212484347U - Serial circuit supporting multi-serial communication and data acquisition equipment - Google Patents
Serial circuit supporting multi-serial communication and data acquisition equipment Download PDFInfo
- Publication number
- CN212484347U CN212484347U CN202021542461.9U CN202021542461U CN212484347U CN 212484347 U CN212484347 U CN 212484347U CN 202021542461 U CN202021542461 U CN 202021542461U CN 212484347 U CN212484347 U CN 212484347U
- Authority
- CN
- China
- Prior art keywords
- pin
- chip
- resistor
- capacitor
- serial port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a serial port circuit and data acquisition equipment of supporting multiple serial ports communication, this circuit is including the serial ports output unit who is used for accomplishing RS485 serial ports output function, a serial ports administrative unit for managing the serial ports equipment of connecting, and be used for carrying out data storage's memory cell based on mass storage medium, accessible memory cell carries out long-term storage with a plurality of data acquisition equipment, and manage a plurality of serial ports equipment of connecting through serial ports administrative unit, thereby can support multiple serial ports communication and further improve data processing ability.
Description
Technical Field
The application relates to the technical field of serial communication of electronic equipment, in particular to a serial circuit and data acquisition equipment supporting multi-serial communication.
Background
Serial ports generally refer to serial interfaces, which are devices that convert parallel data characters received from a CPU into a continuous serial data stream and transmit the serial data stream, and convert the received serial data stream into parallel data characters and supply the parallel data characters to the CPU. The circuit that generally accomplishes this function is called a serial circuit.
The existing serial communication circuit is designed to be that one serial port can only be connected with one serial communication device, if a plurality of serial communication devices need to be connected, one device needs to support a plurality of serial interfaces, although the serial port of one part of devices is designed to be a serial port which can be connected with four or more (left or right) serial communication devices, the communication data volume is small, the communication protocol is simple, and the serial communication circuit is difficult to adapt to the serial communication requirement of a data acquisition scene (such as earthquake monitoring) with relatively large data volume.
Therefore, how to provide a serial port circuit capable of supporting multi-serial port communication and further improving data processing capability is a technical problem to be solved at present.
SUMMERY OF THE UTILITY MODEL
Because the serial port circuit in the prior art supports a small number of connected serial port communication devices and has low data processing capacity, the requirement of a data acquisition scene with large data volume cannot be met.
The utility model provides a serial port circuit supporting multi-serial port communication, which comprises a serial port output unit, a serial port management unit and a storage unit, wherein,
the serial port output unit is used for finishing the output function of the RS485 serial port;
the serial port management unit is used for managing the connected serial port equipment;
the storage unit is used for storing data based on a large-capacity storage medium;
the storage unit, the serial port management unit and the serial port output unit are sequentially connected.
In some embodiments of the present application, the serial port circuit further includes:
the serial port protection unit is used for preventing overvoltage signals from entering the serial port output unit and the serial port management unit, and the serial port protection unit is connected with the serial port output unit.
In some embodiments of the present application, the serial output unit further includes a first chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, an inductive filter, a first transient voltage suppression tube, a second transient voltage suppression tube, and a third transient voltage suppression tube, wherein,
the 3-pin and 4-pin of the first chip are connected with the serial port management unit, the common joint point of the 1-pin of the first chip and the first end of the first capacitor is connected with a 3.3V direct current power supply, the common joint point of the 2-pin of the first chip and the second end of the first capacitor is grounded, the 7-pin of the first chip is connected with the first end of the second resistor, the second end of the second resistor is respectively connected with the 9-pin of the first chip and the common joint point of the second end of the first transient voltage suppression tube and the first end of the second transient voltage suppression tube, the common joint point of the 8-pin of the first chip and the first end of the first resistor is connected with the common joint point of the second end of the second transient voltage suppression tube and the first end of the third transient voltage suppression tube, and the second end of the first resistor and the common joint point of the 10-pin of the first chip are connected with the first end of the first transient voltage suppression tube, the first end of the first transient voltage suppression tube and the second end of the third transient voltage suppression tube are both grounded, the common junction point of the first end of the third resistor and the first end of the second capacitor is connected with the first end of the first transient voltage suppression tube, the common junction point of the second end of the third resistor and the second end of the second capacitor is grounded, the first input end and the second input end of the inductive filter are respectively connected with the two ends of the second transient voltage suppression tube, the first output end and the second output end of the inductive filter are respectively connected with the two ends of the fourth resistor, and the two ends of the fourth resistor are further connected with the serial port protection unit.
In some embodiments of the present application, the serial port protection unit further includes a connector, a first discharge tube, a second discharge tube, a fifth resistor, a sixth resistor, a fourth transient voltage suppression tube, and a fifth transient voltage suppression tube, wherein,
a common junction point of the pin 1 of the connector and the pin a of the first discharge tube is connected to one end of the fourth resistor, a common junction point of the pin 2 of the connector and the pin b of the first discharge tube is connected to the other end of the fourth resistor, the pin 3 of the connector is grounded, a common junction point of the pin 4 of the connector and the pin a of the second discharge tube is connected to a first end of the fifth resistor, a second end of the fifth resistor and a common junction point of the first end of the fourth transient voltage suppression tube are connected to +12V dc power, a common junction point of the second end of the fourth transient voltage suppression tube and a first end of the fifth transient voltage suppression tube is connected to the pin 5 of the connector and to common ground, a common junction point of the pin 6 of the connector and the pin b of the second discharge tube is connected to a first end of the sixth resistor, and a second end of the sixth resistor and a common junction point of the second end of the fifth transient voltage suppression tube are connected to-12V dc power, the pin c of the first discharge tube and the pin c of the second discharge tube are both grounded.
In some embodiments of the present application, the serial port management unit further includes a second chip, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a seventh resistor, an eighth resistor, and a ninth resistor, where,
the common junction points of the pin E9, the pin F10 and the pin J10 of the second chip are respectively connected with the first end of the sixth capacitor, the first end of the fifth capacitor, the first end of the fourth capacitor and the first end of the third capacitor and then connected with a 3.3V direct current power supply, the common junction points of the second end of the sixth capacitor, the second end of the fifth capacitor, the second end of the fourth capacitor and the second end of the third capacitor are grounded, the pin F11 of the second chip is BOOT _ MODE0, the pin G14 of the second chip is BOOT _ MODE1, the pin E14 of the second chip is SWDIO, the pin F12 of the second chip is SWCLK, the pin F13 of the second chip is connected with the first end of the seventh resistor, the second end of the seventh resistor is grounded, the pin J6 of the second chip is respectively connected with the first end of the eighth capacitor, the first end of the seventh capacitor and the first end of the eighth resistor, the second end of the eighth resistor is connected with a VDD _ SD power supply, the common junction of the second end of the seventh capacitor and the second end of the eighth capacitor is grounded, a pin K5 of the second chip is respectively connected with the first end of the tenth capacitor, the first end of the ninth capacitor and the 3.3V direct-current power supply, the common junction of the second end of the ninth capacitor and the second end of the tenth capacitor is grounded, a pin J2 of the second chip is connected with a pin 3 of the first chip, a pin K10 of the second chip is connected with a pin 4 of the first chip, a pin J4 of the second chip and the common junction of the first end of the ninth resistor are connected with the storage unit, the second end of the ninth resistor is connected with the VDD _ SD power supply, and pins J3, J1, K1, H2, J2 and D13 of the second chip are respectively connected with the storage unit.
In some embodiments of the present application, the memory cell further includes a third chip, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a transistor, wherein,
the common junction of the G1 pin, the G2 pin, the G3 pin and the G4 pin of the third chip is grounded, the 1 pin of the third chip is connected with the H2 pin of the second chip, the 2 pin of the third chip is connected with the J2 pin of the second chip, the 3 pin of the third chip is connected with the J4 pin of the second chip, the 4 pin of the third chip is connected with a 3.3V direct current power supply and is respectively connected with the first end of the eleventh capacitor, the first end of the twelfth capacitor and the first end of the thirteenth capacitor, the common junction of the second end of the eleventh capacitor, the second end of the twelfth capacitor and the second end of the thirteenth capacitor is grounded, the 5 pin of the third chip is connected with the first end of the tenth resistor, the second end of the tenth resistor is connected with the J3 pin of the second chip, the 6 pin of the third chip is grounded, the 7 pin of the third chip is connected with the J1 pin of the second chip, the pin 8 of the third chip is connected with the pin K1 of the second chip, the common junction of the pin 9 of the third chip and the first end of the eleventh resistor is connected with the base electrode of the triode, the second end of the eleventh resistor is connected with a 3.3V direct-current power supply, the common junction of the collector electrode of the triode and the first end of the twelfth resistor is connected with the first end of the thirteenth resistor, the second end of the twelfth resistor is connected with the 3.3V direct-current power supply, the second end of the thirteenth resistor is connected with the pin D13 of the second chip, and the emitting electrode of the triode is grounded.
In some embodiments of the present application, the first chip specifically includes any one of RSM3485, RSM485CHT, RSM3485CHT, RSM485ECHT, RSM3485ECHT, RSM485CT, RSM3485CT, RSM485PCHT, RSM3485PCHT, RSM485PHT, and RSM3485 PHT.
In some embodiments of the present application, the mass storage medium is specifically any one of a MicroSD memory card, an SD memory card, and a miniSD memory card.
In some embodiments of the present application, a serial communication protocol of the circuit has a device number identification function and supports connection of a plurality of serial devices.
Correspondingly, the utility model also provides a data acquisition equipment, include as above the serial circuits who supports multi-serial communication.
Through using above technical scheme, serial port circuit that supports multiple serial communication is including the serial ports output unit that is used for accomplishing RS485 serial ports output function, a serial ports administrative unit for managing the serial ports equipment of connecting, and be used for carrying out data storage's memory cell based on large capacity storage medium, accessible memory cell carries out long-term storage with a plurality of collection equipment's data, and manage a plurality of serial ports equipment of connecting through serial ports administrative unit, still prevent that the overvoltage from causing the damage to the circuit through serial ports protection element, thereby can support multiple serial communication and further improve data processing ability and reliability.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 shows a schematic structural diagram of a serial port circuit supporting multiple serial port communication according to an embodiment of the present application;
fig. 2 shows a schematic structural diagram of a serial port output unit in the embodiment of the present application;
fig. 3 shows a schematic structural diagram of a serial port protection unit in an embodiment of the present application;
fig. 4 shows a schematic structural diagram of a serial port management unit in an embodiment of the present application;
FIG. 5 is a schematic structural diagram of a memory cell in the embodiment of the present application;
fig. 6 is a schematic diagram illustrating a principle that a management node device is connected to multiple serial devices in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
As described in the background art, the serial port circuit in the prior art supports a small number of connected serial port communication devices, and has a low data processing amount, which cannot meet the requirements of a data acquisition scenario with a large data volume.
In order to solve the above problem, an embodiment of the present application provides a serial port circuit supporting multi-serial port communication, including a serial port output unit for completing an RS485 serial port output function, a serial port management unit for managing connected serial port devices, and a storage unit for performing data storage based on a large-capacity storage medium, store data of a plurality of acquisition devices through the storage unit, and manage the connected serial port devices through the serial port management unit, thereby supporting multi-serial port communication and further improving data processing capability.
As shown in fig. 1, the serial port circuit includes a serial port output unit, a serial port management unit and a storage unit, wherein,
the serial port output unit is used for finishing the output function of the RS485 serial port;
the serial port management unit is used for managing the connected serial port equipment;
the storage unit is used for storing data based on a large-capacity storage medium;
the storage unit, the serial port management unit and the serial port output unit are sequentially connected.
In order to prevent the serial port circuit from being damaged by overvoltage, in a preferred embodiment of the present application, the serial port circuit further includes:
the serial port protection unit is used for preventing overvoltage signals from entering the serial port output unit and the serial port management unit, and the serial port protection unit is connected with the serial port output unit.
In order to ensure reliable completion of the RS485 serial output function, in a preferred embodiment of the present application, as shown in fig. 2, the serial output unit further includes a first chip U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, an inductive filter L1, a first transient voltage suppression tube D1, a second transient voltage suppression tube D2, and a third transient voltage suppression tube D3, wherein,
the 3 pin and the 4 pin of the first chip U1 are connected to the serial port management unit, wherein the 3 pin of U1 is a TXD interface, the 4 pin of U1 is an RXD interface, the common junction of the 1 pin of the first chip U1 and the first end of the first capacitor C1 is connected to a 3.3V dc power supply, the common junction of the 2 pin of the first chip U1 and the second end of the first capacitor C1 is grounded, the 7 pin of the first chip U1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the 9 pin of the first chip U1 and the common junction of the second end of the first transient voltage suppression tube D1 and the first end of the second transient voltage suppression tube D2, respectively, the common junction of the 8 pin of the first chip U1 and the first end of the first resistor R1 is connected to the second end of the second transient voltage suppression tube D2 and the second end of the third transient voltage suppression tube D3, the second end of the first resistor R1 and the common point of the 10 pins of the first chip U1 are connected to the first end of the first transient voltage suppression tube D1, a first end of the first transient voltage suppression tube D1 and a second end of the third transient voltage suppression tube D3 are both grounded, a common junction point of the first terminal of the third resistor R3 and the first terminal of the second capacitor C2 is connected to the first terminal of the first transient voltage suppression tube D1, the common node between the second terminal of the third resistor R3 and the second terminal of the second capacitor C2 is grounded, the first input terminal 1 and the second input terminal 2 of the inductive filter L1 are respectively connected to two ends of the second transient voltage suppression tube D2, the first output end 3 and the second output end 4 of the inductive filter L1 are respectively connected to two ends of the fourth resistor R4, and two ends of the fourth resistor R4 are further connected to the serial port protection unit.
In order to improve the compatibility of the serial port circuit, in a preferred embodiment of the present application, the first chip U1 specifically includes any one of RSM3485, RSM485CHT, RSM3485CHT, RSM485ECHT, RSM3485ECHT, RSM485CT, RSM3485CT, RSM485PCHT, RSM3485PCHT, RSM485PHT, and RSM3485 PHT.
In order to reliably prevent the overvoltage from damaging the circuit, in the preferred embodiment of the present application, as shown in fig. 3, the serial port protection unit further includes a connector J1, a first discharge tube G1, a second discharge tube G2, a fifth resistor R5, a sixth resistor R6, a fourth transient voltage suppression tube D4, and a fifth transient voltage suppression tube D5, wherein,
a common junction point of the pin 1 of the connector J1 and the pin a of the first discharge tube G1 is connected to one end of the fourth resistor R4, a common junction point of the pin 2 of the connector J1 and the pin b of the first discharge tube G1 is connected to the other end of the fourth resistor R4, the pin 3 of the connector J1 is grounded, a common junction point of the pin 4 of the connector J1 and the pin a of the second discharge tube G2 is connected to a first end of the fifth resistor R5, a common junction point of the second end of the fifth resistor R5 and a first end of the fourth transient voltage suppression tube D4 is connected to a +12V dc power supply, a common junction point of the second end of the fourth transient voltage suppression tube D4 and a first end of the fifth transient voltage suppression tube D5 is connected to a pin 5 of the connector J1 and to a common ground comal, a common junction point of the pin 6 of the connector J1 and the pin b of the second discharge tube G2 is connected to a first end of the sixth resistor R6, the common junction of the second terminal of the sixth resistor R6 and the second terminal of the fifth transient voltage suppressor D5 is connected to a-12V dc power supply, and the pin c of the first discharge tube G1 and the pin c of the second discharge tube G2 are both grounded.
In order to reliably manage the connected serial devices, in a preferred embodiment of the present application, as shown in fig. 4, the serial management unit further includes a second chip U2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9, wherein,
common junctions of a pin E9, a pin F10 and a pin J10 of the second chip U2 are respectively connected to a first end of the sixth capacitor C6, a first end of the fifth capacitor C5, a first end of the fourth capacitor C4 and a first end of the third capacitor C4, and then connected to a 3.3V dc power supply, common junctions of a second end of the sixth capacitor C4, a second end of the fifth capacitor C4, a second end of the fourth capacitor C4 and a second end of the third capacitor C4 are grounded, a pin F4 of the second chip U4 is a pin bot _ MODE 4, a pin G4 of the second chip U4 is a pin SWDIO, a pin F4 of the second chip U4 is SWCLK, a pin F4 of the second chip U4 is connected to a resistor R at a first end of the second chip U4, a pin F4 of the second chip U4 is connected to a resistor R at a second end of the seventh capacitor C4, and a resistor R4 are respectively connected to the ground, a second terminal of the eighth resistor R8 is connected to a VDD _ SD power source, a common node between a second terminal of the seventh capacitor C7 and a second terminal of the eighth capacitor C8 is grounded, the pin K5 of the second chip U2 is respectively connected with the first end of the tenth capacitor C10, the first end of the ninth capacitor C9 and a 3.3V direct current power supply, the common node of the second terminal of the ninth capacitor C9 and the second terminal of the tenth capacitor C10 is grounded, the pin J2 of the second chip U2 is connected with the pin 3 of the first chip, the pin K10 of the second chip U2 is connected with the pin 4 of the first chip, the common joint of the pin J4 of the second chip U2 and the first end of the ninth resistor R9 is connected with the memory cell, the second end of the ninth resistor R9 is connected with a VDD _ SD power supply, and the pins J3, J1, K1, H2, J2 and D13 of the second chip U2 are respectively connected with the memory cells.
In order to reliably process a large amount of collected data, in a preferred embodiment of the present application, as shown in fig. 5, the memory unit further includes a third chip U3, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a transistor Q1, wherein,
the common junction of the pin G1, the pin G2, the pin G3 and the pin G4 of the third chip U3 is grounded, the pin 1 of the third chip U3 is connected to the pin H2 of the second chip U2, the pin 2 of the third chip U3 is connected to the pin J2 of the second chip U2, the pin 3 of the third chip U3 is connected to the pin J4 of the second chip U2, the pin 4 of the third chip U3 is connected to a 3.3V dc power supply and is respectively connected to the first end of the eleventh capacitor C11, the first end of the twelfth capacitor C12 and the first end of the thirteenth capacitor C13, the second end of the eleventh capacitor C11, the second end of the twelfth capacitor C11 and the second end of the thirteenth capacitor C11 are grounded, the pin 5 of the third chip U11 is connected to the first end of the tenth resistor R11, the second end of the second resistor R11 is connected to the pin J366 of the third chip U11, the pin 11 is grounded, a pin 7 of the third chip U3 is connected to a pin J1 of the second chip U2, a pin 8 of the third chip U3 is connected to a pin K1 of the second chip U2, a common junction of a pin 9 of the third chip U3 and a first end of the eleventh resistor R11 is connected to a base of the transistor Q1, a second end of the eleventh resistor R11 is connected to a 3.3V dc power supply, a common junction of a collector of the transistor Q1 and a first end of the twelfth resistor R12 is connected to a first end of the thirteenth resistor R13, a second end of the twelfth resistor R12 is connected to a 3.3V dc power supply, a second end of the thirteenth resistor R13 is connected to a pin D13 of the second chip U2, and an emitter of the transistor Q1 is grounded.
In order to improve the compatibility of the storage unit, in a preferred embodiment of the present application, the mass storage medium is specifically any one of a MicroSD memory card, an SD memory card, and a miniSD memory card, and a person skilled in the art may flexibly select different memory card capacities, such as 16GB, 32GB, 64GB, 128GB, 256GB, and the like.
In order to enable the serial port circuit to reliably support multi-serial port communication, in a preferred embodiment of the application, a serial port communication protocol of the circuit has a device number identification function and supports connection of a plurality of serial port devices.
Through using above technical scheme, serial port circuit that supports multiple serial communication is including the serial ports output unit that is used for accomplishing RS485 serial ports output function, a serial ports administrative unit for managing the serial ports equipment of connecting, and be used for carrying out data storage's memory cell based on large capacity storage medium, accessible memory cell carries out long-term storage with a plurality of collection equipment's data, and manage a plurality of serial ports equipment of connecting through serial ports administrative unit, still prevent that the overvoltage from causing the damage to the circuit through serial ports protection element, thereby can support multiple serial communication and further improve data processing ability and reliability.
As shown in figure 6 be the principle schematic diagram that a plurality of serial port equipment are connected to management node equipment in this application embodiment, management node equipment is equivalent to promptly the embodiment of the utility model provides an in serial port management unit, other serial port equipment all are connected to on the 485 serial ports of management node equipment through serial port cable and serial ports adapter, can support to connect 8 RS485 serial port equipment at most and carry out reliable data communication in step, wherein highest communication rate is 115200bps, the three channel data parallel collection of a serial port communication equipment (electromagnetic wave sensor) that connects, every channel data is the floating point number, highest sampling rate can reach 150Hz, the data transmission that has realized high sampling rate receives and equipment management function.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (9)
1. A serial port circuit supporting multi-serial port communication is characterized by comprising a serial port output unit, a serial port management unit and a storage unit, wherein,
the serial port output unit is used for finishing the output function of the RS485 serial port;
the serial port management unit is used for managing the connected serial port equipment;
the storage unit is used for storing data based on a large-capacity storage medium;
the storage unit, the serial port management unit and the serial port output unit are sequentially connected.
2. The circuit of claim 1, wherein the serial circuit further comprises:
the serial port protection unit is used for preventing overvoltage signals from entering the serial port output unit and the serial port management unit, and the serial port protection unit is connected with the serial port output unit.
3. The circuit of claim 2, wherein the serial output unit further comprises a first chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, an inductive filter, a first transient voltage suppression tube, a second transient voltage suppression tube, and a third transient voltage suppression tube, wherein,
the first chip is specifically any one of the chips including RSM3485, RSM485CHT, RSM3485CHT, RSM485ECHT, RSM3485ECHT, RSM485CT, RSM3485CT, RSM485PCHT, RSM3485PCHT, RSM485PHT, and RSM3485PHT, the 3 and 4 pins of the first chip are connected to the serial port management unit, the common junction of the 1 pin of the first chip and the first end of the first capacitor is connected to a 3.3V dc power supply, the common junction of the 2 pin of the first chip and the second end of the first capacitor is grounded, the 7 pin of the first chip is connected to the first end of the second resistor, the second end of the second resistor is respectively connected to the 9 pins of the second chip and the common junction of the second end of the first transient voltage suppression chip and the first end of the second transient voltage suppression tube, and the second end of the transient voltage suppression tube are connected to the common junction of the second end of the transient voltage suppression tube, the second end of the first resistor is connected with a common junction point of 10 pins of the first chip, the first end of the first transient voltage suppression tube and the second end of the third transient voltage suppression tube are both grounded, the first end of the third resistor and the common junction point of the first end of the second capacitor are connected with the first end of the first transient voltage suppression tube, the second end of the third resistor and the common junction point of the second end of the second capacitor are both grounded, the first input end and the second input end of the inductive filter are respectively connected with two ends of the second transient voltage suppression tube, the first output end and the second output end of the inductive filter are respectively connected with two ends of the fourth resistor, and two ends of the fourth resistor are also connected with the serial port protection unit.
4. The circuit of claim 3, wherein the serial port protection unit further comprises a connector, a first discharge tube, a second discharge tube, a fifth resistor, a sixth resistor, a fourth transient voltage suppression tube, and a fifth transient voltage suppression tube, wherein,
a common junction point of the pin 1 of the connector and the pin a of the first discharge tube is connected to one end of the fourth resistor, a common junction point of the pin 2 of the connector and the pin b of the first discharge tube is connected to the other end of the fourth resistor, the pin 3 of the connector is grounded, a common junction point of the pin 4 of the connector and the pin a of the second discharge tube is connected to a first end of the fifth resistor, a second end of the fifth resistor and a common junction point of the first end of the fourth transient voltage suppression tube are connected to +12V dc power, a common junction point of the second end of the fourth transient voltage suppression tube and a first end of the fifth transient voltage suppression tube is connected to the pin 5 of the connector and to common ground, a common junction point of the pin 6 of the connector and the pin b of the second discharge tube is connected to a first end of the sixth resistor, and a second end of the sixth resistor and a common junction point of the second end of the fifth transient voltage suppression tube are connected to-12V dc power, the pin c of the first discharge tube and the pin c of the second discharge tube are both grounded.
5. The circuit of claim 3, wherein the serial port management unit further comprises a second chip, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a seventh resistor, an eighth resistor, and a ninth resistor, wherein,
the common junction points of the pin E9, the pin F10 and the pin J10 of the second chip are respectively connected with the first end of the sixth capacitor, the first end of the fifth capacitor, the first end of the fourth capacitor and the first end of the third capacitor and then connected with a 3.3V direct current power supply, the common junction points of the second end of the sixth capacitor, the second end of the fifth capacitor, the second end of the fourth capacitor and the second end of the third capacitor are grounded, the pin F11 of the second chip is BOOT _ MODE0, the pin G14 of the second chip is BOOT _ MODE1, the pin E14 of the second chip is SWDIO, the pin F12 of the second chip is SWCLK, the pin F13 of the second chip is connected with the first end of the seventh resistor, the second end of the seventh resistor is grounded, the pin J6 of the second chip is respectively connected with the first end of the eighth capacitor, the first end of the seventh capacitor and the first end of the eighth resistor, the second end of the eighth resistor is connected with a VDD _ SD power supply, the common junction of the second end of the seventh capacitor and the second end of the eighth capacitor is grounded, a pin K5 of the second chip is respectively connected with the first end of the tenth capacitor, the first end of the ninth capacitor and the 3.3V direct-current power supply, the common junction of the second end of the ninth capacitor and the second end of the tenth capacitor is grounded, a pin J2 of the second chip is connected with a pin 3 of the first chip, a pin K10 of the second chip is connected with a pin 4 of the first chip, a pin J4 of the second chip and the common junction of the first end of the ninth resistor are connected with the storage unit, the second end of the ninth resistor is connected with the VDD _ SD power supply, and pins J3, J1, K1, H2, J2 and D13 of the second chip are respectively connected with the storage unit.
6. The circuit of claim 5, wherein the memory cell further comprises a third chip, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a transistor, wherein,
the common junction of the G1 pin, the G2 pin, the G3 pin and the G4 pin of the third chip is grounded, the 1 pin of the third chip is connected with the H2 pin of the second chip, the 2 pin of the third chip is connected with the J2 pin of the second chip, the 3 pin of the third chip is connected with the J4 pin of the second chip, the 4 pin of the third chip is connected with a 3.3V direct current power supply and is respectively connected with the first end of the eleventh capacitor, the first end of the twelfth capacitor and the first end of the thirteenth capacitor, the common junction of the second end of the eleventh capacitor, the second end of the twelfth capacitor and the second end of the thirteenth capacitor is grounded, the 5 pin of the third chip is connected with the first end of the tenth resistor, the second end of the tenth resistor is connected with the J3 pin of the second chip, the 6 pin of the third chip is grounded, the 7 pin of the third chip is connected with the J1 pin of the second chip, the pin 8 of the third chip is connected with the pin K1 of the second chip, the common junction of the pin 9 of the third chip and the first end of the eleventh resistor is connected with the base electrode of the triode, the second end of the eleventh resistor is connected with a 3.3V direct-current power supply, the common junction of the collector electrode of the triode and the first end of the twelfth resistor is connected with the first end of the thirteenth resistor, the second end of the twelfth resistor is connected with the 3.3V direct-current power supply, the second end of the thirteenth resistor is connected with the pin D13 of the second chip, and the emitting electrode of the triode is grounded.
7. The circuit according to claim 1, wherein the mass storage medium is any one of a MicroSD memory card, an SD memory card, and a miniSD memory card.
8. The circuit of claim 1, wherein a serial communication protocol of the circuit has a device number identification function and supports connection of a plurality of serial devices.
9. A data acquisition device comprising a serial circuit supporting multiple serial communication according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021542461.9U CN212484347U (en) | 2020-07-30 | 2020-07-30 | Serial circuit supporting multi-serial communication and data acquisition equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021542461.9U CN212484347U (en) | 2020-07-30 | 2020-07-30 | Serial circuit supporting multi-serial communication and data acquisition equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212484347U true CN212484347U (en) | 2021-02-05 |
Family
ID=74453083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021542461.9U Active CN212484347U (en) | 2020-07-30 | 2020-07-30 | Serial circuit supporting multi-serial communication and data acquisition equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212484347U (en) |
-
2020
- 2020-07-30 CN CN202021542461.9U patent/CN212484347U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103856411B (en) | Switching system connected with UART interface of router | |
| CN212484347U (en) | Serial circuit supporting multi-serial communication and data acquisition equipment | |
| CN201860011U (en) | All-in-one connector | |
| CN111930654A (en) | Serial circuit supporting multi-serial communication and data acquisition equipment | |
| CN213906954U (en) | Edge computing Internet of things gateway | |
| CN208969651U (en) | Drive circuit board and programming system | |
| CN2847703Y (en) | Light receiving and transmitting integrated module | |
| CN201118597Y (en) | Electrical signal loop circuit and optical receiving/transmission module with this loop | |
| CN213934872U (en) | Serial port-to-FDCAN bus conversion recording device | |
| CN206133916U (en) | Electricity utilization information collector | |
| CN211554931U (en) | Embedded collector | |
| CN213152089U (en) | Comprehensive gateway device supporting High Performance Liquid Chromatography (HPLC) communication | |
| CN211207480U (en) | NB-IoT meter reading gateway equipment | |
| CN210605518U (en) | Integrated intelligent controller | |
| CN206620223U (en) | A kind of intelligent video monitoring data exchange system | |
| CN214591998U (en) | 5G module with MINI-PCIE interface | |
| CN208283939U (en) | A kind of data monitoring and record concentrator | |
| CN210983393U (en) | System for realizing self management of functional module through single-wire protocol | |
| CN214480590U (en) | Combined NB-IOT communication module | |
| CN110134620A (en) | A kind of multichannel USB connection equipment and its data control method | |
| CN217718677U (en) | GPI control system based on PCIE interface | |
| CN219419148U (en) | BMS integrated function gyroscope | |
| CN210166928U (en) | Full-function wireless data acquisition unit supporting multiple protocols | |
| CN220934883U (en) | Energy storage battery self-diagnosis control circuit and energy storage battery | |
| CN211829456U (en) | Remote communication module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |