CN212484339U - Chip data writing and testing device - Google Patents
Chip data writing and testing device Download PDFInfo
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- CN212484339U CN212484339U CN202021190946.6U CN202021190946U CN212484339U CN 212484339 U CN212484339 U CN 212484339U CN 202021190946 U CN202021190946 U CN 202021190946U CN 212484339 U CN212484339 U CN 212484339U
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Abstract
The utility model provides a chip data writing and testing device, which comprises a main controller, wherein the main controller is electrically connected with a display device and a first adapter; the master controller is also electrically connected with at least one slave controller and receives signals output by the slave controllers, and each slave controller is electrically connected with the second adapter; the master controller and the slave controller are both connected to the input selection device. The utility model discloses can carry out data write in or test to a plurality of chips simultaneously to main control unit can operate same set of procedure with following the controller, and chip data write in and testing arrangement's development cost is lower.
Description
Technical Field
The utility model relates to a chip data processing field, it is specific relates to a chip data is write in and testing arrangement.
Background
The electronic imaging equipment is taken as common office equipment, great convenience is provided for modern office, the common electronic imaging equipment comprises a printer, a copying machine and the like, the existing printer is divided into an ink-jet printer and a laser printer, and the ink-jet printer uses an ink box containing ink as an ink box to jet the ink to paper so as to form characters or patterns to be printed on the paper; the laser printer uses a toner cartridge containing toner as an ink cartridge to form characters or patterns to be printed on a medium.
The existing ink-jet printer is provided with a shell, a machine core of the ink-jet printer is arranged in the shell, a sliding rod is arranged in the shell, and a print carriage reciprocates along the sliding rod under the driving of a motor. A plurality of ink boxes are detachably mounted on the printing carriage, each ink box is provided with a box body, a cavity for containing ink is enclosed by the box bodies, an ink outlet is formed in the lower end of the cavity, and the ink in the cavity flows out through the ink outlet and supplies ink to an ink supply needle of the printing carriage.
A chip is installed on the outer wall of the box body of the ink box and provided with a base plate, and a plurality of connecting terminals are arranged on one side of the base plate and used for being electrically connected with the adapter plate. The other side of the substrate is provided with a memory, typically a nonvolatile memory such as an EEPROM or a FLASH, which stores information related to the ink cartridge, including variable information and invariable information, the variable information being information that is constantly changeable with the printing operation, such as the remaining amount of ink, the printing duration, the number of printed paper, and the invariable information being information that is not changeable with the printing operation, such as the type of the ink cartridge, the type of an applicable inkjet printer, the color of ink, and the like.
Since the ink cartridge chip needs to store information related to the ink cartridge in advance, corresponding data needs to be written to the ink cartridge chip when the ink cartridge chip is produced, and the written data needs to be tested to ensure that the written data is correct. At present, data writing and testing of printing consumable chips such as ink cartridge chips are generally realized by using a single chip microcomputer or a Micro Control Unit (MCU) as a control device, and the device is called a chip data writing and testing device.
Referring to fig. 1, the conventional chip data writing and testing apparatus includes a main controller 10 and an input keyboard 12, and the input keyboard 12 sends a signal to the main controller 10 for selecting a data type written to the chip. The chip data writing and testing device is further provided with a display device 11, the display device 11 is an LCD screen, the main controller 10 is further connected with one or more adapters, such as an adapter 13 and an adapter 14, and the adapter can be a connector or a contact pin connected with the ink cartridge chip. Further, the main controller 10 may be further connected to a light emitting diode, and the light emitting diode is controlled to emit light or to be turned off to indicate whether the main controller successfully writes data into the chip.
Typically, host controller 10 has multiple sets of IO interfaces, each set of IO interfaces being connectable to one adapter, and each adapter being connectable to one chip. For example, the main controller 10 has a first group of IO interfaces PA 5-PA 9 connected to the adapter 13 and a second group of IO interfaces PB 5-PB 9 connected to the adapter 14. Because the instructions of the main controller 10 are executed sequentially, when the chip data writing and testing device works, the IO interfaces of each group cannot work simultaneously, but work sequentially. For example, the first group of IO interfaces is driven to operate first, and after the adaptor 13 finishes writing data to the first chip, the second group of IO interfaces is driven and the instruction is executed. Therefore, the plurality of adapters work in series, parallel work cannot be realized, and if data needs to be written into the plurality of chips, the data writing efficiency is very low.
In order to synchronously write data into a plurality of chips, one solution is to use a plurality of chip data writing and testing devices to work, i.e. a main controller of the plurality of chip data writing and testing devices operates independently, but needs to occupy more space and greatly increases the cost of chip data writing.
The other solution is to provide a plurality of controllers, including a master controller and a plurality of slave controllers, wherein the master controller controls the work of the plurality of slave controllers, the master controller obtains the work states of the plurality of slave controllers and the signals of the work results, and the display device displays the work results of the controllers. However, the programs run by the master controller and the slave controller in the scheme are obviously different, one chip data writing and testing device at least needs two different programs, which brings difficulty to the work of writing and testing the chip data, for example, the development, debugging, maintenance and upgrading of the chip data writing and testing device are very complicated, and the development of the programs is easy to make mistakes.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a low and chip data write in and testing arrangement that can write in data to a plurality of chips simultaneously of development cost.
In order to realize the main purpose of the utility model, the chip data writing and testing device provided by the utility model comprises a main controller, wherein the main controller is electrically connected with a display device and a first adapter; the master controller is also electrically connected with at least one slave controller and receives signals output by the slave controllers, and each slave controller is electrically connected with the second adapter; the master controller and the slave controller are both connected to the input selection device.
It can be seen from the above solution that the master controller and the slave controller are both connected to the same input selection device, so that the master controller and the slave controller receive signals from the input selection device to perform corresponding operations, such as writing data to the chip through the corresponding adapter. Thus, the programs executed by the master controller and the slave controller are the same, and two different programs do not need to be developed on the master controller, so that the development cost of the chip data writing and testing device is reduced.
In addition, the master controller and the slave controller operate independently, so that data can be written into a plurality of chips at the same time, and the data writing efficiency is high.
Preferably, the master controller is of the same type as the slave controller. Therefore, the programs run by the master controller and the slave controller are completely the same, the master controller and the slave controller can synchronously execute data writing or test operation, and the data processing synchronism of the master controller and the slave controller is good.
The main controller is electrically connected with the first indicating circuit, and each of the sub-controllers is electrically connected with the second indicating circuit.
Therefore, through the first indicating circuit and the second indicating circuit, an operator can know the data writing progress or the data writing result condition of the master controller and the slave controller more intuitively.
The further scheme is that the slave controller outputs a working result signal to the master controller; the main controller outputs the working result signal to the display device.
Therefore, the main controller can receive the working result signals of the slave controllers, the main controller can transmit the received working result signals to the display device, the display device can display the working results of the main controller and the slave controllers, and the data writing condition of the slave display device or each chip can be conveniently visualized by an operator.
Preferably, the input selection device is an input keyboard, and the input keyboard has at least two model selection keys.
Therefore, an operator can select the data model written into the chip or the model of the chip to be written with data through the selection keys on the input keyboard, and the data writing and testing operations are very simple.
Further, the model of the first adapter is the same as the model of the second adapter. Therefore, the main controller and the slave controller have the same model, and the first adapter and the second adapter have the same model, so that the data writing speed of each chip for writing data at the same time can be ensured to be the same, and the data writing or testing efficiency is improved.
Drawings
Fig. 1 is an electrical schematic block diagram of a conventional chip data writing and testing apparatus.
Fig. 2 is an electrical schematic block diagram of an embodiment of the invention.
Fig. 3 is an electrical schematic diagram of an embodiment of the present invention.
The present invention will be further explained with reference to the drawings and examples.
Detailed Description
The utility model discloses a chip data is write in and testing arrangement mainly used carries out the work that data were write in and were tested to printing consumptive material chip, and printing consumptive material chip can be the ink horn chip of installing on the ink horn, also can be the processing box chip of installing on the processing box. Regardless of the ink cartridge chip or the processing cartridge chip, the printing consumable chip needs to write data related to the printing consumable, such as the type of the printing device used by the printing consumable, the initial allowance of the printing consumable, the color of the printing consumable, and the like, before leaving the factory. After writing data, the written data needs to be verified, for example, a test operation is performed to ensure that the written data is correct data.
The chip data writing and testing device can write data into a plurality of chips or test the chips at the same time, so that the data writing or testing efficiency is improved. Referring to fig. 2, the present embodiment has a master controller 20 and two slave controllers 21 and 22, and the two slave controllers 21 and 22 are electrically connected to the master controller 20. However, the master controller 20 does not send an instruction to the two slave controllers 21 and 22, that is, the master controller 20 does not control the operations of the two slave controllers 21 and 22. In the present embodiment, the programs run by the master controller 20 and the slave controllers 21 and 22 are completely the same, and only the connection positions of the master controller 20 and the slave controllers 21 and 22 are different.
As can be seen from fig. 2, the master controller 20 is electrically connected to the display device 25, but the two slave controllers 21 and 22 are not electrically connected to the display device 25, and therefore, the two slave controllers 21 and 22 do not output signals to the display device 25. The display device 25 may be an LCD screen for receiving the signal transmitted from the master controller 20 and displaying the operation results of the master controller 20, the slave controller 21 and the slave controller 22 according to the display transmitted from the master controller 20.
The chip data write and test device is provided with an input keyboard 26 as an input selection device, and the input keyboard 26 outputs signals to the master controller 20 and the two slave controllers 21 and 22, respectively. Preferably, the input keyboard 26 has four keys, including two model selection keys, i.e., "model +" and "model-" keys, and when the operator presses the "model +" key once, the selected data model is increased by 1 unit, and when the operator presses the "model-" key once, the selected data model is decreased by 1 unit. In addition, the input keyboard 26 is provided with two keys of "back" and "confirm".
The master controller 20 is electrically connected to an adapter 30 as a first adapter, the slave controller 21 is electrically connected to the adapter 21, the slave controller 22 is electrically connected to the adapter 22, and the adapter 21 and the adapter 22 are second adapters. It can be seen that each controller is electrically connected to an adapter, i.e. each controller is able to write data to the chip via the matching adapter. Since the present embodiment is provided with one master controller 20 and two slave controllers 21 and 22, three adapters are provided, and each adapter can write data to one chip or perform data test.
In order to facilitate the operator to know the data writing state or the test state of each chip, each controller is electrically connected to an indication circuit, for example, the master controller 20 is electrically connected to the indication circuit 35, the slave controller 21 is electrically connected to the indication circuit 36, and the slave controller 22 is electrically connected to the indication circuit 37. Preferably, each of the indicating circuits is a light emitting diode, and whether the data is written successfully or unsuccessfully is indicated by lighting or extinguishing of the light emitting diode.
Referring to fig. 3, the master controller 20 is a single chip U0, the slave controller 21 is a single chip U1, the slave controller 22 is a single chip U2, and three pins PD0, PD1 and PD2 of the single chip U0 are connected to the display device 25 and used for transmitting signals to the display device 25. The singlechip chips U1 and U2 are not connected to the display device 25, that is, the controllers 21 and 22 do not output signals to the display device 25, so the pins PD0, PD1 and PD2 of the singlechip chips U1 and U2 are suspended, or the three pins are all grounded. Preferably, the master controller 20 is the same as the slave controllers 21 and 22 in model, that is, the single chip microcomputer chips U0, U1 and U2 are completely the same in model.
Each single chip is electrically connected with a corresponding adapter through five pins, for example, pins PB5 to PB9 of the single chip U0 are connected to the adapter 30, pins PB5 to PB9 of the single chip U1 are connected to the adapter 31, and pins PB5 to PB9 of the single chip U2 are connected to the adapter 32, so that each single chip can write data to the chip through the corresponding adapter. Preferably, the adapters are of the same type, which facilitates operation on the controllers by developing the same set of programs, and facilitates operation of the adapters driven by the controllers.
In addition, four pins of each one-chip microcomputer chip are connected to the input keyboard 26, for example, pins PA1 to PA4 of the one-chip microcomputer chip U0 are connected to the input keyboard 26, pins PA1 to PA4 of the one-chip microcomputer chip U1 are connected to the input keyboard 26, pins PA1 to PA4 of the one-chip microcomputer chip U2 are connected to the input keyboard 26, and pins PA1 to PA4 of each one-chip microcomputer chip receive signals of four keys, respectively. Thus, when an operator presses any one of the keys of the input keyboard 26, the three one-chip microcomputer chips all receive a signal that the key is pressed at the same time, and therefore, the three one-chip microcomputer chips receive the same operation signal at the same time.
Each one of the monolithic chips is connected with a light emitting diode, for example, pin PC0 of monolithic chip U0 is connected with the anode terminal of light emitting diode D0, the cathode terminal of light emitting diode D0 is grounded, similarly, pin PC0 of monolithic chip U1 is connected with the anode terminal of light emitting diode D1, the cathode terminal of light emitting diode D1 is grounded, pin PC0 of monolithic chip U2 is connected with the anode terminal of light emitting diode D2, and the cathode terminal of light emitting diode D2 is grounded. After each single chip successfully writes data into the corresponding chip, the pin PC0 is set to be at a high level, the light emitting diode emits light, and an operator can judge that the data of the chip is successfully written through the light emission of the light emitting diode.
In addition, pin PC1 of the one-chip microcomputer U0 is also connected to pin PC0 of the one-chip microcomputer U1, and pin PC2 of the one-chip microcomputer U0 is also connected to pin PC0 of the one-chip microcomputer U2, so that when the level of pin PC0 is set to high by the one-chip microcomputer U1, pin PC1 of the one-chip microcomputer U0 will receive a high signal, and when the level of pin PC0 is set to high by the one-chip microcomputer U2, pin PC2 of the one-chip microcomputer U0 will receive a high signal. As can be seen, the single chip microcomputer U0 can receive two signals of successful input and write output from the controllers 21 and 22 through the pins PC1 and PC2, so as to obtain two signals of work results of the controllers 21 and 22.
The single chip U0 outputs signals to the display device 25 according to the level signals of the pins PC0, PC1, and PC2, and the display device 25 can display the working result information of each single chip, so that the operator can know the writing state or the test state of each chip data.
Because the singlechip chips U1 and U2 do not need to output signals to other singlechip chips, pins PC1 and PC2 of the singlechip chips U1 and U2 are all suspended or grounded.
When the chip data writing and testing device writes data into a plurality of chips, after the chips to be written with the data are connected with the adapter, an operator selects the data model written into each chip through an input keyboard, and after the master controller 20 and the slave controllers 21 and 22 receive signals of the selected model, the data of the corresponding model is written into the corresponding chip. When the master controller 20 successfully writes data into the chip, the light emitting diode D0 emits light, when the slave controller 21 successfully writes data into the chip, the light emitting diode D1 emits light, and when the slave controller 22 successfully writes data into the chip, the light emitting diode D2 emits light, so that an operator can know the data writing situation through the light emitting situation of each light emitting diode.
Further, the master controller 20 also receives signals output from the controllers 21, 22, thereby determining whether the slave controllers 21, 22 successfully write data to the chip, and outputs a signal to the display device 25.
Since the master controller 20 and the slave controllers 21 and 22 run the same program, the respective controllers write data to their respective chips in synchronization, and the chip data writing efficiency is high. In addition, since the master controller 20 is completely the same as the programs run by the slave controllers 21 and 22, there is no need to develop two sets of programs, and the development cost of the chip data writing and testing apparatus is low.
It should be noted that the program run by the master controller 20 is identical to the program run by the prior art, and for example, the program run by the master controller 10 shown in fig. 1 may be applied, so that the present embodiment does not need to improve the existing program at all, but only improves the connection manner of the master controller and the slave controller, that is, the master controller and the slave controller are both connected to the input keyboard, and one pin of the slave controller is connected to a pin of the master controller, and the purpose of reducing chip data writing and development of the test apparatus can be achieved by these changes.
Finally, it should be emphasized that the present invention is not limited to the above embodiments, for example, the master controller and the slave controller may use the specific devices and model changes, or the indicating circuit may not necessarily use the light emitting diode, and may use the buzzer instead, or the number of the slave controllers is set to one or more than three, and these changes should be included in the protection scope of the present invention.
Claims (8)
1. Chip data write in and testing arrangement includes:
the main controller is electrically connected with the display device and the first adapter;
the method is characterized in that:
the master controller is also electrically connected with at least one slave controller and receives signals output by the slave controllers, and each slave controller is electrically connected with a second adapter;
the master controller and the slave controller are both connected to an input selection device.
2. The chip data writing and testing device according to claim 1, wherein:
the type of the master controller is the same as that of the slave controller.
3. The chip data writing and testing device according to claim 1, wherein:
the main controller is electrically connected with the first indicating circuit.
4. The chip data writing and testing device according to claim 1, wherein:
each slave controller is electrically connected with the second indicating circuit.
5. The chip data writing and testing device according to any one of claims 1 to 4, wherein:
the slave controller outputs a working result signal to the master controller;
and the main controller outputs the working result signal to the display device.
6. The chip data writing and testing device according to any one of claims 1 to 4, wherein:
the input selection device is an input keyboard.
7. The chip data writing and testing device according to claim 6, wherein:
the input keyboard has at least two model selection keys.
8. The chip data writing and testing device according to any one of claims 1 to 4, wherein:
the model of the first adapter is the same as the model of the second adapter.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021190946.6U CN212484339U (en) | 2020-06-23 | 2020-06-23 | Chip data writing and testing device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021190946.6U CN212484339U (en) | 2020-06-23 | 2020-06-23 | Chip data writing and testing device |
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| CN212484339U true CN212484339U (en) | 2021-02-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20240160544A1 (en) * | 2022-11-10 | 2024-05-16 | Intelligent Memory Limited | Apparatus, systems, and methods for dynamically reconfigured semiconductor tester for volatile and non-volatile memories |
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- 2020-06-23 CN CN202021190946.6U patent/CN212484339U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20240160544A1 (en) * | 2022-11-10 | 2024-05-16 | Intelligent Memory Limited | Apparatus, systems, and methods for dynamically reconfigured semiconductor tester for volatile and non-volatile memories |
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