CN212463198U

CN212463198U - Programmable self-calibration single-integral analog-digital conversion circuit

Info

Publication number: CN212463198U
Application number: CN202021483455.0U
Authority: CN
Inventors: 许有联
Original assignee: Ningbo Core Photoelectric Technology Co ltd
Current assignee: Ningbo Core Photoelectric Technology Co ltd
Priority date: 2020-07-24
Filing date: 2020-07-24
Publication date: 2021-02-02
Anticipated expiration: 2030-07-24

Abstract

The utility model relates to a programmable self-calibration single integral analog-to-digital conversion circuit, which comprises a sawtooth wave generating circuit, a counter and three third comparators, wherein the sawtooth wave generating circuit comprises an integrator, a rising edge locking circuit and an unlocking circuit; the integrator comprises a controllable constant current source and a capacitor which are connected in series; the controllable constant current source is connected with the programming end; two ends of the capacitor are connected with a discharge switch in parallel; the rising edge locking circuit is used for realizing reliable discharge of the integrator; the unlocking circuit is used for unlocking the integrator to trigger integration action when a clock signal rising edge arrives; the output end of the integrator is connected with one input end of the three third comparators, and the output ends of the three third comparators are respectively connected with the three registers. The utility model discloses promote measurement accuracy when can reduce the circuit complexity.

Description

Programmable self-calibration single-integral analog-digital conversion circuit

Technical Field

The utility model relates to an integral type analog-to-digital conversion circuit especially relates to a self-calibration single integral type analog-to-digital conversion circuit able to programme.

Background

An integral ADC (analog-to-digital conversion) is an indirect measurement method for converting an electric signal into time and then measuring the time, and has the advantages of simple circuit, high measurement precision and the like, and the disadvantage of low measurement speed is generally applied to equipment such as a multimeter and the like.

The performance of the single integral ADC is related to the precision of an integral resistor and a capacitor and reference voltage, and the single integral ADC cannot achieve practical value due to the problems that the precision of element parameters, particularly the precision of the capacitor, is difficult to meet the requirement by the process level, and the parameters drift and the like.

The integrating elements (such as integrating resistor and integrating capacitor) used in the two integrating processes of the double-integration ADC can cancel each other out, so that the problems of parameter accuracy and drift can be solved. However, the double-integration circuit has switch delay in the two-time integration conversion process, a comparator used in the circuit is not ideal and has the problem of offset voltage, the starting time of a counting clock is random, the measuring time required by different measured voltages (Vin) is different, the speed of the improved multi-integration ADC circuit is slightly improved, and the complexity of the circuit is increased.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a self-calibration single integral type analog-to-digital conversion circuit able to programme is provided, promotes measurement accuracy when can reduce the circuit complexity.

The utility model provides a technical scheme that its technical problem adopted is: the programmable self-calibration single-integral analog-to-digital conversion circuit comprises a sawtooth wave generating circuit, a counter and three third comparators, wherein the output end of the counter is respectively connected with three registers, and the sawtooth wave generating circuit comprises an integrator, a rising edge locking circuit and an unlocking circuit; the integrator comprises a controllable constant current source and a capacitor which are connected in series; the controllable constant current source is connected with the programming end; two ends of the capacitor are connected with a discharge switch in parallel; the rising edge locking circuit is used for realizing reliable discharge of the integrator; the unlocking circuit is used for unlocking the integrator to trigger integration action when a clock signal rising edge arrives; the output end of the integrator is connected with one input end of three third comparators, the other input end of one of the three third comparators is connected with the VIN input end, and the other input ends of the other two third comparators are respectively connected with the positive reference voltage end and the negative reference voltage end; and the output ends of the three third comparators are respectively connected with the three registers.

The rising edge locking circuit comprises a first comparator, one input end of the first comparator is connected with the output end of the integrator, the other input end of the first comparator is connected with a first reference voltage, and the output end of the first comparator is connected with one input end of the OR gate; and the output end of the OR gate is respectively connected with the discharge switch and the counter.

The unlocking circuit comprises a second comparator and a D trigger, wherein one input end of the second comparator is connected with the output end of the integrator, the other input end of the second comparator is connected with a second reference voltage, and the output end of the second comparator is connected with one input end of the AND gate through the D trigger; and the other input end of the AND gate is connected with the output end of the OR gate, and the output end of the AND gate is connected with the other input end of the OR gate.

The D flip-flop is a rising edge flip-flop.

Advantageous effects

Since the technical scheme is used, compared with the prior art, the utility model, have following advantage and positive effect: the integrator of the utility model is composed of a controllable constant current source and a capacitor, and then realizes the sawtooth wave function through a discharge switch, changes the cycle of the sawtooth wave by changing the control signal of the controllable constant current source, and realizes the measurement with different precision (digit) under the condition of certain counting clock frequency, thereby realizing the programmable function; a rising edge locking circuit is formed by the first comparator, the AND gate and the OR gate to realize reliable discharge of the integrator; an unlocking circuit is formed by the second comparator and the D flip-flop, and the trigger integral action is unlocked if and only when the rising edge of the clock signal arrives, so that the problem of random phase of the counting clock is solved. In addition, three comparators with consistent characteristics are used, offset voltage is blanked out through subtraction operation in the self-calibration counting process, and therefore measuring accuracy is improved.

Drawings

Fig. 1 is a circuit diagram of the present invention;

FIG. 2 is a schematic diagram of the present invention;

FIG. 3 is a schematic diagram illustrating random problem verification of clock initial phases in an embodiment of the present invention;

FIG. 4 is a graph comparing results of direct conversion after injection of a perturbation with self calibration.

Detailed Description

The present invention will be further described with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Furthermore, it should be understood that various changes and modifications of the present invention may be made by those skilled in the art after reading the teachings of the present invention, and these equivalents also fall within the scope of the appended claims.

The utility model discloses an embodiment relates to a self-calibration list integral type analog-to-digital conversion circuit able to programme, as shown in FIG. 1, including sawtooth wave generating circuit, counter and three third comparator C, the output of counter is connected with three register respectively. The counter and the register in the embodiment can be replaced by a single chip microcomputer or an FPGA. The sawtooth wave generating circuit comprises an integrator, a rising edge locking circuit and an unlocking circuit.

In the present embodiment, the integrator includes a controllable constant current source 1 and a capacitor 2 connected in series; the controllable constant current source 1 is connected with a programming end; and a discharge switch 3 is connected in parallel at two ends of the capacitor 2. The output end of the integrator is connected with one input end of three third comparators C, the other input end of one third comparator C in the three third comparators C is connected with the VIN input end, and the other input ends of the other two third comparators C are respectively connected with a positive reference voltage end and a negative reference voltage end; the output ends of the three third comparators C are respectively connected with the three registers.

Therefore, the integrator is formed by a controllable constant current source and a capacitor and then a discharge switch to realize the sawtooth wave function, the period of the sawtooth wave is changed by changing the control signal of the controllable constant current source, and the measurement with different precision (digit) is realized under the condition that the frequency of the counting clock is certain, so that the programmable function is realized. By three third comparators with consistent characteristics, the offset voltage can be blanked out through subtraction in the self-calibration counting process.

The rising edge locking circuit is used for realizing reliable discharge of the integrator. The rising edge locking circuit comprises a first comparator A, one input end of the first comparator A is connected with the output end of the integrator, the other input end of the first comparator A is connected with a first reference voltage 4, and the output end of the first comparator A is connected with one input end of an OR gate 5; the output end of the or gate 5 is respectively connected with the discharge switch 3 and the counter.

The unlocking circuit is used for unlocking the integrator to trigger the integration action when the rising edge of the clock signal arrives. The unlocking circuit comprises a second comparator B and a D trigger 6, wherein one input end of the second comparator B is connected with the output end of the integrator, the other input end of the second comparator B is connected with a second reference voltage, and the output end of the second comparator B is connected with one input end of an AND gate 7 through the D trigger 6; the other input end of the and gate 7 is connected with the output end of the or gate 5, and the output end of the and gate 7 is connected with the other input end of the or gate 5. The second comparator B and the D flip-flop 6 constitute an unlocking circuit and unlock the trigger integration action if and only if the rising edge of the clock signal arrives, to solve the phase randomness problem of the count clock.

Fig. 2 is a schematic diagram illustrating a programmable self-calibration single-integration analog-to-digital conversion circuit according to this embodiment. Wherein, the slope of the integration curve is determined by a controlled constant current source, and the integration period is changed by changing the voltage so as to obtain different sampling precision and speed (the sampling precision is lower when the speed is higher). At the circled position in the figure, the integrator is triggered only at the rising edge of the clock CKL due to the characteristic of the D trigger, so that the consistency of the clock phase in the measurement process is ensured. The shaded area in the figure is the effective measurement area which avoids the start and end stages of the integrator and thus avoids errors such as switching delays. The parameter self-calibration function is realized by utilizing the relation according with the triangular proportional relation in the effective measurement area and by means of the reference voltage Vref, and the problem that the precision and the parameters of devices such as resistors, capacitors and the like are far away is solved. The measurement time T0, T1 and T2 are obtained by triggering three third comparators, and the offset cancellation voltage band can be cancelled by the self-calibration formula in the figure when the offset voltages of the three third comparators are consistent.

This is further explained below by means of simulation verification. Fig. 3 is a clock initial phase random problem verification. In the case of the upper half of FIG. 3 without D flip-flop, and the lower half with D flip-flop, the two are compared, where the time T2 is represented by the numbers q2_ 0-q 2_7 (for example, eight bits are simulated), and the time T1 is represented by the numbers q1_ 0-q 1_7, and the comparison shows that the D flip-flop without D flip-flop with circle has random fluctuation at the lowest bit, and the D flip-flop with D flip-flop has no random fluctuation problem.

The characteristics of the self-calibrating ADC are verified by adding a DAC circuit. Adding a disturbance signal (the effect is equivalent to parameter drift) at a programming end (Cycle), respectively obtaining digital signals of time T0, T1 and T2 (corresponding to q0, q1 and q2 ends), and respectively comparing a direct DAC conversion result with a result obtained by adopting self-calibration operation by a later stage access DAC circuit (AD558T), wherein the result is shown in figure 4.

Comparing the graph Vin with the input standard sine wave signal, n _1639 with the direct DAC conversion result, Vout with the self-calibration algorithm, the simulation result shows that the disturbance of the integral parameter can be ignored basically after the self-calibration algorithm is adopted, and the same effect of the double-integral ADC can be achieved.

It is not difficult to discover, the utility model discloses a self calibration ADC able to programme is extremely simple on the circuit, also avoids all factors that influence measurement accuracy as far as in the design, has eliminated measuring error in theory, so can realize a low cost, high accuracy, many application areas's ADC solution because possess measurement accuracy programmable function again.

Claims

1. A programmable self-calibration single-integral analog-to-digital conversion circuit comprises a sawtooth wave generating circuit, a counter and three third comparators, wherein the output end of the counter is respectively connected with three registers; the integrator comprises a controllable constant current source and a capacitor which are connected in series; the controllable constant current source is connected with the programming end; two ends of the capacitor are connected with a discharge switch in parallel; the rising edge locking circuit is used for realizing reliable discharge of the integrator; the unlocking circuit is used for unlocking the integrator to trigger integration action when a clock signal rising edge arrives; the output end of the integrator is connected with one input end of three third comparators, the other input end of one of the three third comparators is connected with the VIN input end, and the other input ends of the other two third comparators are respectively connected with the positive reference voltage end and the negative reference voltage end; and the output ends of the three third comparators are respectively connected with the three registers.

2. The programmable self-calibrating single-integration analog-to-digital conversion circuit of claim 1, wherein the rising edge locking circuit comprises a first comparator having an input connected to the output of the integrator, another input connected to a first reference voltage, and an output connected to an input of an or gate; and the output end of the OR gate is respectively connected with the discharge switch and the counter.

3. The programmable self-calibrating single-integration analog-to-digital conversion circuit according to claim 2, wherein the unlocking circuit comprises a second comparator and a D flip-flop, one input end of the second comparator is connected with the output end of the integrator, the other input end of the second comparator is connected with a second reference voltage, and the output end of the second comparator is connected with one input end of the and gate through the D flip-flop; and the other input end of the AND gate is connected with the output end of the OR gate, and the output end of the AND gate is connected with the other input end of the OR gate.

4. The programmable self-calibrating single-integration analog-to-digital conversion circuit of claim 3, wherein said D flip-flop is a rising edge flip-flop.