CN212463187U - Switching value signal control circuit - Google Patents

Switching value signal control circuit Download PDF

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Publication number
CN212463187U
CN212463187U CN202021136549.0U CN202021136549U CN212463187U CN 212463187 U CN212463187 U CN 212463187U CN 202021136549 U CN202021136549 U CN 202021136549U CN 212463187 U CN212463187 U CN 212463187U
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China
Prior art keywords
triode
electrically connected
interface
tube
mosfet field
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CN202021136549.0U
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Chinese (zh)
Inventor
汪亮
袁鹏
王文宇
李爱武
刘勇
邹志强
解苗
唐赛
朱晶亮
肖红
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Zhongke Electric Co ltd
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Zhongke Electric Co ltd
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Abstract

The utility model provides a switching value signal control circuit, switching value signal control circuit includes microprocessor, first switch tube, relay, microprocessor has first IO interface, second IO interface, third IO interface, the control end and the first IO interface electricity of first switch tube are connected, a pair of normally open contact of relay is connected in switching value signal control circuit's controlled circuit, switching value signal control circuit still includes second switch tube, switch tube drive unit, first switch tube, second switch tube, relay coil series connection electricity are connected between first supply terminal and ground; the switch tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switch tube, and a third end electrically connected with the second I/O interface. The utility model discloses can avoid producing the risk of malfunction because of the unexpected acquiescence level signal of first IO interface output, control the relay safely.

Description

Switching value signal control circuit
Technical Field
The utility model relates to an industrial automation control field, concretely designs a circuit of reliable output of switching value signal.
Background
With the national step-in industrial 4.0 information intelligent era, unmanned, automatic, digital and intelligent control becomes the most main development trend in the field of industrial field control in recent years, and almost permeates into each field of industrial control fields, such as unmanned workshops, unmanned restaurants and other application places; the unmanned, automatic, digital and intelligent control is based on the collection and output of a reliable and stable field control system, and the requirements on the precision and accuracy of automatic control are higher and higher, such as collection of analog quantity, collection of input signals of switching quantity, output control of signal of switching quantity and the like.
The conventional switching value signal output control main schematic diagram is shown in fig. 1(a) and 1 (b); the state of a transistor triode or an enhanced MOSFET electronic switch is controlled mainly by configuring the high-low level state of an I/O port output by a microprocessor MCU, so that the power on or power off of a relay coil is achieved, and finally, a relay contact is closed or disconnected, the modes of figure 1(a) and figure 1(b) have the advantages of strong electric isolation and common-mode interference resistance, but the two modes have a fatal defect, when the microprocessor is in the power on and power off processes, the I/O port of the microprocessor is in an uncertain state or an uncontrolled state, the default state of the I/O port of each microprocessor chip is different in the period from the power on of the microprocessor chip to the initialization of a switching value signal output I/O port, the default state of the I/O port of some microprocessor chips is high level, and the default state of the I/O port of some microprocessor chips is low level, therefore, the conventional solutions shown in fig. 1(a) and 1(b) are prone to malfunction of the switching value signal in the above-mentioned uncertain state, which brings fatal harm to the stability, safety and reliability of the control system. Since the default level is not controllable, it can only be set adaptively for different microprocessors to avoid the above-mentioned malfunction. However, since the default levels of different microprocessors are different, if the default levels are set for each microprocessor, the production efficiency is greatly affected.
SUMMERY OF THE UTILITY MODEL
The to-be-solved problem of the utility model is to different microprocessor different and uncontrolled at the power of getting with lose the electric in-process IO mouth default state for traditional switching value signal control circuit produces switching value signal malfunction and brings the problem of fatal harm for control system's stability, security and reliability very easily at this in-process, provides a switching value signal control circuit.
In order to solve the technical problem, the utility model discloses a technical scheme is: a switching value signal control circuit comprises a microprocessor, a first switching tube and a relay, wherein the microprocessor is provided with a first I/O interface, a second I/O interface and a third I/O interface, the control end of the first switching tube is electrically connected with the first I/O interface, and a pair of normally open contacts of the relay is connected in a controlled circuit of the switching value signal control circuit;
the method is characterized in that: the switching value signal control circuit also comprises a second switching tube and a switching tube driving unit, wherein the first switching tube, the second switching tube and the relay coil are electrically connected between the first power supply end and the ground in series;
the switching tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switching tube and a third end electrically connected with the second I/O interface;
the circuit structure of the switching tube driving unit is characterized in that:
(A) when the output of the second I/O interface and the output of the third I/O interface are both high level, the switching tube driving unit turns off the second switching tube;
(B) when the output of the second I/O interface and the output of the third I/O interface are both low level, the switching tube driving unit turns off the second switching tube;
(C) when the outputs of the second I/O interface and the third I/O interface are respectively a high level and a low level, or when the outputs of the second I/O interface and the third I/O interface are respectively a low level and a high level, or when the outputs of the second I/O interface and the third I/O interface are respectively a high level and a low level and the first switching tube is turned on, or when the outputs of the second I/O interface and the third I/O interface are respectively a low level and a high level and the first switching tube is turned on, the switching tube driving unit turns on the second switching tube.
The applicant researches and discovers that although default states of the I/O ports of different microprocessors are different and uncontrolled in power-on and power-off processes, output level states of output levels of the I/O ports in the processes are consistent for the same microprocessor, namely, the output levels are both high or low. The utility model discloses in, when the output of getting electric or losing electric in-process second IO interface, third IO interface default be the high level or default when identifying for the low level, switch tube drive unit all makes the second switch tube turn-off, even this moment because the acquiescence output level of first IO interface has transmitted wrong level signal to first switch tube, because first switch tube, second switch tube, relay coil series connection electricity are connected, consequently the relay coil can not switch on because of the malfunction yet to avoid producing the risk of malfunction because of the unexpected acquiescence level signal of first IO interface output, effectively protected switching value signal control circuit's controlled circuit. When the outputs of the second I/O interface and the third I/O interface are opposite levels (one is high level, and the other is low level), the microprocessor finishes the initialization of each I/O interface, and at the moment, the relay is controlled by each I/O interface, so that the risk of misoperation is avoided. If the structure of the switching tube driving unit enables the second switching tube to be conducted when the outputs of the second I/O interface and the third I/O interface are respectively at a high level and a low level or when the outputs of the second I/O interface and the third I/O interface are respectively at a low level and a high level, the on-off of the first switching tube can be controlled by utilizing the output level of the first I/O interface, and if the first switching tube is conducted, the first switching tube and the second switching tube in the series circuit are conducted to enable the relay to meet the electric condition, so that the relay can be safely controlled. If the structure of the switching tube driving unit makes the second switching tube be turned on when the outputs of the second I/O interface and the third I/O interface are respectively at the high level and the low level and the first switching tube is turned on or when the outputs of the second I/O interface and the third I/O interface are respectively at the low level and the high level and the first switching tube is turned on, the first switching tube and the second switching tube in the series circuit are turned on to enable the relay to meet the electric condition, so that the relay can be safely controlled.
Furthermore, the switch tube driving unit is a third switch tube, and a control end, a connection end and another connection end of the third switch tube are respectively a first end, a second end and a third end of the switch tube driving unit;
the circuit structure of the third switching tube is that:
(A1) when the output of the second I/O interface and the output of the third I/O interface are both high level, the third switch tube is turned off, so that the second switch tube is turned off;
(B1) when the output of the second I/O interface and the output of the third I/O interface are both low level, the third switching tube is turned off, so that the second switching tube is turned off;
(C1) when the output of the second I/O interface and the output of the third I/O interface are respectively at a high level and a low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively at a low level and a high level, the third switching tube is turned on;
(D1) when the third switch tube is conducted, or when the first switch tube and the third switch tube are both conducted, the second switch tube is conducted.
Further, the first switch tube, the second switch tube and the third switch tube are respectively a triode T1, a triode T2 and a triode T3, a base of each triode corresponds to a control end of each triode, and a collector and an emitter of the triode T3 are respectively a connection end and another connection end of the triode T3;
(a1) the triode T1, the triode T2 and the triode T3 are respectively NPN type, PNP type and NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of a relay coil and the ground, and a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the relay coil and a first power supply end; or
(b1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, a collector electrode and an emitter electrode of the triode T1 are respectively and correspondingly electrically connected with an emitter electrode and ground of the triode T2, and a collector electrode of the triode T2 is electrically connected with a first power supply end through a relay coil; or
(c1) The triode T1, the triode T2 and the triode T3 are respectively of a PNP type, a PNP type and an NPN type, a collector electrode of the triode T1 is electrically connected with the ground through a relay coil, and a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T1; or
(d1) The triode T1, the triode T2 and the triode T3 are respectively of a PNP type, an NPN type and a PNP type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of the relay coil and the first power supply end, and a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the relay coil and the ground; or
(e1) The triode T1, the triode T2 and the triode T3 are respectively PNP type, PNP type and NPN type, a collector electrode and an emitter electrode of the triode T1 are respectively and correspondingly and electrically connected with an emitter electrode and a first power supply end of the triode T2, and a collector electrode of the triode T2 is electrically connected with the ground through a relay coil; or
(f1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, a collector electrode of the triode T1 is electrically connected with the first power supply end through a relay coil, and a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly and electrically connected with an emitter electrode and ground of the triode T1.
Further, the first switch tube, the second switch tube and the third switch tube are respectively a MOSFET field effect tube Q1, a MOSFET field effect tube Q2 and a MOSFET field effect tube Q3, the gate of each MOSFET field effect tube is respectively a control end of each MOSFET field effect tube, and the drain and the source of the MOSFET field effect tube Q3 are respectively a connection end and another connection end of the MOSFET field effect tube Q3;
(a2) the MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with one end of the relay coil and the ground, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly and electrically connected with the other end of the relay coil and the first power supply end; or
(b2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field-effect tube Q2, and the drain electrode of the MOSFET field-effect tube Q2 is electrically connected with a first power supply end through a relay coil; or
(c2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field-effect tube Q1 is electrically connected with the ground through a relay coil, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field-effect tube Q1; or
(d2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with one end of the relay coil and the first power supply end, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly and electrically connected with the other end of the relay coil and the ground; or
(e2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field-effect tube Q2, and the drain electrode of the MOSFET field-effect tube Q2 is electrically connected with the ground through a relay coil; or
(f2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field-effect tube Q1 is electrically connected with the first power supply end through a relay coil, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field-effect tube Q1.
Furthermore, the switch tube driving unit is a logic gate circuit with two logic input ends and one logic output end,
one logic input end, one logic output end and the other logic input end of the logic gate circuit are respectively a first end, a second end and a third end of the logic gate circuit;
the circuit structure of the logic gate circuit is such that:
(A2) when the output of the second I/O interface and the output of the third I/O interface are both high level, the logic gate circuit outputs a first level signal, so that the second switching tube is switched off;
(B2) when the outputs of the second I/O interface and the third I/O interface are both low level, the logic gate circuit outputs a first level signal, so that the second switching tube is switched off;
(C2) when the outputs of the second I/O interface and the third I/O interface are respectively at a high level and a low level, or when the outputs of the second I/O interface and the third I/O interface are respectively at a low level and a high level, the logic gate circuit outputs a second level signal;
(D2) when the logic gate circuit outputs a second level signal, or when the first switch tube is switched on and the logic gate circuit outputs the second level signal, the second switch tube is switched on.
Furthermore, the first switch tube and the second switch tube are respectively a triode T1 and a triode T2, and the base of each triode is the control end of each triode;
(a3) the triode T1 and the triode T2 are respectively NPN type and PNP type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of the relay coil and the ground, a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the relay coil and the first power supply end, and the logic gate circuit is a logic exclusive-OR gate; or
(b3) The triode T1 and the triode T2 are respectively NPN type and NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with an emitter and ground of the triode T2, a collector of the triode T2 is electrically connected with a first power supply end through a relay coil, and the logic gate circuit is a logic exclusive-OR gate; or
(c3) The triode T1 and the triode T2 are respectively of a PNP type and a PNP type, a collector electrode of the triode T1 is electrically connected with the ground through a relay coil, a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T1, and the logic gate circuit is a logic exclusive-OR gate; or
(d3) The triode T1 and the triode T2 are respectively of a PNP type and an NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of the relay coil and the first power supply end, a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the relay coil and the ground, and the logic gate circuit is a logic exclusive-OR gate; or
(e3) The triode T1 and the triode T2 are respectively of a PNP type and a PNP type, a collector electrode and an emitter electrode of the triode T1 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T2, the collector electrode of the triode T2 is electrically connected with the ground through a relay coil, and the logic gate circuit is a logic exclusive-OR gate; or
(f3) The triode T1 and the triode T2 are respectively of an NPN type and an NPN type, a collector electrode of the triode T1 is electrically connected with the first power supply end through a relay coil, a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and the ground of the triode T1, and the logic gate circuit is a logic exclusive-OR gate.
Furthermore, the first switch tube and the second switch tube are respectively a MOSFET field effect tube Q1 and a MOSFET field effect tube Q2, and the gate of each MOSFET field effect tube is the control end of each MOSFET field effect tube;
(a4) the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with one end of the relay coil and the ground, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the other end of the relay coil and the first power supply end, and the logic gate circuit is a logic exclusive-OR gate; or
(b4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect transistor Q2, the drain electrode of the MOSFET field effect transistor Q2 is electrically connected with a first power supply end through a relay coil, and the logic gate circuit is a logic exclusive-OR gate; or
(c4) The MOSFET (metal-oxide-semiconductor field effect transistor) Q1 and the MOSFET Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET Q1 is electrically connected with the ground through a relay coil, the drain electrode and the source electrode of the MOSFET Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET Q1, and the logic gate circuit is a logic exclusive-OR gate; or
(d4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with one end of the relay coil and the first power supply end, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the other end of the relay coil and the ground, and the logic gate circuit is a logic exclusive-OR gate; or
(e4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field effect transistor Q2, the drain electrode of the MOSFET field effect transistor Q2 is electrically connected with the ground through a relay coil, and the logic gate circuit is a logic exclusive-OR gate; or
(f4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is electrically connected with the first power supply end through a relay coil, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect transistor Q1, and the logic gate circuit is a logic exclusive-OR gate.
Further, the first power supply terminal is electrically connected with a positive voltage power supply terminal of the microprocessor.
The utility model has the advantages and positive effects that: the utility model discloses can avoid producing the risk of malfunction because of the unexpected acquiescence level signal of first IO interface output, control the relay safely.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1(a) is a schematic diagram of a prior art transistor switching value output circuit;
FIG. 1(b) is a schematic diagram of a prior art enhanced MOSFET switching value output circuit;
fig. 2(a) is a schematic circuit structure diagram of a switching value signal control circuit according to embodiment 1 of the present invention;
fig. 2(b) is a schematic circuit structure diagram of a switching value signal control circuit according to embodiment 2 of the present invention;
fig. 2(c) is a schematic circuit structure diagram of a switching value signal control circuit according to embodiment 3 of the present invention;
fig. 3 is a schematic circuit structure diagram of a switching value signal control circuit according to embodiment 4 of the present invention;
fig. 4 is a schematic circuit structure diagram of a switching value signal control circuit according to embodiment 7 of the present invention;
fig. 5(a) is a schematic diagram of a partial circuit structure of a switching value signal control circuit according to embodiment 13 of the present invention;
fig. 5(b) is a schematic diagram of a partial circuit structure of the switching value signal control circuit according to embodiment 14 of the present invention;
fig. 5(c) is a schematic diagram of a partial circuit structure of the switching value signal control circuit according to embodiment 15 of the present invention;
in the figure, the device comprises a microprocessor 1, a microprocessor 2, a relay 3, a logic exclusive-OR gate 4 and a logic exclusive-OR gate.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example 1
How to ensure that the switching value signal of the whole process can be stably, reliably and safely output is the key point for reducing the misoperation of the industrial automation field control system.
The utility model provides a switching value signal control circuit, including microprocessor 1, first switch tube, relay 2, microprocessor 1 has first IO interface, second IO interface, third IO interface, the control end and the first IO interface electricity of first switch tube are connected, a pair of normally open contact (P1, P2) of relay 2 are connected in switching value signal control circuit's controlled circuit, switching value signal control circuit still includes second switch tube, switch tube drive unit. The controlled circuit is switched on or off by a pair of normally open contacts of the relay 2.
The first switch tube, the second switch tube and the relay 2 coil are electrically connected between the first power supply end and the ground in series. The first switch tube, the second switch tube and the coil of the relay 2 are electrically connected between the first power supply end and the ground in series, and the meaning is that: and the two connecting ends of the first switch tube, the two connecting ends of the second switch tube and the two ends of the coil of the relay 2 are all positioned in a series circuit between the first power supply end and the ground.
The switch tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switch tube, and a third end electrically connected with the second I/O interface.
The circuit structure of the switching tube driving unit is characterized in that:
(A) when the output of the second I/O interface and the output of the third I/O interface are both high level, the switching tube driving unit turns off the second switching tube;
(B) when the output of the second I/O interface and the output of the third I/O interface are both low level, the switching tube driving unit turns off the second switching tube;
(C) when the outputs of the second I/O interface and the third I/O interface are respectively a high level and a low level, or when the outputs of the second I/O interface and the third I/O interface are respectively a low level and a high level, or when the outputs of the second I/O interface and the third I/O interface are respectively a high level and a low level and the first switching tube is turned on, or when the outputs of the second I/O interface and the third I/O interface are respectively a low level and a high level and the first switching tube is turned on, the switching tube driving unit turns on the second switching tube.
The first I/O interface, the second I/O interface and the third I/O interface are I/O1, I/O2 and I/O3 respectively.
The switch tube driving unit is a third switch tube, and a control end, a connecting end and the other connecting end of the third switch tube are respectively a first end, a second end and a third end of the switch tube driving unit;
as shown in fig. 2(a), in this embodiment 1, the first switch tube, the second switch tube, and the third switch tube are a transistor T1, a transistor T2, and a transistor T3, respectively. The base electrodes B1, B2, and B3 of the respective triodes correspond to the control terminals of the respective triodes, and the collector electrode C3 and the emitter electrode E3 of the triode T3 are respectively one connection terminal and the other connection terminal of the triode T3, and are respectively electrically connected to the base electrode B2 and the second I/O interface I/O2 of the triode T2.
The triode T1, the triode T2 and the triode T3 are respectively NPN type, PNP type and NPN type, a collector C1 and an emitter E1 of the triode T1 are respectively and correspondingly electrically connected with one end of the coil of the relay 2 and the ground GND, and a collector C2 and an emitter E2 of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the first power supply end VCC.
In this embodiment 1, through the structure of the transistor T1, the transistor T2, and the transistor T3 and the connection relationship, the following steps are performed:
(A1) when the outputs of the second I/O interface and the third I/O interface are both high level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(B1) when the outputs of the second I/O interface and the third I/O interface are both low level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(C1) when the outputs of the second I/O interface and the third I/O interface are respectively at a low level and a high level, the transistor T3 is turned on. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is completed after the microprocessor 1 is started, namely, the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is started, and two switching tubes connected with the coil of the relay 2 in series are not required to be reused for protection;
(D1) when the transistor T3 is turned on, the transistor T2 is turned on. If the output level of the I/O1 is high, the transistor T1 is turned on, and at this time, both the two switch tubes connected in series with the coil of the relay 1 are turned on, so that the output level of the I/O1 can be used to control the connection or disconnection of a pair of normally open contacts of the relay 1.
A diode D1 is connected in parallel to the relay 2 coil.
The first power supply terminal VCC may be a positive voltage power supply terminal. Preferably, the first power supply terminal VCC is electrically connected to a positive voltage power supply terminal VDD of the microprocessor 1. Ground GND is common to ground terminal VSS of microprocessor 1.
T1, T2 and T3 are transistors. The PNP triode can be selected from the triode with model number SS8550BBU of fairy children company, and Collector Current ICis-1.5A, collector emitter voltage VCEis-25V. The NPN triode can be selected from BC81716MFT triode manufactured by fairy children company, the Collector Current (Collector Current) is 0.8A, and the Collector emitter voltage VCEAt 45V, transistors T1, T2, and T3 all operate in a switching state. Collector current I of transistors T1, T2 and T3CCollector emitter voltage VCEThe requirements are met in a weak current control system of a microprocessor. The sink current and source current capability of an I/O port of the microprocessor are +/-4 mA, the I/O port generally outputs 3.3V or 5V level when outputting high level, and the I/O port generally outputs 0V level when outputting low level. The model of the switching value output relay 2 can be PA1a-5V of Songhai company, the rated voltage of two ends of a coil is 5VDC, the rated current consumption of the relay is 24mA, and under the condition that the power VCC power is enough, the transistor of T1, T2 and T3 can meet the requirement of on-site switching value signal output. Diode D1 is a freewheeling diode for releasing the coil of the relay, and diode D1 provides a freewheeling circuit for the coil energy when the relay coil is in a power-off condition to avoidVoltage spikes appear to break down the relay coil, diode model FDLL4148 from fairchild corporation.
The microprocessor can be a single chip microcomputer, a DSP, an FPGA, a CPLD control chip, such as TMS320F2812 of TI company.
A first resistor R1 is connected between the base of the triode T1 and the first I/O interface, a second resistor R2 is connected between the base of the triode T2 and the collector of the triode T3, and a third resistor R3 is connected between the base of the triode T3 and the third I/O interface. The resistances of the first resistor R1, the second resistor R2 and the third resistor R3 can be selected to be 4.7K omega, 1.5K omega and 4.7K omega, so that the current flowing into or out of the I/O port of the microprocessor is controlled to be below 4 mA.
In this embodiment 1, after the microprocessor MCU is powered on and the initialization is completed, in the initialization process of the I/O port of the microprocessor, the I/O1, the I/O2 and the I/O3 may be set to be in a push-pull output state, and in the whole operation process of outputting the switching value of the microprocessor, the I/O3 is set to be in a high level output state, and the I/O2 is set to be in a low level output state, and when the relay 2 contact needs to be controlled to be closed, the I/O1 is set to be in a high level state, and when the relay contact needs to be controlled to be opened, the I/O1 is set to be in a low level state, so as to control the relay 2 coil to be de-energized or energized, so that the pair of normally open contacts of the.
Example 2
As shown in fig. 2(b), the present embodiment 2 is different from embodiment 1 in that: the triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, a collector C1 and an emitter E1 of the triode T1 are respectively and correspondingly electrically connected with an emitter E2 and ground GND of the triode T2, and a collector C2 of the triode T2 is electrically connected with a first power supply end VCC through a coil of the relay 2.
In this embodiment 2, through the structure of the transistor T1, the transistor T2, and the transistor T3 and the connection relationship, the following steps are performed:
(A1) when the outputs of the second I/O interface I/O2 and the third I/O interface I/O3 are both high level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O states immediately after the microprocessor is started is avoided;
(B1) when the outputs of the second I/O interface I/O2 and the third I/O interface I/O3 are both low level, the triode T3 is turned off, so that the triode T2 is turned off, and a pair of normally open contacts of the relay 1 cannot be communicated, thereby avoiding misoperation caused by uncertain and uncontrolled I/O state after the microprocessor is started;
(C1) when the outputs of the second I/O interface and the third I/O interface are respectively at a high level and a low level, the transistor T3 is turned on. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is completed after the microprocessor 1 is started, namely, the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is started, and the two switching tubes connected with the coil of the relay 2 in series are not required to be reused for protection.
(D1) When the transistor T1 and the transistor T3 are both turned on, the transistor T2 is turned on. After the triode T3 is conducted, the relay 2 can be controlled by the triode T1, namely, the output signal of the I/O1 enables the triode T1 to be conducted, at the moment, the triode T2 is conducted, the conduction condition is also met, and the conduction is achieved, so that the loop where the coil of the relay 1 is located is conducted, and the pair of normally open contacts is closed. If the output signal of the I/O1 signals the transistor T1 to turn off, it indicates that the controlled circuit is not desired to be turned on, and the circuit in which the coil of the relay 1 is located cannot be turned on because the transistor T1 is turned off and the transistor T2 is turned off, so the controlled circuit cannot be turned on.
In this embodiment 2, after the microprocessor MCU is powered on and the initialization is completed, during the initialization of the I/O port of the microprocessor, the I/O1, the I/O2 and the I/O3 are all set to the push-pull output state, and during the whole operation of the microprocessor for outputting the switching value, the I/O3 is set to the low level output and the I/O2 is set to the high level output. When the contact of the relay 2 needs to be controlled to be closed, the I/O1 is set to be at a high level, and when the contact of the relay needs to be controlled to be opened, the I/O1 is set to be at a low level, so that the coil of the relay 2 is controlled to be powered off or powered on, a pair of normally open contacts of the relay 2 is turned off or on, and the control on a controlled circuit is realized.
Example 3
As shown in fig. 2(c), the present embodiment 3 differs from embodiment 1 in that: triode T1, triode T2, triode T3 are PNP type, NPN type respectively, the collecting electrode of triode T1 passes through the relay 2 coil and is connected with ground GND electricity, the collecting electrode of triode T2, projecting pole correspond the electricity with projecting pole, the first supply terminal VCC of triode T1 respectively and are connected.
(A1) When the outputs of the second I/O interface and the third I/O interface are both high level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(B1) when the outputs of the second I/O interface and the third I/O interface are both low level, the triode T3 is turned off, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(C1) when the outputs of the second I/O interface and the third I/O interface are respectively at a low level and a high level, the transistor T3 is turned on. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is completed after the microprocessor 1 is started, namely, the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is started, and two switching tubes connected with the coil of the relay 2 in series are not required to be reused for protection;
(D1) when the transistor T3 is turned on, the transistor T2 is turned on. When the transistor T3 is turned on, the transistor T2 is turned on. If the output level of the I/O1 is low, the transistor T1 is turned on, and at this time, both transistors connected in series with the coil of the relay 1 are turned on, so that the transistor T1 can be controlled by the output level of the I/O1, thereby controlling the connection or disconnection of a pair of normally open contacts of the relay 1.
In this embodiment 3, after the microprocessor MCU is powered on and the initialization is completed, in the initialization process of the I/O port of the microprocessor, the I/O1, the I/O2 and the I/O3 are all set to be in the push-pull output state, and in the whole operation process of the microprocessor for outputting the switching value, the I/O3 is set to be in the high level output state, and the I/O2 is set to be in the low level output state, and when the relay 2 contact needs to be controlled to be closed, the I/O1 is set to be in the low level state, and when the relay contact needs to be controlled to be opened, the I/O1 is set to be in the high level state, so as to control the relay 2 coil to be de-energized or energized, so that the pair of normally open contacts of.
Examples 4 to 6
As shown in fig. 3, example 4 differs from example 1 in that: the triode T1, the triode T2 and the triode T3 are respectively of a PNP type, an NPN type and a PNP type, a collector C1 and an emitter E1 of the triode T1 are respectively and correspondingly electrically connected with one end of a coil of the relay 2 and a first power supply end VCC, and a collector C2 and an emitter E2 of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the ground GND.
Example 5 differs from example 4 in that: the triode T1, the triode T2 and the triode T3 are respectively PNP type, PNP type and NPN type, a collector C1 and an emitter E1 of the triode T1 are respectively and correspondingly electrically connected with an emitter E2 and a first power supply end of the triode T2, and a collector C2 of the triode T2 is electrically connected with the ground through a coil of the relay 2. The corresponding figures are not shown, and can be obtained by analogy with FIG. 3.
Example 6 differs from example 4 in that: the triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector electrode of the triode T1 is electrically connected with the first power supply end through the coil of the relay 2, and the collector electrode and the emitter electrode of the triode T2 are respectively and correspondingly electrically connected with the emitter electrode and the ground of the triode T1. The corresponding figures are not shown, and can be obtained by analogy with FIG. 3.
Examples 7 to 12
As shown in fig. 4, example 7 differs from example 1 in that: the first switch tube, the second switch tube and the third switch tube are respectively a MOSFET field effect tube Q1, a MOSFET field effect tube Q2 and a MOSFET field effect tube Q3, the grid electrodes (G1, G2 and G3) of each MOSFET field effect tube are respectively the control ends of each MOSFET field effect tube, the drain electrode D3 and the source electrode S3 of the MOSFET field effect tube Q3 are respectively one connecting end and the other connecting end of the MOSFET field effect tube Q3 and are respectively and correspondingly and electrically connected with the grid electrode G2 and the I/O2 of the Q2, and the grid electrode G3 is electrically connected with the I/O3. MOSFET field-effect transistor Q1, MOSFET field-effect transistor Q2, MOSFET field-effect transistor Q3 are N channel enhancement mode, P channel enhancement mode, N channel enhancement mode respectively, MOSFET field-effect transistor Q1 'S drain electrode D1, source S1 correspond the electricity with relay 2 coil one end, ground GND respectively and are connected, MOSFET field-effect transistor Q2' S drain electrode D2, source S2 correspond the electricity with relay 2 coil other end, first feed end VCC respectively and are connected.
Example 8 differs from example 7 in that: the MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field-effect tube Q2, and the drain electrode of the MOSFET field-effect tube Q2 is electrically connected with the first power supply end through a relay 2 coil. The corresponding figures are not shown, and can be obtained by analogy with FIG. 4.
Example 9 differs from example 7 in that: the MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field-effect tube Q1 is electrically connected with the ground through a relay 2 coil, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field-effect tube Q1. The corresponding figures are not shown, and can be obtained by analogy with FIG. 4.
Example 10 differs from example 7 in that: the power supply system is characterized in that the MOSFET (metal oxide semiconductor field effect transistor) Q1, the MOSFET Q2 and the MOSFET Q3 are respectively of a P-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET Q1 are respectively and correspondingly electrically connected with one end of the relay 2 coil and the first power supply end, and the drain electrode and the source electrode of the MOSFET Q2 are respectively and correspondingly and electrically connected with the other end of the relay 2 coil and the ground. The corresponding figures are not shown, and can be obtained by analogy with FIG. 4.
Example 11 differs from example 7 in that: the MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field-effect tube Q2, and the drain electrode of the MOSFET field-effect tube Q2 is electrically connected with the ground through a relay 2 coil. The corresponding figures are not shown, and can be obtained by analogy with FIG. 4.
Example 12 differs from example 7 in that: the MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field-effect tube Q1 is electrically connected with the first power supply end through the relay 2 coil, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field-effect tube Q1. The corresponding figures are not shown, and can be obtained by analogy with FIG. 4.
In the embodiment of the present invention, the P-channel enhancement MOSFET model can adopt FDN5618P, Drain Current (Drain Current) I of the company of armeniamDis-1.25A, the drain source voltage VDSis-60V. The model of the N-channel enhancement type MOSFET can adopt 2N7002, Drain Current (Drain Current) I of the company AnsonD0.115A, drain-source voltage VDSIs 60V. The Q1, Q2 and Q3 enhancement mode MOSFETs are all operated in the on-off state, the drain currents I of Q1, Q2 and Q3DAnd a drain source voltage VDSThe requirements are met in a weak current control system of a microprocessor.
A first resistor R1 may be disposed between the gate G1 of Q1 and the first I/O interface, a second resistor R2 may be disposed between the gate G2 of Q2 and the drain D3 of Q3, and a third resistor R3 may be disposed between the gate G3 of Q3 and the third I/O interface. R1, R2 and R3 can adopt chip resistors with 3K resistance values, and the current flowing into or out of the I/O port of the microprocessor is controlled to be below 4 mA.
Example 13
This example 13 differs from example 1 in that:
the switch tube driving unit is a logic gate circuit with two logic input ends and one logic output end, and one logic input end, one logic output end and the other logic input end of the logic gate circuit are respectively a first end, a second end and a third end of the logic gate circuit.
The circuit structure of the logic gate circuit is such that:
(A2) when the output of the second I/O interface and the output of the third I/O interface are both high level, the logic gate circuit outputs a first level signal, so that the second switching tube is switched off;
(B2) when the outputs of the second I/O interface and the third I/O interface are both low level, the logic gate circuit outputs a first level signal, so that the second switching tube is switched off;
(C2) when the outputs of the second I/O interface and the third I/O interface are respectively at a high level and a low level, or when the outputs of the second I/O interface and the third I/O interface are respectively at a low level and a high level, the logic gate circuit outputs a second level signal;
(D2) when the logic gate circuit outputs a second level signal, or when the first switch tube is switched on and the logic gate circuit outputs the second level signal, the second switch tube is switched on.
The first switch tube and the second switch tube are respectively a triode T1 and a triode T2, and a base B1 and a base B2 of each triode are control ends of each triode;
the circuit difference between this embodiment 13 and embodiment 1 is that the elements in fig. 5(a) are used to replace the elements between the I/O interface of the microprocessor 1 and point M2 in fig. 2 (a).
In this embodiment 13, the triode T1 and the triode T2 are respectively NPN type and PNP type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected to one end of the coil of the relay 2 and the ground, a collector and an emitter of the triode T2 are respectively and correspondingly and electrically connected to the other end of the coil of the relay 2 and the first power supply end, and the logic gate circuit is a logic exclusive or gate 4.
In this embodiment 13, through the structure of the transistor T1, the transistor T2, and the logic xor gate 4 and the connection relationship, it is possible to:
(A2) when the outputs of the second I/O interface and the third I/O interface are both high level, the output of the logic exclusive-OR gate 4 is high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(B2) when the outputs of the second I/O interface and the third I/O interface are both low level, the output of the logic exclusive-OR gate 4 is high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(C2) and when the outputs of the second I/O interface and the third I/O interface are respectively low level and high level or high level and low level, the output of the logic exclusive-OR gate 4 is low level. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is completed after the microprocessor 1 is started, namely, the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is started, and two switching tubes connected with the coil of the relay 2 in series are not required to be reused for protection;
(D2) when the output of the logic exclusive or nor gate 4 is at a low level, the transistor T2 is turned on. If I/O1 outputs a high, transistor T1 is turned on. At this time, two switch tubes connected in series with the coil of the relay 1 are both conducted, so that the output level of the I/O1 can be used for controlling the connection or disconnection of a pair of normally open contacts of the relay 1.
In this embodiment, the exclusive nor gate may adopt HEF4077B, and the exclusive nor gate may adopt 74HCT1G 86.
Example 14
The circuit difference between this embodiment 14 and embodiment 1 is that the elements in fig. 5(b) are used to replace the devices between the I/O interface of the microprocessor 1 and point M1 in fig. 2 (b).
The present embodiment 14 differs from embodiment 13 in that: the triode T1 and the triode T2 are respectively NPN type and NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with an emitter and ground of the triode T2, a collector of the triode T2 is electrically connected with a first power supply end VCC through a coil of the relay 2, and the logic gate circuit is a logic exclusive-OR gate 3.
In this embodiment 14, through the structure of the transistor T1, the transistor T2, and the logic xor gate 3 and the connection relationship, it is possible to:
(A2) when the outputs of the second I/O interface and the third I/O interface are both high level, the output of the logic exclusive-OR gate 3 is low level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and the misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(B2) when the outputs of the second I/O interface and the third I/O interface are both at a low level, the output of the logic exclusive-OR gate 3 is at a low level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O states immediately after the microprocessor is started is avoided;
(C2) and when the outputs of the second I/O interface and the third I/O interface are respectively low level and high level or high level and low level, the output of the logic exclusive-OR gate 3 is high level. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is completed after the microprocessor 1 is started, namely, the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is started, and two switching tubes connected with the coil of the relay 2 in series are not required to be reused for protection;
(D2) when the logic exclusive or gate 3 output is high and the transistor T1 is on, the transistor T2 is on. When the I/O1 outputs a high level, the transistor T1 can be used to control the relay 2, i.e., the output signal of the I/O1 makes the transistor T1 conduct, and at this time, the transistor T2 conducts and also meets the conduction condition to conduct, so that the loop where the coil of the relay 1 is located conducts, and thus the pair of normally open contacts is closed. If the output signal of the I/O1 signals the transistor T1 to turn off, it indicates that the controlled circuit is not desired to be turned on, and the circuit in which the coil of the relay 1 is located cannot be turned on because the transistor T1 is turned off and the transistor T2 is turned off, so the controlled circuit cannot be turned on.
Example 15
The circuit difference between this embodiment 15 and embodiment 1 is that the elements in fig. 5(c) are used instead of the elements between the I/O interface of the microprocessor 1 and point M3 in fig. 2 (c).
The present embodiment 15 differs from embodiment 13 in that: the triode T1 and the triode T2 are respectively of a PNP type and a PNP type, a collector electrode of the triode T1 is connected with the ground through a coil of the relay 2, a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T1, and the logic gate circuit is a logic exclusive-OR gate 4.
In this embodiment 15, through the structure of the transistor T1, the transistor T2, and the transistor T3 and the connection relationship, the following steps are performed:
(A2) when the outputs of the second I/O interface and the third I/O interface are both high level, the output of the logic exclusive-OR gate 4 is high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(B2) when the outputs of the second I/O interface and the third I/O interface are both low level, the output of the logic exclusive-OR gate 4 is high level, so that the triode T2 is turned off, a pair of normally open contacts of the relay 1 cannot be communicated, and therefore misoperation caused by uncertain and uncontrolled I/O state immediately after the microprocessor is started is avoided;
(C2) and when the outputs of the second I/O interface and the third I/O interface are respectively low level and high level or high level and low level, the output of the logic exclusive-OR gate 4 is low level. The difference of the two I/O interfaces indicates that the initialization process of each IO interface is completed after the microprocessor 1 is started, namely, the initialization process is not influenced by the uncertainty of the level of the IO interface when the microprocessor is started, and two switching tubes connected with the coil of the relay 2 in series are not required to be reused for protection;
(D2) when the output of the logic exclusive or nor gate 4 is at a low level, the transistor T2 is turned on. If I/O1 outputs a low, transistor T1 is turned on. At this time, two switch tubes connected in series with the coil of the relay 1 are both conducted, so that the output level of the I/O1 can be used for controlling the connection or disconnection of a pair of normally open contacts of the relay 1.
Examples 16 to 18
Example 16 differs from example 13 in that: the triode T1 and the triode T2 are respectively of PNP type and NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of a coil of the relay 2 and a first power supply end, a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the ground, and the logic gate circuit is a logic exclusive-OR gate 3. The corresponding figures are not shown, and can be obtained by analogy with fig. 4 and 5 (a).
Example 17 differs from example 13 in that: triode T1, triode T2 are PNP type, PNP type respectively, triode T1's collecting electrode, projecting pole correspond the electricity with triode T2's projecting pole, first supply terminal and are connected, triode T2's collecting electrode passes through relay 2 coil and ground electricity connection, the logic gate circuit is logic exclusive-OR gate 4. The corresponding figures are not shown, and can be obtained by analogy with fig. 4 and 5 (a).
Example 18 differs from example 13 in that: the triode T1 and the triode T2 are respectively of an NPN type and an NPN type, a collector electrode of the triode T1 is electrically connected with the first power supply end through a coil of the relay 2, a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and the ground of the triode T1, and the logic gate circuit is a logic exclusive-OR gate 3. The corresponding figures are not shown, and can be obtained by analogy with fig. 4 and 5 (a).
Examples 19 to 24
Example 19 differs from example 13 in that: the first switch tube and the second switch tube are respectively a MOSFET (metal oxide semiconductor field effect transistor) Q1 and a MOSFET Q2, and the grid electrode of each MOSFET is the control end of each MOSFET; the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with one end of the coil of the relay 2 and the ground, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the first power supply end, and the logic gate circuit is a logic exclusive-OR gate 4. The corresponding figures are not shown and can be obtained by analogy with other figures.
Example 20 differs from example 19 in that: the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect transistor Q2, the drain electrode of the MOSFET field effect transistor Q2 is electrically connected with the first power supply end through a relay 2 coil, and the logic gate circuit is a logic exclusive-OR gate 3. The corresponding figures are not shown and can be obtained by analogy with other figures.
Example 21 differs from example 19 in that: the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is connected with the ground through a relay 2 coil, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field effect transistor Q1, and the logic gate circuit is a logic exclusive-OR gate 4.
Example 22 differs from example 19 in that: the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P channel enhancement type and an N channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with one end of the coil of the relay 2 and the first power supply end, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay 2 and the ground, and the logic gate circuit is a logic exclusive-OR gate 3. The corresponding figures are not shown and can be obtained by analogy with other figures.
Example 23 differs from example 19 in that: the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field effect transistor Q2, the drain electrode of the MOSFET field effect transistor Q2 is connected with the ground through a coil of a relay 2, and the logic gate circuit is a logic exclusive-OR gate 4. The corresponding figures are not shown and can be obtained by analogy with other figures.
Example 24 differs from example 19 in that: the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is electrically connected with the first power supply end through a relay 2 coil, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect transistor Q1, and the logic gate circuit is a logic exclusive-OR gate 3. The corresponding figures are not shown and can be obtained by analogy with other figures.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
The embodiments of the present invention have been described in detail, but the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by the present patent. After reading the present invention, modifications of various equivalent forms of the invention by those skilled in the art will fall within the scope of the appended claims. In the case of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other.

Claims (8)

1. A switching value signal control circuit comprises a microprocessor (1), a first switching tube and a relay (2), wherein the microprocessor (1) is provided with a first I/O interface, a second I/O interface and a third I/O interface, the control end of the first switching tube is electrically connected with the first I/O interface, a pair of normally open contacts of the relay (2) is connected in a controlled circuit of the switching value signal control circuit,
the method is characterized in that: the switching value signal control circuit also comprises a second switching tube and a switching tube driving unit, wherein the first switching tube, the second switching tube and a relay (2) coil are electrically connected between the first power supply end and the ground in series;
the switching tube driving unit is provided with a first end electrically connected with the third I/O interface, a second end electrically connected with the control end of the second switching tube and a third end electrically connected with the second I/O interface;
the circuit structure of the switching tube driving unit is characterized in that:
(A) when the output of the second I/O interface and the output of the third I/O interface are both high level, the switching tube driving unit turns off the second switching tube;
(B) when the output of the second I/O interface and the output of the third I/O interface are both low level, the switching tube driving unit turns off the second switching tube;
(C) when the outputs of the second I/O interface and the third I/O interface are respectively a high level and a low level, or when the outputs of the second I/O interface and the third I/O interface are respectively a low level and a high level, or when the outputs of the second I/O interface and the third I/O interface are respectively a high level and a low level and the first switching tube is turned on, or when the outputs of the second I/O interface and the third I/O interface are respectively a low level and a high level and the first switching tube is turned on, the switching tube driving unit turns on the second switching tube.
2. The switching value signal control circuit according to claim 1, wherein: the switch tube driving unit is a third switch tube, and a control end, a connecting end and the other connecting end of the third switch tube are respectively a first end, a second end and a third end of the switch tube driving unit;
the circuit structure of the third switching tube is that:
(A1) when the output of the second I/O interface and the output of the third I/O interface are both high level, the third switch tube is turned off, so that the second switch tube is turned off;
(B1) when the output of the second I/O interface and the output of the third I/O interface are both low level, the third switching tube is turned off, so that the second switching tube is turned off;
(C1) when the output of the second I/O interface and the output of the third I/O interface are respectively at a high level and a low level, or when the output of the second I/O interface and the output of the third I/O interface are respectively at a low level and a high level, the third switching tube is turned on;
(D1) when the third switch tube is conducted, or when the first switch tube and the third switch tube are both conducted, the second switch tube is conducted.
3. The switching value signal control circuit according to claim 2, wherein: the first switch tube, the second switch tube and the third switch tube are respectively a triode T1, a triode T2 and a triode T3, the base electrode of each triode corresponds to the control end of each triode, and the collector electrode and the emitter electrode of the triode T3 are respectively one connecting end and the other connecting end of the triode T3;
(a1) the triode T1, the triode T2 and the triode T3 are respectively NPN type, PNP type and NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and the ground, and a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and a first power supply end; or
(b1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, a collector electrode and an emitter electrode of the triode T1 are respectively and correspondingly electrically connected with an emitter electrode and ground of the triode T2, and a collector electrode of the triode T2 is electrically connected with a first power supply end through a coil of a relay (2); or
(c1) The triode T1, the triode T2 and the triode T3 are respectively of a PNP type, a PNP type and an NPN type, a collector electrode of the triode T1 is connected with the ground through a coil of a relay (2), and a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T1; or
(d1) The triode T1, the triode T2 and the triode T3 are respectively of a PNP type, an NPN type and a PNP type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and a first power supply end, and a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the ground; or
(e1) The triode T1, the triode T2 and the triode T3 are respectively of a PNP type, a PNP type and an NPN type, a collector electrode and an emitter electrode of the triode T1 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T2, and a collector electrode of the triode T2 is electrically connected with the ground through a coil of a relay (2); or
(f1) The triode T1, the triode T2 and the triode T3 are respectively NPN type, NPN type and PNP type, the collector of the triode T1 is electrically connected with the first power supply end through a coil of the relay (2), and the collector and the emitter of the triode T2 are respectively and correspondingly electrically connected with the emitter of the triode T1 and the ground.
4. The switching value signal control circuit according to claim 2, wherein: the first switch tube, the second switch tube and the third switch tube are respectively a MOSFET field effect tube Q1, a MOSFET field effect tube Q2 and a MOSFET field effect tube Q3, the grid electrode of each MOSFET field effect tube is respectively a control end of each MOSFET field effect tube, and the drain electrode and the source electrode of the MOSFET field effect tube Q3 are respectively a connecting end and another connecting end of the MOSFET field effect tube Q3;
(a2) the MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and the ground, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the first power supply end; or
(b2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field-effect tube Q2, and the drain electrode of the MOSFET field-effect tube Q2 is electrically connected with a first power supply end through a relay (2) coil; or
(c2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field-effect tube Q1 is electrically connected with the ground through a relay (2) coil, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field-effect tube Q1; or
(d2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and the first power supply end, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly and electrically connected with the other end of the coil of the relay (2) and the ground; or
(e2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of a P-channel enhancement type, a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field-effect tube Q1 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field-effect tube Q2, and the drain electrode of the MOSFET field-effect tube Q2 is electrically connected with the ground through a coil of the relay (2); or
(f2) The MOSFET field-effect tube Q1, the MOSFET field-effect tube Q2 and the MOSFET field-effect tube Q3 are respectively of an N-channel enhancement type, an N-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field-effect tube Q1 is electrically connected with the first power supply end through a relay (2) coil, and the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field-effect tube Q1.
5. The switching value signal control circuit according to claim 1, wherein: the switch tube driving unit is a logic gate circuit with two logic input ends and one logic output end,
one logic input end, one logic output end and the other logic input end of the logic gate circuit are respectively a first end, a second end and a third end of the logic gate circuit;
the circuit structure of the logic gate circuit is such that:
(A2) when the output of the second I/O interface and the output of the third I/O interface are both high level, the logic gate circuit outputs a first level signal, so that the second switching tube is switched off;
(B2) when the outputs of the second I/O interface and the third I/O interface are both low level, the logic gate circuit outputs a first level signal, so that the second switching tube is switched off;
(C2) when the outputs of the second I/O interface and the third I/O interface are respectively at a high level and a low level, or when the outputs of the second I/O interface and the third I/O interface are respectively at a low level and a high level, the logic gate circuit outputs a second level signal;
(D2) when the logic gate circuit outputs a second level signal, or when the first switch tube is switched on and the logic gate circuit outputs the second level signal, the second switch tube is switched on.
6. The switching value signal control circuit according to claim 5, wherein: the first switch tube and the second switch tube are respectively a triode T1 and a triode T2, and the base electrode of each triode is the control end of each triode;
(a3) the triode T1 and the triode T2 are respectively NPN type and PNP type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and the ground, a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and a first power supply end, and the logic gate circuit is a logic exclusive-OR gate (4); or
(b3) The triode T1 and the triode T2 are respectively NPN type and NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with an emitter and the ground of the triode T2, a collector of the triode T2 is electrically connected with a first power supply end through a coil of a relay (2), and the logic gate circuit is a logic exclusive-OR gate (3); or
(c3) The triode T1 and the triode T2 are respectively of a PNP type and a PNP type, a collector electrode of the triode T1 is electrically connected with the ground through a coil of a relay (2), a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T1, and the logic gate circuit is a logic exclusive-OR gate (4); or
(d3) The triode T1 and the triode T2 are respectively of a PNP type and an NPN type, a collector and an emitter of the triode T1 are respectively and correspondingly electrically connected with one end and a first power supply end of a coil of the relay (2), a collector and an emitter of the triode T2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the ground, and the logic gate circuit is a logic exclusive-OR gate (3); or
(e3) The triode T1 and the triode T2 are respectively of a PNP type and a PNP type, a collector electrode and an emitter electrode of the triode T1 are respectively and correspondingly electrically connected with an emitter electrode and a first power supply end of the triode T2, the collector electrode of the triode T2 is electrically connected with the ground through a coil of a relay (2), and the logic gate circuit is a logic exclusive-OR gate (4); or
(f3) The triode T1 and the triode T2 are respectively of an NPN type and an NPN type, a collector electrode of the triode T1 is electrically connected with a first power supply end through a coil of a relay (2), a collector electrode and an emitter electrode of the triode T2 are respectively and correspondingly electrically connected with an emitter electrode and the ground of the triode T1, and the logic gate circuit is a logic exclusive-OR gate (3).
7. The switching value signal control circuit according to claim 5, wherein: the first switch tube and the second switch tube are respectively a MOSFET (metal oxide semiconductor field effect transistor) Q1 and a MOSFET Q2, and the grid electrode of each MOSFET is the control end of each MOSFET;
(a4) the MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and the ground, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the first power supply end, and the logic gate circuit is a logic exclusive-OR gate (4); or
(b4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with the source electrode and the ground of the MOSFET field effect transistor Q2, the drain electrode of the MOSFET field effect transistor Q2 is electrically connected with the first power supply end through a relay (2) coil, and the logic gate circuit is a logic exclusive-OR gate (3); or
(c4) The MOSFET field-effect tube Q1 and the MOSFET field-effect tube Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode of the MOSFET field-effect tube Q1 is electrically connected with the ground through a relay (2) coil, the drain electrode and the source electrode of the MOSFET field-effect tube Q2 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET field-effect tube Q1, and the logic gate circuit is a logic exclusive-OR gate (4); or
(d4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of a P-channel enhancement type and an N-channel enhancement type, the drain electrode and the source electrode of the MOSFET field effect transistor Q1 are respectively and correspondingly electrically connected with one end of a coil of the relay (2) and a first power supply end, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the other end of the coil of the relay (2) and the ground, and the logic gate circuit is a logic exclusive-OR gate (3); or
(e4) The MOSFET (metal-oxide-semiconductor field effect transistor) Q1 and the MOSFET Q2 are respectively of a P-channel enhancement type and a P-channel enhancement type, the drain electrode and the source electrode of the MOSFET Q1 are respectively and correspondingly electrically connected with the source electrode and the first power supply end of the MOSFET Q2, the drain electrode of the MOSFET Q2 is electrically connected with the ground through a coil of a relay (2), and the logic gate circuit is a logic exclusive-OR gate (4); or
(f4) The MOSFET field effect transistor Q1 and the MOSFET field effect transistor Q2 are respectively of an N-channel enhancement type and an N-channel enhancement type, the drain electrode of the MOSFET field effect transistor Q1 is electrically connected with the first power supply end through a relay (2) coil, the drain electrode and the source electrode of the MOSFET field effect transistor Q2 are respectively and correspondingly electrically connected with the source electrode of the MOSFET field effect transistor Q1 and the ground, and the logic gate circuit is a logic exclusive-OR gate (3).
8. The switching value signal control circuit according to claim 1, wherein: the first power supply end is electrically connected with a positive voltage power supply end of the microprocessor (1).
CN202021136549.0U 2020-06-18 2020-06-18 Switching value signal control circuit Withdrawn - After Issue CN212463187U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111654276A (en) * 2020-06-18 2020-09-11 湖南中科电气股份有限公司 Switching value signal control circuit and control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111654276A (en) * 2020-06-18 2020-09-11 湖南中科电气股份有限公司 Switching value signal control circuit and control method
CN111654276B (en) * 2020-06-18 2024-05-14 湖南中科电气股份有限公司 Switching value signal control circuit and control method

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