CN212412059U - Array substrate and display device - Google Patents
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- CN212412059U CN212412059U CN202020742038.7U CN202020742038U CN212412059U CN 212412059 U CN212412059 U CN 212412059U CN 202020742038 U CN202020742038 U CN 202020742038U CN 212412059 U CN212412059 U CN 212412059U
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Abstract
The utility model discloses an array substrate, including substrate and first thin film transistor, first thin film transistor sets up on the substrate, and first thin film transistor is including setting up first source electrode, first drain electrode and the first gate layer on the substrate, and one of them is surrounded by another to first source electrode and first drain electrode, and first gate layer is located between first source electrode and the first drain electrode. Due to the surrounding relationship between the first source electrode and the first drain electrode of the first thin film transistorPower supply VDDWhen the current is changed, the output current of the first thin film transistor is more constant, and the current I flowing through the light-emitting elementOLEDThe change degree is less, the problem of uneven brightness of the display device can be relieved, the display brightness of the display device is uniform, and the display performance of the display device is improved. The application also provides a display device comprising the array substrate.
Description
Technical Field
The utility model relates to a show technical field, in particular to array substrate and display device.
Background
Organic Light Emitting Diode (OLED) has many excellent characteristics such as wide viewing angle, wide color gamut, high contrast, low power consumption and foldability/flexibility, and has strong competitiveness in display technology, wherein Active-matrix Organic Light Emitting Diode (OLED) or Active-matrix organic light emitting diode (AMOLED) technology is one of the key development directions of current display technology. Currently, some OLED devices employ Low Temperature Polysilicon Oxide (LTPO) display panel technology, which is an LTPO display panel obtained by combining Low Temperature Polysilicon (LTPS) display panel technology and Oxide (Oxide) display panel technology. The LTPO display panel not only has the advantages of high resolution, high reaction speed, high luminance, high aperture ratio, etc. of the LTPS display panel, but also has the advantages of low production cost and low power consumption.
Pixels (pixels) in the LTPO display panel are controlled by Thin Film Transistors (TFTs) in the backplane, which are a composite of metal oxide Thin Film transistors (LTPS TFTs) and low temperature polysilicon Thin Film transistors (IGZO TFTs). Among them, the metal oxide thin film transistor (LTPS TFT) is used as a Switching thin film transistor (Switching TFT) for realizing a Switching function. The low-temperature polysilicon thin film transistor has high mobility, so the low-temperature polysilicon thin film transistor is used as a Driving thin film transistor (Driving TFT) for realizing the Driving of an OLED and improving the luminous brightness.
However, the conventional display panel may have an IR drop (IR drop) phenomenon, which causes a non-uniform current distribution (as shown in fig. 1), and thus the LTPO display panel is prone to have a non-uniform luminance (as shown in fig. 2).
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, the utility model provides an array substrate and display device that can promote luminance homogeneity.
In a first aspect, the present application provides an array substrate, including a substrate and a first thin film transistor, where the first thin film transistor is disposed on the substrate, the first thin film transistor includes a first source, a first drain, and a first gate layer disposed on the substrate, one of the first source and the first drain is surrounded by the other, and the first gate layer is located between the first source and the first drain.
In one embodiment, the first gate layer surrounds one of the first source and the first drain and is surrounded by the other of the first source and the first drain.
In an embodiment, the first thin film transistor further includes a first semiconductor layer, the first semiconductor layer is disposed on a side of the first source and the first drain facing the substrate, the first source and the first drain are both electrically connected to the first semiconductor layer, and the first gate layer is located on a side of the first semiconductor layer facing away from the substrate.
In one embodiment, the first semiconductor layer is a polysilicon semiconductor layer.
In one embodiment, the first thin film transistor further includes a first gate insulating layer disposed between the first semiconductor layer and the first gate layer, the first gate insulating layer surrounding one of the first source electrode and the first drain electrode and surrounded by the other of the first source electrode and the first drain electrode.
In one embodiment, the first thin film transistor further includes a buffer layer disposed between the first semiconductor layer and the substrate.
In an embodiment, the first thin film transistor further includes a first interlayer dielectric layer, the first interlayer dielectric layer covers the first gate layer, the first gate insulating layer, the first semiconductor layer and the buffer layer, a groove is formed in a portion of the first interlayer dielectric layer corresponding to the first source and the first drain, and the first source and the first drain are electrically connected to the first semiconductor layer through the groove.
In an embodiment, the device further includes a passivation layer covering the first source electrode, the first drain electrode and the first interlayer dielectric layer.
In an embodiment, the display device further includes a second thin film transistor, the second thin film transistor is disposed on the substrate and spaced apart from the first thin film transistor, the second thin film transistor includes a second semiconductor layer, a second source and a second drain, the second semiconductor layer is disposed on a side of the substrate facing the first thin film transistor, and the second source and the second drain are spaced apart from a side of the second semiconductor layer facing away from the substrate and electrically connected to the second semiconductor layer.
In one embodiment, the second semiconductor layer is an oxide semiconductor layer.
In one embodiment, the second thin film transistor further includes a second gate layer disposed on a side of the second semiconductor layer facing away from the substrate.
In one embodiment, the second thin film transistor further includes a second gate layer disposed between the second semiconductor layer and the substrate.
In one embodiment, the second thin film transistor further includes a blocking layer, and the second semiconductor layer is disposed between the second gate layer and the blocking layer.
In a second aspect, the present application further provides a display device, including the array substrate.
According to the array substrate and the display device provided by the application, due to the surrounding relation between the first source electrode and the first drain electrode of the first thin film transistor, when the power supply V is usedDDWhen the current is changed, the output current of the first thin film transistor is more constant, and the current I flowing through the light-emitting elementOLEDThe change degree is less, the problem of uneven brightness of the display device can be relieved, the display brightness of the display device is uniform, and the display performance of the display device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic voltage drop diagram of a display panel provided in the prior art.
Fig. 2 is a schematic diagram of a display effect of a display panel provided in the prior art.
Fig. 3 is a schematic plan view of a display device according to a first embodiment of the present application.
Fig. 4 is a schematic circuit diagram of the array substrate shown in fig. 3.
Fig. 5 is a schematic structural view of the array substrate shown in fig. 3.
Fig. 6 is a graph comparing the IV characteristics of the array substrate provided in the present application with the related art.
Fig. 7 is a schematic cross-sectional view of the display device shown in fig. 3.
Fig. 8-11 are schematic cross-sectional views of the display device shown in fig. 3 in various manufacturing steps.
Fig. 12 is a schematic cross-sectional view of a display device according to a second embodiment of the present application.
Fig. 13 is a schematic cross-sectional view of a display device according to a third embodiment of the present application.
Fig. 14-17 are schematic cross-sectional views of the display device shown in fig. 13 at various manufacturing steps.
Fig. 18 is a schematic cross-sectional view of a display device according to a fourth embodiment of the present application.
Fig. 19 is a schematic cross-sectional structure diagram illustrating a manufacturing step of the display device shown in fig. 18.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 3, fig. 3 is a schematic plan view of a display device according to a first embodiment of the present disclosure.
The present application provides a display device 200 including an array substrate 100. It is to be understood that the display device 200 according to the embodiment of the present invention may be used in, but not limited to, a mobile phone, a tablet computer, a palm computer, a Personal Digital Assistant (PDA), an electronic reader, or the like, and the embodiment of the present invention is not limited thereto.
The array substrate 100 includes a substrate 10, a pixel array 20 and a driving circuit 40, and the pixel array 20 and the driving circuit 40 are disposed on the substrate 10. The pixel array 20 is used to display an image. The pixel array 20 includes a plurality of pixel units 30 arranged in an array.
Referring to fig. 4 and 5, fig. 4 is a schematic circuit structure diagram of the array substrate shown in fig. 3. Fig. 5 is a schematic structural view of the array substrate shown in fig. 3.
Each pixel unit 30 includes a light emitting element 31, a first thin film transistor 33, a second thin film transistor 35, and a capacitor 37 disposed on the substrate 10. The second thin film transistor 35 is spaced apart from the first thin film transistor 33, and the second thin film transistor 35 is used as a switching thin film transistor, and is connected between the driving circuit 40 and the first thin film transistor 33 to control whether the second thin film transistor 35 is turned on or off. The first thin film transistor 33 as a driving thin film transistor is connected to a power supply VDDAnd the light emitting element 31, for outputting a drive current to the light emitting element 31. The first thin film transistor 33 includes a first source electrode 337, a first drain electrode 338 and a first gate layer 335 disposed on the substrate 10 (as shown in fig. 3), the first drain electrode 338 is disposed around the first source electrode 337, the first gate layer 335 is disposed between the first source electrode 337 and the first drain electrode 338, that is, the first gate layer 335 is disposed around the first source electrode 337, and the first gate layer 335 is surrounded by the first drain electrode 338. The capacitor 37 is connected between the first gate layer 335 and the first source 337 of the first tft 33.
The present application provides an array substrate 100 andthe display device 200, due to the surrounding relationship between the first source electrode 337 and the first drain electrode 338 of the first TFT 33, when the power source V is appliedDDWhen the current is changed, the output current of the first thin film transistor 33 is more constant, and the current I flowing through the light emitting element 31 is more constantOLEDThe variation degree of (2) is small, the problem of uneven brightness of the display device 200 can be alleviated, the display brightness of the display device 200 is even, and the display performance of the display device 200 is improved. Specifically, as shown in fig. 6, compared to the prior art, the present application includes the first source electrode 337 and the first drain electrode 338 disposed around the first source electrode, so that the current I flowing through the light emitting element 31OLEDRemain substantially unchanged.
In this embodiment, with the stacking direction of the first thin film transistor 33 and the substrate 10 as the first direction, an orthogonal projection of the first source electrode 337 onto the substrate 10 along the first direction is circular, an orthogonal projection of the first gate layer 335 onto the substrate 10 along the first direction is annular and is disposed around the first source electrode 337, and an orthogonal projection of the first drain electrode 338 onto the substrate 10 along the first direction is annular and is disposed around the first gate layer 335.
It is understood that the first drain electrode 338 is not limited to be disposed around the first source electrode 337, for example, in an alternative embodiment, the first source electrode 337 may be disposed around the first drain electrode 338, wherein a projection of the first drain electrode 338 onto the substrate 10 along the first direction is circular, a projection of the first source electrode 337 and the first gate layer 335 onto the substrate 10 along the first direction is annular, the first source electrode 337 is disposed around the first drain electrode 338, the first gate layer 335 surrounds the first drain electrode 337 and is surrounded by the first source electrode 337, that is, one of the first source electrode 337 and the first drain electrode 338 is surrounded by the other, and the first gate layer 335 is disposed between the first source electrode 337 and the first drain electrode 338.
It is to be understood that the shapes of the first source electrode 337, the first drain electrode 338 and the first gate layer 335 are merely exemplary, and the specific shapes of the first source electrode 337, the first drain electrode 338 and the first gate layer 335 are not limited thereto. For example, in the modified embodiment, but not limited to, the projection of the first source electrode 337 onto the substrate 10 along the first direction is rectangular, the projection of the first drain electrode 338 and the first gate layer 335 onto the substrate 10 along the first direction is "mouth" type, and the first gate layer 335 is disposed around the first source electrode 337 and surrounded by the first drain electrode 338. For another example, in an alternative embodiment, but not limited to, the projection of the first drain electrode 338 onto the substrate 10 along the first direction is rectangular, the projection of the first source electrode 337 and the first gate layer 335 onto the substrate 10 along the first direction is "mouth" type, and the first gate layer 335 is disposed around the first drain electrode 338 and surrounded by the first source electrode 337.
In this embodiment, the substrate 10 is a planar rectangular material layer. It is understood that the shape of the substrate 10 is not limited. It is understood that the substrate 10 is not limited to the material of the substrate 10, the substrate 10 can be made of flexible organic material, such as Polyimide (PI) or other materials with similar characteristics, and the substrate 10 can also be made of non-flexible materials, such as glass, quartz, etc.
Referring to fig. 7, fig. 7 is a schematic cross-sectional view of the display device shown in fig. 3.
The first thin film transistor 33 further includes a buffer layer 331, a first semiconductor layer 333, a first gate insulating layer 334, a first interlayer dielectric layer 336 and a passivation layer 339. The buffer layer 331 is disposed between the first semiconductor layer 333 and the substrate 10. The first semiconductor layer 333 is disposed on a side of the first source 337 and the first drain 338 facing the substrate 10, and the first semiconductor layer 333 is a polysilicon semiconductor layer. The first source 337 and the first drain 338 are electrically connected to the first semiconductor layer 333. The first gate layer 335 is located on a side of the first semiconductor layer 333 facing away from the substrate 10. The first gate insulating layer 334 is disposed between the first semiconductor layer 333 and the first gate layer 335. The first gate insulating layer 334 is disposed around the first source electrode 337 and is surrounded by the first drain electrode 338. The first interlayer dielectric layer 336 covers the first gate layer 335, the first gate insulating layer 334, the first semiconductor layer 333 and the buffer layer 331, a groove is formed in a portion of the first interlayer dielectric layer 336 corresponding to the first source electrode 337 and the first drain electrode 338, and the first source electrode 337 and the first drain electrode 338 are electrically connected to the first semiconductor layer 333 through the groove. Specifically, a side of the first gate layer 335 facing the center of the ring is taken as an inner side, and a side of the first gate layer 335 facing away from the center of the ring is taken as an outer side. The first interlayer dielectric layer 336 is provided with a first groove 3361 corresponding to the inner side of the first gate layer 335, and the first interlayer dielectric layer 336 is provided with a second groove 3363 corresponding to the outer side of the first gate layer 335. The first source electrode 337 is fixedly received in the first recess 3361 and electrically connected to the first semiconductor layer 333. The first drain electrode 338 is fixedly received in the second recess 3363 and electrically connected to the first semiconductor layer 333. The passivation layer 339 covers the first source electrode 337, the first drain electrode 338 and the first interlayer dielectric layer 336.
It is to be understood that the first semiconductor layer 333 is not limited to a polysilicon semiconductor layer. It is understood that the first gate insulating layer 334 is not limited to be disposed around the first source electrode 337 and surrounded by the first drain electrode 338, for example, in a modified embodiment, when the first source electrode 337 is disposed around the first drain electrode 338, the first gate insulating layer 334 may be disposed around the first drain electrode 338 and surrounded by the first source electrode 337.
In this embodiment, an orthogonal projection of the second thin film transistor 35 on the substrate 10 along the first direction is square. The second thin film transistor 35 includes a second semiconductor layer 351, a second gate insulating layer 353, a second gate layer 354, a second interlayer dielectric layer 356, a second source electrode 357, a second drain electrode 358, and a third interlayer dielectric layer 359. The second semiconductor layer 351 is an oxide semiconductor layer. The second semiconductor layer 351 is disposed on a side of the passivation layer 339 facing away from the substrate 10. The second gate insulating layer 353 and the second gate layer 354 are sequentially stacked on the second semiconductor layer 351 on a side away from the substrate 10. The second interlayer dielectric layer 356 covers the second gate layer 354, the second gate insulating layer 353, the second semiconductor layer 351 and the passivation layer 339. The portion of the second interlayer dielectric layer 356 corresponding to the second source 357 and the second drain 358 is formed with a via 3561, and the second source 357 and the second drain 358 are disposed at an interval on a side of the second semiconductor layer 351 away from the substrate 10 and are electrically connected to the second semiconductor layer 351 through the via 3561. The third interlayer dielectric layer 359 covers the passivation layer 339, the second interlayer dielectric layer 356, the second source electrode 358, and the second drain electrode 357.
It is to be understood that the shape of the orthographic projection of the second thin film transistor 35 on the substrate 10 in the first direction is not limited. The second semiconductor layer 351 is not limited to an oxide semiconductor layer.
The array substrate 100 and the display device 200 provided by the present application can not only improve the uniformity of the brightness of the display panel, but also reduce the size of the pixels, and correspondingly improve the resolution of the display device 200, so as to improve the advantages of the Low Temperature Polycrystalline Oxide (LTPO) display panel technology in the flexible OLED.
The present application also provides a method of manufacturing the array substrate 100:
step S1, as shown in fig. 8, providing a substrate 10, and depositing a buffer layer 331 on the substrate 10; depositing a monocrystalline silicon (A-Si) material and patterning; crystallizing the single crystal silicon (a-Si) material to form a polycrystalline silicon (Poly-Si) semiconductor layer, that is, a first semiconductor layer 333; depositing an insulating material on the first semiconductor layer 333 and patterning the insulating material to form a ring-shaped first gate insulating layer 334; a metal material is deposited on the first gate insulating layer 334 and patterned to form a ring-shaped first gate layer 335.
Step S5, as shown in fig. 9, depositing an insulating material on the first gate layer 335, the first gate insulating layer 334, the first semiconductor layer 333 and the buffer layer 331, and patterning the insulating material to form a first interlayer dielectric layer 336; and a first groove 3361 is provided in a region of the first interlayer dielectric layer 336 corresponding to an inner side (a side facing a circular center) of the first gate layer 335, and a second groove 3363 is provided in a region of the first interlayer dielectric layer 336 corresponding to an outer side (a side facing away from the circular center) of the first gate layer 335, so as to expose a portion of the first semiconductor layer 333. A metal material is deposited and patterned on the first interlayer dielectric layer 336 to form a circular first source electrode 337 and a circular first drain electrode 338, wherein the first source electrode 337 is located in the first recess 3361 and connected to the first semiconductor layer 333, and the first drain electrode 338 is located in the second recess 3363 and connected to the first semiconductor layer 333.
In step S3, as shown in fig. 10, a polyvinyl chloride (PV) material is deposited on the first interlayer dielectric layer 336, the first source electrode 337 and the first drain electrode 338 to form a passivation layer 339. An Oxide semiconductor material, such as, but not limited to, Indium Gallium Zinc Oxide (IGZO), Zinc Oxide (ZnO), Indium Oxide (InO), Gallium Oxide (GaO), or a mixture including the same, is deposited on the passivation layer 339 and patterned to form the second semiconductor layer 351.
Step S4, as shown in fig. 11, depositing an insulating material on the second semiconductor layer 351 and patterning the insulating material to form a second gate insulating layer 353; a metal material is deposited on the second gate insulating layer 353 and patterned to form a second gate layer 354. An insulating material is deposited on the second gate layer 354, the second gate insulating layer 353, the second semiconductor layer 351 and the passivation layer 339 to form a second interlayer dielectric layer 356, and a through hole 3561 is formed in a region of the second interlayer dielectric layer 356 corresponding to the second source electrode 357 and the second drain electrode 358, so that a portion of the second semiconductor layer 351 is exposed. A metal material is deposited on the second interlayer dielectric layer 356 and patterned to form a second source 357 and a second drain 358, wherein the second source 357 and the second drain 358 are connected to the second semiconductor layer 351 through the via 3561.
In step S5, as shown in fig. 7, a third interlayer dielectric layer 359 is deposited on the second source electrode 357, the second drain electrode 358, the second interlayer dielectric layer 356 and the passivation layer 339.
Second embodiment
Referring to fig. 12, fig. 12 is a schematic cross-sectional structure view of a display device according to a second embodiment of the present disclosure.
The display device 500 according to this embodiment is different from the display device according to the first embodiment in that the positions of the first source 537 and the first drain 538 are reversed, that is, the first source 537 is disposed around the first drain 538. The first gate layer 535 and the first gate insulating layer 534 are disposed around the first drain electrode 538 and are surrounded by the first source electrode 537. Specifically, the first source electrode 537 is annularly shaped along the orthographic projection of the first direction on the substrate 510, and the first source electrode 537 is fixedly accommodated in the second recess 5363 of the first interlayer dielectric layer 536 and electrically connected to the first semiconductor layer 533. The first drain 538 is circular in shape as an orthographic projection along the first direction on the substrate 510, and the first drain 538 is fixedly received in the first groove 5361 of the first interlayer dielectric layer 536 and electrically connected to the first semiconductor layer 533.
Third embodiment
Referring to fig. 13, fig. 13 is a schematic cross-sectional structure view of a display device according to a third embodiment of the present application.
The array substrate 600 provided in this embodiment is different from the first embodiment in that the second gate insulating layer and the second interlayer dielectric layer are omitted, and the second gate layer 654 is disposed between the second semiconductor layer 651 and the substrate 610.
The present embodiment also provides a method of manufacturing the array substrate 600:
step S1, as shown in fig. 14, providing a substrate 610, and depositing a buffer layer 631 on the substrate 610; depositing a monocrystalline silicon (A-Si) material and patterning; crystallizing the single crystal silicon (a-Si) material to form a polycrystalline silicon (Poly-Si) semiconductor layer, i.e., the first semiconductor layer 633; depositing an insulating material on the first semiconductor layer 633 and patterning the insulating material to form a ring-shaped first gate insulating layer 634; a metal material is deposited on the first gate insulating layer 634 and patterned to form a ring-shaped first gate layer 635.
Step S2, as shown in fig. 15, depositing an insulating material on the first gate layer 635, the first gate insulating layer 634, the first semiconductor layer 633 and the buffer layer 631, and patterning the insulating material to form a first interlayer dielectric layer 636; a first groove 661 is disposed in a region of the first interlayer dielectric layer 636 corresponding to an inner side (a side facing a circular center) of the first gate layer 635, and a second groove 663 is disposed in a region of the first interlayer dielectric layer 636 corresponding to an outer side (a side facing away from the circular center) of the first gate layer 635, so as to expose a portion of the first semiconductor layer 633. Depositing a metal material on the first interlayer dielectric layer 636 and patterning the metal material to form a circular first source 637 and a ring-shaped first drain 638, wherein the first source 637 is located in the first groove 661 and connected to the first semiconductor layer 633, and the first drain 638 is located in the second groove 663 and connected to the first semiconductor layer 633; a metal material is deposited and patterned on the first interlayer dielectric layer 636 to form a second gate layer 654.
In step S3, as shown in fig. 16, a polyvinyl chloride (PV) material is deposited on the first interlayer dielectric layer 636, the first source electrode 637, the first drain electrode 638 and the second gate electrode layer 654 to form a passivation layer 639. An Oxide semiconductor material, such as, but not limited to, Indium Gallium Zinc Oxide (IGZO), Zinc Oxide (ZnO), Indium Oxide (InO, Gallium Oxide (GaO), or a mixture including the same, is deposited on the passivation layer 639 and patterned to form the second semiconductor layer 651.
In step S4, as shown in fig. 17, a metal material is deposited over the second semiconductor layer 651 and patterned to form a second source electrode 657 and a second drain electrode 658, and the second source electrode 657 and the second drain electrode 658 are connected to the second semiconductor layer 651.
In step S10, as shown in fig. 13, a third interlayer dielectric layer 659 is deposited on the second semiconductor layer 651, the second source electrode 657, the second drain electrode 658 and the passivation layer 639.
Fourth embodiment
Referring to fig. 18, fig. 18 is a schematic cross-sectional structure view of a display device according to a fourth embodiment of the present application.
The array substrate 700 provided in this embodiment is different from the third embodiment in that the array substrate further includes a barrier layer 770, and the second semiconductor layer 751 is disposed between the second gate layer 754 and the barrier layer 770.
The present embodiment also provides a method for manufacturing an array substrate 700, which is different from the method for manufacturing an array substrate of the third embodiment in that: in the present application, as shown in fig. 19, after an oxide semiconductor material is deposited and patterned on a passivation layer 739 to form a second semiconductor layer 751, a barrier layer 770 is further formed on the second semiconductor layer 751. Then, a metal material is deposited over the second semiconductor layer 751, the passivation layer 739, and the barrier layer 770 and patterned to form a second source electrode 757 and a second drain electrode 758, and the second source electrode 757 and the second drain electrode 758 are connected to the second semiconductor layer 751. Finally, as shown in fig. 18, a third interlayer dielectric layer 759 is deposited over the second semiconductor layer 751, the second source electrode 757, the second drain electrode 758, and the passivation layer 739.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.
Claims (14)
1. An array substrate comprises a substrate and a first thin film transistor, wherein the first thin film transistor is arranged on the substrate, the first thin film transistor comprises a first source electrode, a first drain electrode and a first gate layer, the first source electrode, the first drain electrode and the first gate layer are arranged on the substrate, one of the first source electrode and the first drain electrode is surrounded by the other, and the first gate layer is located between the first source electrode and the first drain electrode.
2. The array substrate of claim 1, wherein the first gate layer surrounds one of the first source and the first drain and is surrounded by the other of the first source and the first drain.
3. The array substrate of claim 2, wherein the first thin film transistor further comprises a first semiconductor layer disposed on a side of the first source and the first drain facing the substrate, the first source and the first drain are both electrically connected to the first semiconductor layer, and the first gate layer is disposed on a side of the first semiconductor layer facing away from the substrate.
4. The array substrate of claim 3, wherein the first semiconductor layer is a polysilicon semiconductor layer.
5. The array substrate of claim 3, wherein the first thin film transistor further comprises a first gate insulating layer disposed between the first semiconductor layer and the first gate layer, the first gate insulating layer surrounding one of the first source and the first drain and surrounded by the other of the first source and the first drain.
6. The array substrate of claim 5, wherein the first thin film transistor further comprises a buffer layer disposed between the first semiconductor layer and the substrate.
7. The array substrate of claim 6, wherein the first thin film transistor further comprises a first interlayer dielectric layer, the first interlayer dielectric layer covers the first gate layer, the first gate insulating layer, the first semiconductor layer and the buffer layer, a groove is formed in a portion of the first interlayer dielectric layer corresponding to the first source and the first drain, and the first source and the first drain are electrically connected to the first semiconductor layer through the groove.
8. The array substrate of claim 7, further comprising a passivation layer covering the first source electrode, the first drain electrode and the first interlayer dielectric layer.
9. The array substrate of claim 1, further comprising a second thin film transistor disposed on the substrate and spaced apart from the first thin film transistor, wherein the second thin film transistor comprises a second semiconductor layer disposed on a side of the substrate facing the first thin film transistor, a second source and a second drain, the second source and the second drain being spaced apart from a side of the second semiconductor layer facing away from the substrate and electrically connected to the second semiconductor layer.
10. The array substrate of claim 9, wherein the second semiconductor layer is an oxide semiconductor layer.
11. The array substrate of claim 9, wherein the second thin film transistor further comprises a second gate layer disposed on a side of the second semiconductor layer facing away from the substrate.
12. The array substrate of claim 9, wherein the second thin film transistor further comprises a second gate layer disposed between the second semiconductor layer and the substrate.
13. The array substrate of claim 12, wherein the second thin film transistor further comprises a blocking layer, and the second semiconductor layer is disposed between the second gate layer and the blocking layer.
14. A display device comprising the array substrate according to any one of claims 1 to 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020742038.7U CN212412059U (en) | 2020-05-07 | 2020-05-07 | Array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020742038.7U CN212412059U (en) | 2020-05-07 | 2020-05-07 | Array substrate and display device |
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| CN212412059U true CN212412059U (en) | 2021-01-26 |
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