CN212367617U - Integrated circuit substrate - Google Patents

Abstract

An integrated circuit substrate. The integrated circuit substrate includes: an auxiliary positioning structure and an offset detection structure. The auxiliary positioning structure is used for defining a drilling position. The offset detection structure is arranged on the auxiliary positioning structure and is symmetrically arranged relative to the center of the auxiliary positioning structure.

Description

Integrated circuit substrate

Technical Field

The present application relates generally to devices, and more particularly to an integrated circuit substrate.

Background

Conventionally, when drilling a circuit board, especially a multilayer circuit board, since the drilling position is covered by an upper insulating layer (e.g. resin) and a conductive layer (e.g. copper layer), it is impossible to effectively detect whether the drilling position is deviated from a predetermined position.

SUMMERY OF THE UTILITY MODEL

In view of the above, an object of the present invention is to provide an integrated circuit substrate.

According to an embodiment of the present application, an integrated circuit substrate is disclosed. The integrated circuit substrate includes: an auxiliary positioning structure and an offset detection structure. The auxiliary positioning structure is used for defining a drilling position. The offset detection structure is arranged on the auxiliary positioning structure and is symmetrically arranged relative to the center of the auxiliary positioning structure.

According to an embodiment of the present application, the auxiliary positioning structure and the offset detecting structure are etching structures, and the offset detecting structure includes two auxiliary lines disposed symmetrically to the center of the auxiliary positioning structure.

According to an embodiment of the present application, the two auxiliary lines are two parallel lines extending in the first direction.

According to an embodiment of the present disclosure, the line width of each auxiliary line is in a range of 0.075 to 0.085 mm.

According to an embodiment of the present application, the line width of each auxiliary line is 0.08 mm.

According to an embodiment of the present application, a line pitch of the two auxiliary lines is a sum of a drilling diameter, a line width of half of each of the two auxiliary lines, and an amount of undercut generated in a second direction when the two auxiliary lines are etched, less a maximum offset allowed in the second direction, wherein the first direction is perpendicular to the second direction.

According to an embodiment of the present application, an integrated circuit substrate is disclosed. The integrated circuit substrate includes: the semiconductor device comprises a substrate, a first conducting layer, an insulating layer, a second conducting layer and a through hole. The first conductive layer is formed on the substrate. The first conductive layer includes: an auxiliary positioning structure and an offset detection structure. The auxiliary positioning structure is used for defining a drilling position. The offset detection structure is arranged on the auxiliary positioning structure and is symmetrically arranged relative to the center of the auxiliary positioning structure. The insulating layer is formed over the first conductive layer. The second conductive layer is formed over the insulating layer. The through hole penetrates through the substrate, the first conductive layer, the insulating layer and the second conductive layer.

According to an embodiment of the present application, the auxiliary positioning structure surrounds the through hole.

According to an embodiment of the present application, the offset detection structure partially overlaps the via.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:

FIG. 1 is a top view of an integrated circuit substrate according to one embodiment of the present application.

Fig. 2 is a top view of a patterned structure according to an embodiment of the present application.

Fig. 3A-3E are flow diagrams of fabricating an integrated circuit substrate according to an embodiment of the present application.

Fig. 4 is a top view of a patterned conductive layer after a drilling operation according to one embodiment of the present application.

FIG. 5 is a flow chart of a method of fabricating an integrated circuit substrate according to an embodiment of the present application.

Detailed Description

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains.

It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.

A conventional multilayer circuit board (e.g., a four-layer circuit board) includes a substrate (e.g., a BT board) in the middle, first conductive layers (e.g., copper layers) formed on upper and lower sides of the substrate, insulating layers (e.g., resin) formed on upper and lower sides of the first conductive layers, and second conductive layers (e.g., copper layers) formed on upper and lower sides of the insulating layers. Conventionally, when drilling a multi-layer circuit board, a portion of a conductive material (e.g., copper) is removed by etching from a first conductive layer (e.g., a copper layer), thereby forming a patterned conductive layer, and a patterned structure in the patterned conductive layer is used as a target for drilling.

Then, an insulating layer and a second conductive layer are sequentially formed on the patterned conductive layer. When the drilling operation is to be performed, the patterned conductive layer covered with the insulating layer and the second conductive layer is observed by X-rays to confirm the position of the patterned structure as a target, and then the drilling operation is performed. The horizontal deviation of the drilled holes using the conventional patterning structure is easy to observe and allowable, however, it is not effective to detect whether the drilled hole position is deviated in the vertical direction. Therefore, the present application provides an integrated circuit substrate to solve the above problems.

Fig. 1 is a top view of an integrated circuit substrate 1 according to an embodiment of the present application. In some embodiments, the integrated circuit substrate 1 is a multilayer circuit board. In some embodiments, the integrated circuit substrate 1 is a four-layer circuit board. The integrated circuit substrate 1 includes a substrate (not shown) in the middle and conductive layers 10 formed on the upper and lower sides of the substrate. In certain embodiments, the substrate may be a BT substrate and the conductive layer 10 may include copper.

As described above, the integrated circuit substrate 1 may further include an insulating layer formed on both upper and lower sides of the conductive layer 10 and another conductive layer formed on both upper and lower sides of the insulating layer. Fig. 1 depicts only a part related to the inventive spirit of the present application for convenience of explanation.

The conductive layer 10 includes patterned structures 11 and 12. In some embodiments, the patterned structures 11 and 12 are located at the middle of the left and right sides of the integrated circuit substrate 1. The patterned structures 11 and 12 serve as targets to define drilling locations, wherein the patterned structures 11 and 12 are horizontally symmetric structures. In some embodiments, the patterned structures 11 and 12 are formed by etching the conductive layer 10.

Fig. 2 is a top view of a patterned structure 11 according to an embodiment of the present application. Since the patterned structure 11 and the patterned structure 12 are horizontally symmetrical, the following embodiments are only exemplified by the patterned structure 11, and those skilled in the art should easily extend the structure to the patterned structure 12.

The patterned structure 11 includes an auxiliary positioning structure 21, a main positioning structure 22 and an offset detecting structure 23. The auxiliary positioning structure 21 and the main positioning structure 22 are used to define the drilling position. In detail, the primary positioning structure 22 serves as a target bulls-eye to mark the drill hole location. The secondary positioning structure 21 surrounds the primary positioning structure 22 and the secondary positioning structure 21 is arranged concentrically with the primary positioning structure 22. Thus, the auxiliary positioning structure 21 may be considered as a boundary of the drill position, in other words, the auxiliary positioning structure 21 may define a maximum offset of the drill position.

The offset detecting structure 23 is disposed on the auxiliary positioning structure 21 and is symmetrically disposed with respect to the centers of the main positioning structure 22 and the auxiliary positioning structure 21. In detail, the deviation detecting structure 23 includes auxiliary lines 231 and auxiliary lines 232 symmetrically disposed with respect to the center of the auxiliary positioning structure 21. The auxiliary line 231 and the auxiliary line 232 extend in the first direction (x-axis direction) and are parallel. In some embodiments, the width of the auxiliary lines 231 and 232 is in the range of 0.075-0.085 mm. Preferably, the line widths of the auxiliary lines 231 and 232 are 0.08 mm.

In some embodiments, the auxiliary positioning structure 21, the main positioning structure 22 and the offset detection structure 23 are formed by etching. Due to the isotropic nature of the etching, lateral etching occurs during the etching of the auxiliary positioning structure 21, the main positioning structure 22 and the offset detection structure 23. In some embodiments, the line pitch (i.e., the distance from the line center to the line center) of the auxiliary lines 231 and 232 is designed to be the sum of the diameter of the drilled hole, the line width of each half of the auxiliary lines 231 and 232 (i.e., the line width of a single auxiliary line), and the amount of undercut generated in the second direction (y-axis direction) when etching the auxiliary lines 231 and 232, minus the maximum allowable offset in the second direction (y-axis direction).

It should be noted that, in the present embodiment, the auxiliary positioning structure 21 and the main positioning structure 22 are concentric structures. In some embodiments, the aperture of the primary positioning structure 22 is 3.15 mm. However, this is not a limitation of the present application. In other embodiments, the secondary positioning structure 21 and the primary positioning structure 22 may be other shapes that are concentrically arranged.

Fig. 3A-3E are flow diagrams of fabricating an integrated circuit substrate according to an embodiment of the present application. In some embodiments, the process flow illustrated in fig. 3A-3E may be used to implement the integrated circuit substrate 1 of fig. 1. It should be noted that the flow shown in fig. 3A to 3E only depicts the portion of the integrated circuit substrate relevant to the spirit of the present invention.

In fig. 3A, a conductive layer 31 is formed over a substrate 30. In addition, the conductive layer 31' is formed below the substrate 30. In certain embodiments, substrate 30 is a BT board and conductive layers 31 and 31' comprise copper.

In fig. 3B, the conductive layer 31 is etched to produce a patterned conductive layer 32. The patterned conductive layer 32 includes an auxiliary positioning structure 321, a main positioning structure 322, and an offset detection structure 323, wherein the offset detection structure 323 includes auxiliary lines 3231 and 3232. Similarly, the conductive layer 31 'is etched to produce a patterned conductive layer 32'. The patterned conductive layer 32 ' includes an auxiliary positioning structure 321 ', a main positioning structure 322 ', and an offset detection structure 323 ', wherein the offset detection structure 323 ' includes auxiliary lines 3231 ' and 3232 '. The assistant positioning structures 321 and 321 ', the main positioning structures 322 and 322 ', and the offset detection structures 323 and 323 ' are the same as the corresponding components shown in fig. 2, and the detailed description is omitted here.

In fig. 3C, an insulating layer 33 is formed over the patterned conductive layer 32, and an insulating layer 33 'is formed under the patterned conductive layer 32'. In some embodiments, the insulating layers 33 and 33' comprise a resin.

In fig. 3D, a conductive layer 34 is formed over the insulating layer 33, and a conductive layer 34 'is formed under the insulating layer 33'. In certain embodiments, conductive layers 34 and 34' comprise copper.

In fig. 3E, the positions of the auxiliary positioning structure 321, the main positioning structure 322 and the offset detecting structure 323 are observed by irradiating X-rays, and drilling is performed according to the target position represented by the main positioning structure 322 to generate the through hole 35.

Fig. 4 is a top view of the patterned conductive layer 32 after a drilling operation according to one embodiment of the present application. As shown in FIG. 4, the auxiliary positioning structure 321 surrounds the through hole 35, and the offset detection structure 323 partially overlaps the through hole 35. Whether the via 35 is shifted in the second direction (i.e., the y-axis direction) can be determined according to the overlap between the shift detection structure 323 and the via 35. Taking the embodiment of fig. 4 as an example, the through holes 35 are trimmed from the auxiliary lines 3231 and partially overlap the auxiliary lines 3232. As can be seen, the through hole 35 is offset downward.

FIG. 5 is a flow chart of a method 50 of fabricating an integrated circuit substrate according to one embodiment of the present application. In some embodiments, the integrated circuit substrate manufacturing method 50 may be used to implement the integrated circuit substrate 1 of fig. 1. The present application is not limited to being performed solely in accordance with the process steps illustrated in fig. 5, provided that substantially the same results are achieved. The integrated circuit substrate manufacturing method 50 can be summarized as follows:

step 51: a first conductive layer is formed on a substrate.

Step 52: the first conductive layer is etched to generate a patterned conductive layer, the patterned conductive layer includes an auxiliary positioning structure and an offset detection structure, the auxiliary positioning structure is used for defining a drilling position, and the offset detection structure is arranged on the auxiliary positioning structure and symmetrically arranged relative to the center of the auxiliary positioning structure.

Step 53: an insulating layer and a second conductive layer are sequentially formed on the patterned conductive layer.

Step 54: and drilling the center positions of the insulating layer and the second conducting layer corresponding to the auxiliary positioning structures to generate through holes.

Step 55: and judging whether the through hole deviates or not according to the through hole and the deviation detecting structure.

The details of the integrated circuit substrate manufacturing method 50 will be readily understood by those skilled in the art after reading the above embodiments, and the detailed description is omitted here for brevity.

Claims (9)

1. An integrated circuit substrate, comprising:

the auxiliary positioning structure is used for defining the position of the drilling hole; and

and the offset detection structure is arranged on the auxiliary positioning structure and is symmetrically arranged relative to the center of the auxiliary positioning structure.

2. The integrated circuit substrate of claim 1, wherein the auxiliary positioning structure and the offset detecting structure are etched structures, and the offset detecting structure comprises two auxiliary lines disposed symmetrically to the center of the auxiliary positioning structure.

3. The integrated circuit substrate of claim 2, wherein the two auxiliary lines are two parallel lines extending in the first direction.

4. The integrated circuit substrate of claim 3, wherein the width of each auxiliary line is in the range of 0.075-0.085 mm.

5. The integrated circuit substrate according to claim 4, wherein the line width of each auxiliary line is 0.08 mm.

6. The integrated circuit substrate of claim 3, wherein the line pitch of the two auxiliary lines is a sum of a drilling diameter, a line width of half of each of the two auxiliary lines, and an amount of undercut generated in a second direction when the two auxiliary lines are etched, less a maximum offset allowed in the second direction, wherein the first direction is perpendicular to the second direction.

7. An integrated circuit substrate, comprising:

a substrate;

a first conductive layer formed on the substrate, comprising:

the auxiliary positioning structure is used for defining the position of the drilling hole; and

the offset detection structure is arranged on the auxiliary positioning structure and is symmetrically arranged relative to the center of the auxiliary positioning structure;

an insulating layer formed over the first conductive layer;

a second conductive layer formed over the insulating layer; and

a via hole penetrating the substrate, the first conductive layer, the insulating layer, and the second conductive layer.

8. The integrated circuit substrate of claim 7, wherein the auxiliary positioning structure surrounds the via.

9. The integrated circuit substrate of claim 7, wherein the offset detection structure partially overlaps the via.

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