CN212367112U - Programmable direct current power supply - Google Patents
Programmable direct current power supply Download PDFInfo
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- CN212367112U CN212367112U CN202021585089.XU CN202021585089U CN212367112U CN 212367112 U CN212367112 U CN 212367112U CN 202021585089 U CN202021585089 U CN 202021585089U CN 212367112 U CN212367112 U CN 212367112U
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Abstract
The utility model discloses a direct current power supply able to programme, which comprises an outer shell, the front side of shell is equipped with the front panel, and this front panel has a display screen that shows user interface, the display screen downside is equipped with the auxiliary function soft key that is used for the menu to show, and the display screen left side is equipped with the USBHost interface that allows external USB driver to be connected to equipment, provides multichannel voltage output, and total output power is up to 200W, and each channel output is separately controllable; the voltage-stabilizing and current-stabilizing values of the 1 and 2 paths are adjustable in a stepping mode, two working states of voltage stabilization and current stabilization can be automatically switched along with the change of a load, the outputs of the 1 and 2 paths can be connected in series, in parallel and independently work, and the 3 rd path provides four selectable output voltages of 1.8V, 2.5V, 3.3V and 5V.
Description
Technical Field
The utility model relates to a measure technical field, specifically be a DC power supply able to programme.
Background
The direct current power supply is provided with a positive electrode and a negative electrode, the positive electrode has high potential, the negative electrode has low potential, and when the two electrodes are communicated with the circuit, constant potential difference can be maintained between the two ends of the circuit, so that current from the positive electrode to the negative electrode is formed in the external circuit;
the direct current power supply in the current market needs different channel interfaces for input and output, so that the number of input channels or output channels which can be set in an operation panel is too small, and the use requirements of users cannot be met; in addition, the current direct-current power supply technology is not intelligent enough, when multiple channels are needed to realize output simultaneously, quick and convenient synchronous and multi-channel common output cannot be provided, and the output can be realized by using multiple direct-current power supplies together, so that poor experience is brought to users, and the use is inconvenient;
the prior art can not meet the requirements of people at the present stage, and the prior art is urgently needed to be reformed based on the current situation.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a dc power supply able to programme to solve the problem that proposes among the above-mentioned background art.
The utility model provides a following technical scheme direct current power supply able to programme, including the shell, the front side of shell is equipped with the front panel, and this front panel has a display screen that shows user interface, the display screen downside is equipped with the auxiliary function soft key that is used for the menu to show, and the display screen left side is equipped with the USB Host interface that allows external USB driver to be connected to equipment;
the right side of the display screen is provided with a function key, a direction key and a numeric keyboard;
preferably, the function keys include: a Meter View key for displaying a selected channel Meter View, a Tracking key for turning on or off a second group of output channels, a third group of output channel Tracking mode, a Store/Recall key for turning on a save or call menu, and an Enter key for determining a selection;
preferably, the direction key includes: an up key, a down key, a left key, and a right key for moving a cursor position;
preferably, the numeric keypad includes: a number key, a decimal key and a delete key for directly inputting numerical values;
preferably, the front panel is further provided with a set of adjusting knobs, and the adjusting knobs comprise: a voltage regulating knob for regulating voltage with unit precision of 1MV and a current regulating knob for regulating current with unit precision of 1 MA;
a power switch is independently arranged at the lower left corner of the front panel;
the front panel is also provided with four groups of output channels, and the four groups of output channels are respectively: a first group of output channels, a second group of output channels, a third group of output channels and a fourth group of output channels;
preferably, each of the four sets of output channels comprises: the device comprises a positive output terminal, a negative output terminal, a selection key and a channel output control key;
preferably, ALL ON/OFF keys and a common ground terminal for fully opening or fully closing ALL output channels are arranged between the second group of output channels and the third group of output channels from top to bottom;
the rear side of shell is equipped with interface panel, interface panel includes: LAN interface for accessing local area network, USB Device interface for connecting computer, RS-232 interface for serial communication, DIO digital IO interface for input/output, AC voltage selection switch, GPIB interface for universal bus connection, power supply interface and exhaust fan;
preferably, the LAN interface is accessed to a local area network through an RJ-45 interface, and is remotely controlled through a computer;
preferably, the USB Device interface is connected with a computer through a USB interface, and sends an SCPI command or self-defined programming control through upper computer software;
preferably, the DIO digital IO interface is used for external equipment, and can be used as an output interface or an input interface;
preferably, the voltage steps selectable by the alternating voltage selection switch are 100V, 120V, 220V and 240V;
the output modes of the first group of output channels, the second group of output channels, the third group of output channels and the fourth group of output channels all comprise: constant current output and constant voltage output;
preferably, in the constant current output, the output current is equal to the set current value, and the output voltage value is equal to the current set value multiplied by the load resistance value, and when the load voltage exceeds the set voltage value, the constant voltage output is performed.
Preferably, the output voltage is equal to a set voltage value when the constant voltage output is performed, the output current value is equal to a voltage set value divided by a load resistance value, and the constant current output is performed when the load current exceeds the set current value.
Preferably, the DIO digital IO interface is electrically connected with a Sense terminal, and the Sense terminal detects output voltage when the DIO digital IO interface is used as an output interface and feeds the output voltage back to the MCU for verification; when a DIO digital IO interface of the rear panel is selected for constant voltage output, the Sense terminal can automatically compensate voltage drop caused by a load lead, the output configuration is divided into two-wire induction and four-wire induction, and the value measured by the four-wire induction relative to the two-wire induction is more accurate, so that the set power output value is ensured to be consistent with the voltage obtained by the load.
Preferably, the channel output has a plurality of output control modes, including:
outputting over-protection delay, wherein each channel has over-protection and delay functions, the delay time is set to be 0-3600s, and the step is 1 ms; the power supply ignores the CC (constant current) output state during the delay period of the OCP (over current protection), and if the delay time is over, the output state is still CC, the output is forbidden; if the output voltage reaches a voltage protection value, the output state of the channel is changed from CV (constant voltage) to OV (overvoltage), and the channel is set to be forbidden to output; and if the output current reaches the current protection value, the output state of the channel is changed from CV to CC, and the channel is set to be forbidden to output.
And coupling the output, wherein the delayed output of a single channel or a plurality of channels can be selected to be coupled with the output of a plurality of channels. The auxiliary function soft key is provided with an on/off coupling key, channels needing coupling output can be started through the on/off coupling key, any one of the channel outputs is opened after the coupling output is started, and the rest coupling channels are opened at the same time; when only partial channel output coupling is started, ALL ON/OFF keys of the front panel are turned ON, and ALL channels turn ON the output regardless of whether the channels enable switch coupling or not; when a single channel is output, no channel coupling is required.
A multi-mode operational output, said auxiliary function soft key having an operational mode key therein which selects an independent, series, parallel and tracking operational mode for a first set of output channels and a second set of output channels; wherein the content of the first and second substances,
when the operation mode is the independent operation mode, the channels are independently output without mutual influence, and the output voltage or current is the set voltage and the set current of each channel;
when the operation mode is a series operation mode, the 1+ port wiring terminal of the first group of output channels and the 2-port wiring terminal of the second group of output channels are two output terminals of the series output circuit, the output voltage is 2 times of the set voltage of the first group of output channels, and the output current is the set current of the first group of output channels; the output ends of the SERIES output circuits in the first group of output channels and the second group of output channels are connected in SERIES to form single SERIES channel output, at the moment, the window of the second group of output channels of the main interface displays 'SERIES with CH 1', namely the first group of output channels are output by the main channel, and the second group of output channels are output by the slave channel;
when the operation mode is the parallel operation mode, the 1+ port wiring terminal and the 1-port wiring terminal of the first group of output channels are two output terminals of the parallel circuit, the output current is 2 times of the set current of the first group of output channels, and the output voltage is the set voltage of the first group of output channels; parallel output circuits in the first group of output channels and the second group of output channels are connected in parallel to form a single parallel output. The second group of output channels of the main interface displays 'PARALLEL with CH 1', namely the first group of output channels are output by a main channel, and the second group of output channels are output by a slave channel;
when the operation mode is a tracking operation mode, the first group of output channels and the second group of output channels are correlated, correlation symbols and a 'Track' mark are displayed between the first group of output channels and the second group of output channels of the main interface, voltages are tracked mutually, the set voltage of any channel is changed, and the set voltage of the other channel is changed; the current of the two channels is not affected.
Remote control output, which is realized by inhibiting signal input, wherein an external signal is input from a third group of output channels, the delay time of the input signal is less than 450us, the maximum time for opening and closing the output channels is 45ms, and the external input signal controls the output states of all the output channels in the power supply through the input logic state; allowing the external signal input state to have logic true to false conversion, wherein the output state is determined by the external input signal, and when the external input signal is true, the digital signal is remotely inhibited from being output from the third group of output channels; when the external input signal is false, the output is normal.
A digital IO fault output, wherein the first group of output channels, the second group of output channels and the third group of output channels can be set as universal bidirectional digital input and output;
when the first group of output channels and the second group of output channels are used as outputs, the third group of output channels are used as In input pins, display 1 indicates a fault signal, and display 0 indicates no fault signal; wherein
The polarity of the IO port is set to be positive, and output is displayed as low level under normal working condition. When a fault occurs, the In input pin is changed from 0 to 1, a high level is output, and the In input pin is recovered to a low level after the fault is cleared;
the polarity of the IO port is set as a negative electrode, and when the IO port works normally, the output is displayed as a high level. When a fault occurs, the In input pin is changed from 0 to 1, a low level is output, and the high level is recovered after the fault is cleared.
The inside control circuit that is equipped with of shell is used for supporting the function that the front panel operation realized, and control circuit includes: the power consumption adjustable low-power output circuit, the anti-interference reset circuit, the high-power amplifying circuit, the series-parallel circuit and the digital IO circuit;
preferably, the power consumption adjustable low-power output circuit includes:
the power device Q2 comprises a voltage stabilizing diode and an inverter, wherein a D end and an S end which generate voltage difference are arranged at the two ends of the anode and the cathode of the voltage stabilizing diode; the inverter is electrically connected with a voltage difference control circuit for controlling the voltage difference output;
the differential pressure control circuit includes: the voltage division filter circuit is composed of a voltage division resistor R3 and a voltage division resistor R4 which are connected with a filter capacitor C6 in parallel;
the power control circuit is provided with a low-power amplifying triode Q1, one end of a filter capacitor C6 is electrically connected with a voltage dividing end between a voltage dividing resistor R3 and a voltage dividing resistor R4, the other end of the filter capacitor C6 is electrically connected with an emitting electrode of the low-power amplifying triode Q1, the voltage of the D end of a power device Q2 flows through the voltage dividing resistors R4 and R3, and a large-voltage signal obtained by voltage division and filtering of the filter capacitor C6 is transmitted to the low-power amplifying triode for power amplification.
The control circuit is provided with current-limiting protection resistors R2 and R19 which are loaded at the power supply end of the low-power amplifying triode +/-15V;
a transformer P1 having 4 winding ends, wherein the first winding end and the fourth winding end form a group of large voltage winding ends, and the second winding end and the third winding end form another group of small voltage winding ends;
the first winding end and the second winding end are connected with a first relay K1 in the same direction, the third winding end and the fourth winding end are connected with a second relay K2 in the same direction, and the first relay K1 and the second relay K2 are respectively connected with a diode D1 and a diode D2 in parallel to load power supply ends;
the output end of the first relay K1 is electrically connected with the second pin end of the rectifier bridge through a fuse, the rectifier bridge converts an alternating current signal input by a transformer into a direct current signal, the output end of the second relay K2 is directly connected with the third pin end of the rectifier bridge, and the first pin end and the fourth pin end of the rectifier bridge are respectively and electrically connected with the first output port and the second output port of the power output end P2.
Preferably, the tamper resistant reset circuit includes:
the reset control key or the reset control pin transmits a reset signal to a first-stage RC filter circuit formed by connecting a resistor R7 in parallel with a capacitor C1 for primary filtering;
the anti-interference reset circuit further comprises a first Schmitt reverse trigger and a second Schmitt reverse trigger which are in equidirectional cascade connection, and the first Schmitt reverse trigger and the second Schmitt reverse trigger carry out interference processing on the reset signal for 2 times;
the discharge protection branch circuit consists of a protector series connection resistor R9, and two ends of the discharge protection branch circuit are connected with two ends of a resistor R8 in parallel; the resistor R8 and the capacitor C2 form a second-stage RC filter circuit; the second-stage RC filter circuit is electrically connected with a reset phase inverter through a third Schmidt reverse-phase trigger, and the output end of the reset phase inverter is electrically connected with a reset pin of the MCU.
The high-power amplifying circuit is provided with a transformer, two output ends of the transformer are respectively connected with diodes D4 and D5 in parallel in the same direction, and the transformer is grounded through a middle coil;
the diodes D4 and D5 form a plate bridge rectifier, and the output end of the rectifier is provided with a parallel filter circuit formed by connecting an electrolytic capacitor with a large capacitance value in parallel with a resistor;
the parallel filter circuit outputs signals through an amplifying MOS tube, the amplifying MOS tube is connected with a control end through a resistor, the control end controls the voltage difference at two ends of the amplifying MOS tube, the control end is also electrically connected with a quick discharge circuit, the quick discharge circuit is formed by connecting a switch MOS tube with a resistor in series, and the other end of the quick discharge circuit is electrically connected with the output end of the amplifying MOS tube to assist in discharging;
when the voltage at the end 1 of the transformer is high and the voltage at the end 2 is low, the current is only output through the diode D4, the output end is connected to the ground to form a circulation loop, and the current only flows through the diode D4 in the working process of one period of the whole circuit; when the voltage at the end 2 of the transformer is high and the voltage at the end 1 is low, the current is only output through the diode D2, the output end is connected to the ground, a circulation loop is formed, and the current only flows through one diode D5 in the working process of one period of the whole circuit.
Preferably, the series-parallel circuit includes:
a first set of output channels comprising a channel 1+ port and a channel 1-port;
a second set of output channels comprising a channel 2+ port and a channel 2-port;
a third set of output channels comprising a channel 3+ port and a channel 3-port;
a fourth set of output channels comprising a channel 4+ port and a channel 4-port;
the MCU is provided with a P control pin which is electrically connected with the third relay K6 through the first drive circuit;
the first driving circuit is provided with a driving triode, the driving triode is provided with a base electrode, the base electrode is electrically connected with the P control pin through a current limiting resistor R62 connected in series, the driving triode is further provided with a collector electrode, the output end of the collector electrode is divided into a first output branch and a second output branch, the first output branch is electrically connected with the third relay K6, and the second output branch is electrically connected with the first relay K4;
the MCU is also provided with an S control pin which is electrically connected with a second relay K5 through a second drive circuit;
the first relay K4, the second relay K5 and the third relay K6 are all provided with a first switching gear, a second switching gear and a third switching gear;
the first switch gear of the first relay K4 is electrically connected with the port of the channel 1+ and the second switch gear of the first relay K4 is open, and the third switch gear of the first relay K4 is electrically connected with the port of the channel 2 +;
the first switch gear of the second relay K5 is electrically connected with the port of the channel 2+, the second switch gear of the second relay K5 is open, and the third switch gear of the second relay K5 is electrically connected with the port of the channel 1;
the first switch of the third relay K6 is electrically connected with the 1-port of the channel, the second switch of the third relay K6 is disconnected, and the third switch of the third relay K6 is electrically connected with the 2-port of the channel;
second switch gears of the first relay K4, the second relay K5 and the third relay K6 are all selective switch gears, and the second switch gears can be selectively and electrically connected with a third switch gear;
the MCU controls a third relay K4 and a third relay K6 through a P control pin;
the MCU controls the third relay K5 through the S control pin;
when the second switching gears of the first relay K4, the second relay K5 and the third relay K6 are all selected to be disconnected, the first group of output channels and the first group of output channels are rated in output voltage and current;
when the second switch gear of the first relay K4 is selected to be electrically connected with a third switch gear, the second switch gear of the second relay K5 is selected to be disconnected, the second switch gear of the third relay K6 is selected to be electrically connected with the third switch gear, and a channel 1+ port and a channel 2+ port form a parallel output circuit with a channel 1-port and a channel 2-port;
when the second switch gear of the first relay K4 is selected to be disconnected, the second switch gear of the second relay K5 is selected to be electrically connected with a third switch gear, and the second switch gear of the third relay K6 is selected to be disconnected, a channel 2+ port is connected with a channel 1-port in series, and the channel 1+ port and the channel 2-port form a series output circuit;
the current output by the series output circuit is unchanged, and the output voltage is equal to the sum of two rated output voltages;
the voltage output by the parallel output circuit is unchanged, and the output current is equal to the sum of rated output currents.
Preferably, the digital IO circuit is provided with a DIO _ IN input port, the input port is electrically connected with a GPIO input pin of the single chip microcomputer, the other end of the DIO _ IN input port is electrically connected with a phase inverter, the phase inverter is connected with the power supply circuit through a voltage division circuit formed by serially connecting a voltage division resistor R15 and a voltage division resistor R16, the power supply circuit is provided with a protection diode, the tube voltage drop of the protection diode is 0.2V, and the power supply of the power supply circuit is 5V;
the protection diode is electrically connected with a power supply and is used for preventing high voltage from being led into the power supply;
a filter circuit is arranged in the phase inverter, so that the phase inverter has an inhibiting effect on noise signals and effectively prevents false triggering caused by interference signals;
the digital IO circuit is further provided with a DIO _ OUT output port which is electrically connected with a GPIO output pin of the single chip microcomputer, the other end of the DIO _ OUT output port is electrically connected with a MOS transistor Q8 through a protective resistor R17, the MOS transistor Q8 is provided with a drain electrode, the MOS transistor Q8 is electrically connected with a Schottky diode D7 through the drain electrode, and the other end of the Schottky diode D7 is electrically connected with a DIO digital IO interface through an inductor L4;
the DIO digital IO interface is used for externally connecting equipment and can be used as an output interface or an input interface;
the voltage drop of the Schottky diode D2 is low, so that a small voltage can be ensured when a DIO digital IO interface outputs a low level;
a capacitor C5 and a TVS tube are electrically connected between the Schottky diode D7 and the inductor L4, the capacitor C5 and the inductor L4 form an LC filter circuit, and the TVS tube is used for absorbing large voltage and performing electrostatic protection.
Has the advantages that:
(1) the 3.5-inch TFT display screen is adopted, a plurality of parameters and states can be displayed simultaneously, a clear user interface is provided, the tracking display function is realized, the voltage/current waveform is dynamically displayed in real time, and the voltage, current and power values displayed in a digital mode are matched, so that the output state and trend of the instrument are clear for a user, and various communication interfaces can meet the diversified test requirements of the user;
(2) providing multi-path voltage output, wherein the total output power is up to 200W, and the output of each channel is independently controllable; the voltage-stabilizing and current-stabilizing values of the 1 and 2 paths are adjustable in a stepping mode, two working states of voltage stabilization and current stabilization can be automatically switched along with the change of a load, the outputs of the 1 and 2 paths can be connected in series, in parallel and independently work, and the 3 rd path provides four selectable output voltages of 1.8V, 2.5V, 3.3V and 5V;
(3) the output ripple and the noise are ultra-low;
(4) the device has a Sense function, and automatically compensates the voltage drop caused by a load lead when the large current is output;
(5) the series and parallel output functions are supported;
(6) the digital IO interface is provided with a DIO digital IO interface, and can be used as an input interface and an output interface.
Drawings
FIG. 1 is a schematic diagram of the structure of the front panel and the housing of the present invention;
fig. 2 is a schematic diagram of the structure of the housing and the interface panel of the present invention;
FIG. 3 is a block diagram of the Sense terminal detection of the present invention;
FIG. 4 is a diagram of the structure of the Sense terminal connection DIO digital IO interface of the present invention;
fig. 5 is a wiring diagram of the output terminal in the series operation mode of the present invention;
fig. 6 is a wiring diagram of the output terminal in the parallel operation mode of the present invention;
fig. 7 is a circuit diagram of the power consumption adjustable low power output circuit of the present invention;
FIG. 8(a) is a circuit diagram of a reset circuit on the market today;
fig. 8(b) is a circuit diagram of the anti-interference reset circuit of the present invention;
fig. 9 is a circuit diagram of the high power amplifier circuit of the present invention;
fig. 10 is an internal connection diagram of the output channel of the series output circuit of the present invention;
FIG. 11 is an internal connection diagram of the output channel of the parallel output circuit of the present invention;
fig. 12 is a circuit diagram of a series-parallel circuit according to the present invention;
fig. 13 is a circuit diagram of the digital IO circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the utility model provides a field ordinary skilled person does not make all other embodiments that obtain under the creative work prerequisite, all belong to the utility model discloses the scope of protection.
In one aspect, the present invention provides an alternative embodiment illustrating the structure and function of the present invention.
Referring to fig. 1, a programmable dc power supply comprises a housing 1, a front panel is provided on the front side of the housing 1, the front panel has a display screen 2 for displaying a user interface, an auxiliary function soft key 3 for menu display is provided on the lower side of the display screen 2, a USB Host interface 4 for allowing an external USB driver to be connected to the device is provided on the left side of the display screen 2, a function key 5, a direction key 6 and a numeric keypad 7 are provided on the right side of the display screen 2, wherein the function key 5 comprises: a Meter View key for displaying a selected channel Meter View, a Tracking key for turning on or off Tracking modes of the second group of output channels 12 and the third group of output channels 13, a Store/call key for turning on a save or call menu, and an Enter key for determining a selection; the direction key 6 includes: an up key, a down key, a left key, and a right key for moving a cursor position; the numeric keypad 7 includes: a "0-9" number key, a "-" decimal key, and an "x" delete key for directly inputting a numerical value; the front panel still is equipped with a set of adjust knob, and this adjust knob includes: a voltage adjusting knob 8 for adjusting the unit precision of voltage to be 1MV and a current adjusting knob 9 for adjusting the unit precision of current to be 1 MA; a power switch 10 is independently arranged at the lower left corner of the front panel; the front panel is also provided with four groups of output channels, and the four groups of output channels are respectively: a first set of output channels 11, a second set of output channels 12, a third set of output channels 13 and a fourth set of output channels 14; wherein, every group output channel of these four groups output channel all includes: a positive output terminal, a negative output terminal, a selection key 15 and a channel output control key 16; ALL ON/OFF keys 17 and a common ground terminal 18 which are ALL opened or ALL closed are arranged between the second group of output channels 12 and the third group of output channels 13 from top to bottom;
referring to fig. 2, the rear side of the housing 1 is provided with an interface panel including: LAN interface 19 of the cut-in LAN, USB Device interface 20 of the connecting computer, RS-232 interface 21 of the serial communication, DIO digital IO interface 22 that can be regarded as the input and can be regarded as the output as well, alternating voltage selector switch 23, GPIB interface 24, power interface 25 and exhaust fan 26 that the general bus connects; the LAN interface 19 is accessed to a local area network through an RJ-45 interface and is remotely controlled through a computer; the USB Device interface 20 is connected with a computer through a USB interface, and sends an SCPI command or self-defined programming control through upper computer software; the DIO digital IO interface 22 is used for external equipment, and can be used as an output interface or an input interface; the voltage steps selectable by the alternating voltage selection switch 23 are 100V, 120V, 220V and 240V; by correspondingly opening a first group of output channels 11, a second group of output channels 12, a third group of output channels 13 and a fourth group of output channels 14 through a channel output control key 16 of each group, when a certain output channel is opened, the background of the corresponding channel in the display screen 2 is highlighted, then the channel is selected through a selection key 15, the specific parameters of the channel appear in the display screen 2, the function operation is carried out through a function key 5 of a front panel, the cursor position can be moved up, down, left and right through a direction key 6, the cursor can be positioned to 'voltage'/'current', the digital keyboard 7 is used, the setting is carried out by matching with a voltage adjusting knob 8 and a current adjusting knob 9, the specific parameters of the channel are directly input through the digital keyboard 7, and the like; when a plurality of channel outputs need to be used simultaneously, ALL output channels can be opened completely by using the ALL ON key;
the output modes of the first group of output channels 11, the second group of output channels 12, the third group of output channels 13 and the fourth group of output channels 14 all include: constant current output and constant voltage output; when the constant current is output, the output current is equal to a set current value, the output voltage value is equal to the current set value multiplied by the load resistance value, and when the load voltage exceeds the set voltage value, the constant voltage output is realized; and outputting constant voltage, wherein the output voltage is equal to a set voltage value, the output current value is equal to a voltage set value divided by a load resistance value, and when the load current exceeds the set current value, the constant current output is realized.
The voltage steps selectable by the alternating voltage selection switch 23 are 100V, 120V, 220V and 240V; when the voltage-selecting switch is used, a proper alternating voltage is required to be selected to input a gear, the input voltage is required to be within a range allowed by the gear, and the corresponding relation between the voltage-selecting switch gear and the voltage allowed to be input is shown in the following table:
| alternating |
Input of alternating voltage |
| 100V | 100V±10％，50Hz |
| 120V | 120V±10％，50Hz |
| 220V | 220V±10％，60Hz |
| 240V | 240V±10％，60Hz |
Referring to fig. 3 and 4, the DIO digital IO interface 22 is electrically connected to a Sense terminal, the Sense terminal detects an output voltage when the DIO digital IO interface 22 is used as an output interface and feeds the output voltage back to the MCU for verification, when the rear panel DIO digital IO interface 22 is selected for constant voltage output, the Sense terminal can automatically compensate for a voltage drop caused by a load lead, the output configuration is divided into two-wire sensing and four-wire sensing, and a value measured by the four-wire sensing is more accurate than that measured by the two-wire sensing, so that a set power output value is ensured to be consistent with a voltage obtained by a load.
In a second aspect, the present invention provides another alternative embodiment, illustrating a method for controlling channel output, comprising:
outputting over-protection delay, wherein each channel has over-protection and delay functions, the delay time is set to be 0-3600s, and the step is 1 ms; the power supply ignores the CC (constant current) output state during the delay period of the OCP (over current protection), and if the delay time is over, the output state is still CC, the output is forbidden; if the output voltage reaches a voltage protection value, the output state of the channel is changed from CV (constant voltage) to OV (overvoltage), and the channel is set to be forbidden to output; and if the output current reaches the current protection value, the output state of the channel is changed from CV to CC, and the channel is set to be forbidden to output.
And coupling the output, wherein the delayed output of a single channel or a plurality of channels can be selected to be coupled with the output of a plurality of channels. The auxiliary function soft key is provided with an on/off coupling key, channels needing coupling output can be started through the on/off coupling key, any one of the channel outputs is opened after the coupling output is started, and the rest coupling channels are opened at the same time; when only partial channel output coupling is turned ON, the ALL ON/OFF key 17 of the front panel is turned ON, and ALL channels turn ON the output regardless of whether the channels enable the switch coupling; when a single channel is output, no channel coupling is required.
A multi-mode operation output, wherein the auxiliary function soft key has an operation mode key which selects an independent, serial, parallel and tracking operation mode for the first group of output channels 11 and the second group of output channels 12;
when the operation mode is the independent operation mode, the channels are independently output without mutual influence, and the output voltage or current is the set voltage and the set current of each channel;
referring to fig. 5, when the operation mode is the series operation mode, the 1+ port of the first group of output channels 11 and the 2-port terminal of the second group of output channels 12 are two output terminals of the series output circuit, the output voltage is 2 times of the set voltage of the first group of output channels 11, and the output current is the set current of the first group of output channels 11; the output ends of the SERIES output circuits in the first group of output channels 11 and the second group of output channels 12 are connected in SERIES to form a single SERIES channel output, at this time, the window of the second group of output channels 12 of the main interface displays "services with CH 1", that is, the first group of output channels 11 are the main channel output, and the second group of output channels 12 are the slave channel output;
referring to fig. 6, when the operation mode is the parallel operation mode, the 1+ port and 1-port terminals of the first group of output channels 11 are two output terminals of the parallel circuit, the output current is 2 times of the set current of the first group of output channels 11, and the output voltage is the set voltage of the first group of output channels 11; parallel output circuits inside the first group of output channels 11 and the second group of output channels 12 are connected in parallel to form a single parallel output. The second group of output channels 12 of the main interface displays "PARALLEL with CH 1" in a window, that is, the first group of output channels 11 is output by a main channel, and the second group of output channels 12 is output by a slave channel;
when the operation mode is a tracking operation mode, the first group of output channels 11 and the second group of output channels 12 are correlated, correlation symbols and a 'Track' mark are displayed between the first group of output channels 11 and the second group of output channels 12 on the main interface, voltages are tracked with each other, the set voltage of any channel is changed, and the set voltage of the other channel is changed; the current of the two channels is not affected.
Remote control output, which is realized by inhibiting signal input, wherein an external signal is input from a third group of output channels 13, the delay time of the input signal is less than 450us, the maximum time for opening and closing the output channels is 45ms, and the external input signal controls the output states of all the output channels in the power supply through the input logic state; allowing the external signal input state to have logic true to false conversion, wherein the output state is determined by the external input signal, and when the external input signal is true, the digital signal is remotely inhibited from being output from the third group of output channels 13; when the external input signal is false, the output is normal.
Digital IO fault outputs, the first group of output channels 11, the second group of output channels 12, and the third group of output channels 13 may all be set to general bidirectional digital inputs and outputs, with their internal pins being pin1, pin2, and pin3 pins, respectively. The data bit allocation for each pin is as follows:
the fault output function enables a fault condition on any channel to generate a fault protection signal on the digital IO port. The fault conditions include over-voltage, over-current, over-temperature and inhibit signals, where the first 11, second 12 groups of output channels are used for fault output, and the third 13 group of output channels is used as In input: the status (binary bit 0 or 1) applied to the pin is displayed.
When the first group of output channels 11 and the second group of output channels 12 are used as outputs, the third group of output channels 13 is used as In input pins, and display 1 indicates a fault signal, and display 0 indicates no fault signal.
(1) The polarity of the IO port is set to be positive, and output is displayed as low level under normal working condition. When a fault occurs, the In input pin is changed from 0 to 1, a high level is output, and the In input pin is recovered to a low level after the fault is cleared;
(2) the polarity of the IO port is set as a negative electrode, and when the IO port works normally, the output is displayed as a high level. When a fault occurs, the In input pin is changed from 0 to 1, a low level is output, and the high level is recovered after the fault is cleared.
In a third aspect, the present invention provides another alternative embodiment, which supports the implementation of the technical solutions disclosed in the first and second aspects through the related control circuit;
a control circuit, comprising: the power consumption adjustable low-power output circuit, the anti-interference reset circuit, the high-power amplifying circuit, the series-parallel circuit and the digital IO circuit;
referring to fig. 7, the power consumption adjustable low-power output circuit is provided with a power device Q2, which is composed of a zener diode and an inverter, wherein a D terminal and an S terminal for generating a voltage difference are arranged at two ends of a positive pole and a negative pole of the zener diode; the inverter is electrically connected with a voltage difference control circuit for controlling the voltage difference output; the differential pressure control circuit includes: the voltage division filter circuit is composed of a voltage division resistor R3 and a voltage division resistor R4 which are connected with a filter capacitor C6 in parallel; the power control circuit is provided with a low-power amplifying triode Q1, one end of a filter capacitor C6 is electrically connected with a voltage dividing end between a voltage dividing resistor R3 and a voltage dividing resistor R4, the other end of the filter capacitor C6 is electrically connected with an emitter of the low-power amplifying triode Q1, the voltage D of a power device Q2 flows through the voltage dividing resistors R4 and R3, a large-voltage signal obtained by the filter capacitor C6 is subjected to voltage dividing and filtering and then is transmitted to the low-power amplifying triode for power amplification, and the power control circuit is provided with a current-limiting protection resistor R2 and a current-limiting protection resistor R19 which are loaded at the power;
the power consumption adjustable low-power output circuit is also provided with a transformer P1 with 4 winding ends, wherein the first winding end and the fourth winding end form a group of large voltage winding ends, and the second winding end and the third winding end form another group of small voltage winding ends; the first winding end and the second winding end are connected with a first relay K1 in the same direction, the third winding end and the fourth winding end are connected with a second relay K2 in the same direction, and the first relay K1 and the second relay K2 are respectively connected with a diode D1 and a diode D2 in parallel to load power supply ends; the output end of the first relay K1 is electrically connected with a second pin end of a rectifier bridge through a fuse, the rectifier bridge converts an alternating current signal input by a transformer into a direct current signal, the output end of the second relay K2 is directly connected with a third pin end of the rectifier bridge, and the first pin end and the fourth pin end of the rectifier bridge are respectively and electrically connected with a first output port and a second output port of a power output end P2; the voltage generated at the end D is marked as V1, the voltage generated at the end S is marked as V2, Q2 works in an amplification area, when the voltage output by a power output end P2 is low voltage, namely the voltage V2 is smaller, the voltage difference between the end D and the end S of Q2 is V1-V2, the power consumption of Q2 is P ═ V1-V2I, and if the power consumption of the part is overlarge, the part is converted into useless power and is emitted in the form of heat;
now, the power consumption is adjusted by controlling the values of V1 and V2 to achieve the lowest power consumption, and the feasibility of the technical solution of the present invention is illustrated by the method of reducing the power consumption of Q2 in this embodiment;
the voltage value of the V1 is controlled to adjust the voltage difference, so that the power consumption of the Q2 is reduced;
specifically, the method comprises the following steps: when the output voltage V2 is relatively large, the forward voltage of the transformer goes to the first winding end through the first relay K1, and the circuit flows as follows: the first winding end flows into the second pin end of the rectifier bridge after flowing through the fuse, flows out of the first pin end of the rectifier bridge, flows back through the fourth pin end of the rectifier bridge after passing through the loop, and flows back to the fourth winding end of the second relay K2 through the third pin end to form a complete loop, so that when the output voltage V2 is larger, the voltage difference of V1 is improved to be the minimum as possible (the voltage difference of V1-V2 is close to zero in the most ideal state of the voltage differences of V1-V2), and the voltage difference is small, so that the power consumption is also reduced;
specifically, the method comprises the following steps: when the output voltage V2 is relatively small, the forward voltage of the transformer goes to the second winding end through the first relay K1, and the circuit flows as follows: the second winding end flows into the second pin end of the rectifier bridge after flowing through the fuse, flows out of the first pin end of the rectifier bridge, flows back through the fourth pin end of the rectifier bridge after passing through the loop, and flows back to the third winding end of the second relay K2 through the third pin end to form a complete loop, so that when the output voltage V2 is smaller, the V1 is reduced, the voltage difference between V1 and V2 is minimized, the voltage difference between V1 and V2 is close to zero in the most ideal state, and the voltage difference is reduced, so that the power consumption is also reduced.
Referring to fig. 8(a) and 8(b), the tamper resistant reset circuit includes: the reset control key or the reset control pin transmits a reset signal to a first-stage RC filter circuit formed by connecting a resistor R7 in parallel with a capacitor C1 for primary filtering; the anti-interference reset circuit further comprises a first Schmitt reverse trigger and a second Schmitt reverse trigger which are in equidirectional cascade connection, and the first Schmitt reverse trigger and the second Schmitt reverse trigger carry out interference processing on the reset signal for 2 times; the discharge protection branch circuit consists of a protector series connection resistor R9, and two ends of the discharge protection branch circuit are connected with two ends of a resistor R8 in parallel; the resistor R8 and the capacitor C2 form a second-stage RC filter circuit; the second-stage RC filter circuit is electrically connected with a reset phase inverter through a third Schmidt reverse-phase trigger, and the output end of the reset phase inverter is electrically connected with a reset pin of the MCU;
after the reset signal is filtered by the first stage of RC filter circuit, because the reset signal is not processed, interference signals such as a burr signal and the like are doped, if the voltage of the reset signal is too large, the fluctuation amplitude of the interference signals is increased easily, and false triggering is easily caused, the interference signals are processed by the first Schmitt reverse-phase trigger and the second Schmitt reverse-phase trigger, the fluctuation amplitude of the interference signals is reduced, in order to prevent the processed reset signal from still suffering from the interference signals with small amplitude, the filtering is carried out by the second stage of RC filter circuit, the interference signals are processed again by the third Schmitt reverse-phase trigger, the anti-interference performance of the reset signal transmitted to the MCU by the reset inverter is obviously enhanced, meanwhile, in the process of processing the interference signals, the resistor R9 in the discharge protection branch is far smaller than the resistor R8, certain protection is provided for electrostatic interference; the circuit effectively carries out anti-interference processing for a plurality of times on burr signals, electrostatic interference signals and the like doped in the reset signals, so that the reset signals in the circuit are normally triggered, the interference signals exist in time, but the change of the amplitude of the interference signals does not form a triggering condition, and the phenomenon of false triggering is effectively solved.
Referring to fig. 9, the high power amplifying circuit has a transformer having two output terminals connected in parallel with diodes D4 and D5 in the same direction, respectively, and the transformer is grounded through a middle coil; the diodes D4 and D5 form a plate bridge rectifier, the rectifier output end is provided with a parallel filter circuit formed by connecting electrolytic capacitors with large capacitance values in parallel with resistors, the parallel filter circuit outputs signals through an amplifying MOS (metal oxide semiconductor) tube, the amplifying MOS tube is connected with a control end through a resistor, the control end controls the voltage difference at two ends of the amplifying MOS tube, the control end is also electrically connected with a quick discharge circuit, the quick discharge circuit is formed by connecting a switch MOS tube with a resistor in series, and the other end of the quick discharge circuit is in auxiliary discharge through the output end electrically connected with the amplifying MOS tube;
when the voltage at the end 1 of the transformer is high and the voltage at the end 2 is low, the current is only output through the diode D4, the output end is connected to the ground to form a circulation loop, and the current only flows through the diode D4 in the working process of one period of the whole circuit; when the voltage at the end 2 of the transformer is high and the voltage at the end 1 is low, the current is only output through the diode D2, the output end is connected to the ground to form a circulation loop, the current only flows through the diode D5 in the working process of the whole circuit in one period, the voltage drop of each diode is Ud, the current passing through the diode is Id, the power consumption of the rectifying circuit is Ud Id, the power consumption in the working process of the circuit is effectively reduced, and compared with a common circuit, the loss on components is reduced to half of the original loss; no matter the voltage of transformer 1 end is high or the voltage of transformer 2 end is high, the high voltage passes through the voltage difference at control end control amplification MOS pipe both ends, realize the voltage of control output, when the voltage of output was still too big, need carry out voltage conversion through fast discharge circuit to the voltage of output fast discharge, open switch MOS pipe through the control end, discharge the voltage of output to ground through fast discharge circuit and resistance R14 two ways simultaneously, the conversion of voltage has been accelerated, and the power consumption that generates heat of rectifier circuit has been saved.
Referring to fig. 12, the series-parallel circuit includes:
a first set of output channels 11 comprising a channel 1+ port and a channel 1-port;
a second set of output channels 12 comprising a channel 2+ port and a channel 2-port;
a third set of output channels 13 comprising a channel 3+ port and a channel 3-port;
a fourth set of output channels 14 comprising a channel 4+ port and a channel 4-port;
the MCU is provided with a P control pin which is electrically connected with the third relay K6 through the first drive circuit;
the first driving circuit is provided with a driving triode, the driving triode is provided with a base electrode, the base electrode is electrically connected with the P control pin through a current limiting resistor R62 connected in series, the driving triode is further provided with a collector electrode, the output end of the collector electrode is divided into a first output branch and a second output branch, the first output branch is electrically connected with the third relay K6, and the second output branch is electrically connected with the first relay K4; the MCU is also provided with an S control pin which is electrically connected with a second relay K5 through a second drive circuit; the first relay K4, the second relay K5 and the third relay K6 are all provided with a first switching gear, a second switching gear and a third switching gear; the first switch gear of the first relay K4 is electrically connected with the port of the channel 1+ and the second switch gear of the first relay K4 is open, and the third switch gear of the first relay K4 is electrically connected with the port of the channel 2 +; the first switch gear of the second relay K5 is electrically connected with the port of the channel 2+, the second switch gear of the second relay K5 is open, and the third switch gear of the second relay K5 is electrically connected with the port of the channel 1; the first switch of the third relay K6 is electrically connected with the 1-port of the channel, the second switch of the third relay K6 is disconnected, and the third switch of the third relay K6 is electrically connected with the 2-port of the channel; second switch gears of the first relay K4, the second relay K5 and the third relay K6 are all selective switch gears, and the second switch gears can be selectively and electrically connected with a third switch gear; the MCU controls a third relay K4 and a third relay K6 through a P control pin; the MCU controls the third relay K5 through the S control pin; when the second switching gears of the first relay K4, the second relay K5 and the third relay K6 are all selected to be disconnected, the first group of output channels 11 and the first group of output channels 11 are rated to output voltage and current;
referring to fig. 11, when the second switching position of the first relay K4 selects to electrically connect the third switching position, the second switching position of the second relay K5 selects to open the circuit, and the second switching position of the third relay K6 selects to electrically connect the third switching position, the channel 1+ port and the channel 2+ port form a parallel output circuit with the channel 1-port and the channel 2-port;
referring to fig. 10, when the second switching position of the first relay K4 is selectively disconnected, the second switching position of the second relay K5 is selectively electrically connected to the third switching position, and the second switching position of the third relay K6 is selectively disconnected, a channel 2+ port is connected in series with a channel 1-port, and the channel 1+ port and the channel 2-port form a series output circuit.
The current output by the series output circuit is unchanged, and the output voltage is equal to the sum of two rated output voltages; the voltage output by the parallel output circuit is unchanged, and the output current is equal to the sum of rated output currents;
for example, the maximum rated output voltage and current of the first group of output channels 11 and the first group of output channels 11 are both 32V/3A, if the actually required current is 5A, the current outputs of the first group of output channels 11 and the first group of output channels 11 do not meet the requirement condition, at this time, a parallel output circuit is selected, and since the maximum output voltage and current thereof is 32V/6A, the sum of the currents of the first group of output channels 11 and the output currents of the output channels 11 and the output currents of 32V/3A and 32V/2A or 32V/2A and 32V/3A can be adjusted in real time to be 5A for collocation use; if the actually required voltage is 60V, the voltage outputs of the first group of output channels 11 and the first group of output channels 11 do not meet the required condition, at this time, the series output circuit is selected, and because the maximum output voltage and current of the series output circuit are 64V/3A, the sum of the voltages of the first group of output channels 11 and the output voltages of the series output circuit are adjusted to be 25V/3A and 25V/3A or 20V/3A and 30V/2A in real time to be 50V for matching; the current can be selectively adjusted and increased through the parallel output circuit, and the maximum output current is the sum of the current output values of the first group of output channels 11 and the first group of output channels 11; the voltage can be selectively adjusted and increased by the series output circuit, and the maximum output voltage is the sum of the voltage output values of the first group of output channels 11 and the first group of output channels 11; the MCU controls the P control pin and the S control pin to respectively increase the driving capability of the circuit at signals through the first driving circuit and the second driving circuit, and the second switch gear of each relay can fluctuate rapidly after the signals are amplified.
Referring to fig. 13, the digital IO circuit has a DIO _ IN input port electrically connected to a GPIO input pin of the single chip microcomputer, the other end of the DIO _ IN input port is electrically connected to a phase inverter, the phase inverter is connected to a power supply circuit through a voltage dividing circuit formed by serially connecting voltage dividing resistors R16 with voltage dividing resistors R15, the power supply circuit is provided with a protection diode, a tube voltage drop of the protection diode is 0.2V, and a power supply source of the power supply circuit is 5V; the protection diode is electrically connected with a power supply and is used for preventing high voltage from being led into the power supply; a filter circuit is arranged in the phase inverter, so that the phase inverter has an inhibiting effect on noise signals and effectively prevents false triggering caused by interference signals;
the digital IO circuit is further provided with a DIO _ OUT output port which is electrically connected with a GPIO output pin of the single chip microcomputer, the other end of the DIO _ OUT output port is electrically connected with a MOS transistor Q8 through a protective resistor R17, the MOS transistor Q8 is provided with a drain electrode, the MOS transistor Q8 is electrically connected with a Schottky diode D7 through the drain electrode, and the other end of the Schottky diode D7 is electrically connected with the DIO digital IO interface 22 through an inductor L4; the DIO digital IO interface 22 is used for external equipment, and can be used as an output interface or an input interface; the voltage drop of the schottky diode D2 is low, which can ensure that the DIO digital IO interface 22 has a relatively small voltage when outputting a low level; a capacitor C5 and a TVS tube are electrically connected between the Schottky diode D7 and the inductor L4, the capacitor C5 and the inductor L4 form an LC filter circuit, and the TVS tube is used for absorbing large voltage to perform electrostatic protection;
the digital IO circuit realizes the function that a single port can input and output, and is compatible with the noise-to-split function, after a DIO _ IN input port and a DIO _ OUT output port are connected to a GPIO input pin and a GPIO output pin of a single chip microcomputer, the DIO _ IN input port is configured into an input function through the single chip microcomputer, and the DIO _ OUT output port is configured into an output function;
when DIO digital IO interface 22 needs to be used as an input, DIO _ OUT output port outputs low level, MOS transistor Q8 is turned off, and current flows through DIO digital IO interface 22 to the following: flowing through inductor L4 → divider resistor R15 → inverter U4 → DIO _ IN input port, when the DIO digital IO interface 22 inputs low level, it is inverted through inverter U4, at this time, the DIO _ IN input port is high level, when the DIO digital IO interface 22 inputs high level, it is inverted through inverter U4, at this time, the DIO _ IN input port is low level; when the current flows into the DIO digital IO interface 22, the current forms an LC filter circuit through the capacitor C5 and the inductor L4 to perform filtering, and the TVS tube absorbs the input large voltage to perform electrostatic protection;
when the DIO digital IO interface 22 needs to be used as an output pin, the DIO _ OUT output port outputs a high level, the MOS transistor Q8 is turned on, the schottky diode D7 is turned on, and at this time, the DIO digital IO interface 22 outputs a low level; when the DIO _ OUT output port outputs a low level, the MOS transistor Q8 is turned off, and the schottky diode D7 is turned off, at this time, the DIO digital IO interface 22 outputs a high level; the singlechip controls the current flow direction as follows: DIO _ OUT output port → protective resistor R17 → MOS transistor Q8 → schottky diode D7 → inductor L4 → DIO digital IO interface 22, the voltage value required by DIO digital IO interface 22 can be output by using protective diodes with different voltage values, since the tube voltage drop of the protective diode of the present circuit is 0.2V and the power supply of the power supply circuit is 5V, the voltage output by DIO digital IO interface 22 is 5V-0.2V ═ 4.8V; if the tube voltage drop of the protection diode is 0.4V and the power supply of the power supply circuit is still 5V, the voltage output by the DIO digital IO interface 22 is 5V-0.4V — 4.6V.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.
Claims (10)
1. A programmable dc power supply comprising a housing (1), said housing (1) being provided at its front side with a front panel having a display screen (2) for displaying a user interface, characterized in that: an auxiliary function soft key (3) for displaying a menu is arranged on the lower side of the display screen (2), and a USB Host interface (4) allowing an external USB driver to be connected to the equipment is arranged on the left side of the display screen (2);
a function key (5), a direction key (6) and a numeric keyboard (7) are arranged on the right side of the display screen (2);
the function keys (5) comprise a Meter View key for displaying a selected channel instrument View, a Tracking key for opening or closing a second group of output channels and a third group of output channel Tracking mode, a Store/Recall key for opening a save or call menu, and an Enter key for determining selection;
the direction key (6) includes: an up key, a down key, a left key, and a right key for moving a cursor position;
the numeric keypad (7) includes: a number key, a decimal key and a delete key for directly inputting numerical values;
the front panel still is equipped with a set of adjust knob, and this adjust knob includes: a voltage regulating knob (8) for regulating voltage with unit precision of 1MV and a current regulating knob (9) for regulating current with unit precision of 1 MA;
a power switch (10) is independently arranged at the lower left corner of the front panel;
the front panel is also provided with four groups of output channels, and the four groups of output channels are respectively: a first group of output channels (11), a second group of output channels (12), a third group of output channels (13) and a fourth group of output channels (14);
each of the four sets of output channels includes: a positive output terminal, a negative output terminal, a selection key (15) and a channel output control key (16);
the second group of output channels (12) and the third group of output channels (13) are arranged from top to bottom: ALL ON/OFF keys (17) and a common ground terminal (18) that ALL turn ON or ALL turn OFF ALL output channels.
2. A programmable dc power supply as in claim 1, wherein: an interface panel is arranged on the rear side of the shell (1);
the interface panel comprises a LAN interface (19) for accessing a local area network, a USB Device interface (20) for connecting a computer, an RS-232 interface (21) for serial communication, a DIO digital IO interface (22) for input/output, an alternating voltage selection switch (23), a GPIB interface (24) for universal bus connection, a power supply interface (25) and an exhaust fan (26).
3. A programmable dc power supply as in claim 2, wherein: the LAN interface (19) is accessed to a local area network through an RJ-45 interface and is remotely controlled through a computer.
4. A programmable dc power supply as in claim 2, wherein: the USB Device interface (20) is connected with a computer through a USB interface, and sends an SCPI command or self-defined programming control through upper computer software.
5. A programmable dc power supply as in claim 2, wherein: the DIO digital IO interface (22) is externally connected with equipment and can be used as an output interface or an input interface.
6. A programmable dc power supply as in claim 2, wherein: the voltage steps selectable by the alternating voltage selection switch (23) are four steps of 100V, 120V, 220V and 240V.
7. A programmable dc power supply as in claim 1, wherein: the output modes of the four groups of output channels comprise: constant current output and constant voltage output.
8. A programmable dc power supply as in claim 7, wherein: when the constant current is output, the output current value is equal to the set current value, the output voltage value is equal to the current set value multiplied by the load resistance value, and when the load voltage value exceeds the set voltage value, the constant current is converted into constant voltage output.
9. A programmable dc power supply as in claim 7, wherein: when the constant voltage is output, the output voltage value is equal to the set voltage value, the output current value is equal to the voltage set value divided by the load resistance value, and when the load current value exceeds the set current value, the constant current is converted into the constant current output.
10. A programmable dc power supply as in claim 2, wherein: the DIO digital IO interface (22) is electrically connected with a Sense terminal;
the Sense terminal detects the output voltage when a DIO digital IO interface (22) is used as an output interface, and feeds back the detected voltage value to the MCU for verification;
when the DIO digital IO interface (22) outputs a constant voltage, the Sense terminal can automatically compensate the voltage drop caused by a load lead.
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| CN112416105A (en) * | 2021-01-21 | 2021-02-26 | 北京中新绿景科技有限公司 | Multi-channel TFX structure power supply |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112416105A (en) * | 2021-01-21 | 2021-02-26 | 北京中新绿景科技有限公司 | Multi-channel TFX structure power supply |
| CN112416105B (en) * | 2021-01-21 | 2021-05-11 | 北京中新绿景科技有限公司 | Multi-channel TFX structure power supply |
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