CN212342600U

CN212342600U - Packaging structure and semiconductor package

Info

Publication number: CN212342600U
Application number: CN202022055101.2U
Authority: CN
Inventors: 张锋; 周继峰; 蔡颖达
Original assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Current assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Priority date: 2020-09-18
Filing date: 2020-09-18
Publication date: 2021-01-12
Anticipated expiration: 2030-09-18

Abstract

A package structure and a semiconductor package are provided. In one example, a package structure may include a first leadframe including a die pad and a chip stack coupled to the first leadframe. The chip stack may include a Transient Voltage Suppression (TVS) device coupled to the die pad, a solder wafer coupled to the TVS device, and a glass passivation tray (GPP) device coupled to the solder wafer.

Description

Packaging structure and semiconductor package

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and more particularly to a package structure for a low capacity Transient Voltage Suppression (TVS) device.

Background

Packaging integrated circuits is often the final stage of semiconductor device fabrication. During the packaging process, the semiconductor die, which represents the core of the semiconductor device, is packaged in a housing that protects the die from physical damage and corrosion. For example, semiconductor dies are typically mounted on copper substrates using solder alloy reflow, conductive epoxy, and the like. The mounted semiconductor die is then typically encapsulated in a plastic or epoxy compound.

As power requirements for semiconductor devices increase, larger semiconductor dies (sometimes referred to as "large area semiconductor dies") become necessary to provide correspondingly higher levels of current handling. In some cases, such as in TVS diode applications, multiple large area dies must be connected in series in a stack configuration to provide a sufficiently high breakdown voltage. However, larger and larger semiconductor dies used in, for example, surface mount c-type (SMC) packages have an excessive solder voiding rate. The present disclosure is provided to address at least this disadvantage.

SUMMERY OF THE UTILITY MODEL

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. The disclosure is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In some embodiments, a package structure may include a first leadframe including a die pad, and a chip stack (stack) coupled to the first leadframe. The chip stack may include a Transient Voltage Suppression (TVS) device coupled to the die pad, a conductive wafer coupled to the TVS device, and a glass passivation tray (GPP) device coupled to the conductive wafer.

In some embodiments, a semiconductor package may include a first leadframe including a die pad, and a chip stack coupled to the first leadframe, wherein the chip stack includes a solder wafer sandwiched between a Transient Voltage Suppression (TVS) chip and a glass passivation tray (GPP) chip.

In some embodiments, a method for forming a package structure may include providing a first leadframe including a die pad, and coupling a chip stack to the first leadframe. The chip stack may include a Transient Voltage Suppression (TVS) device coupled to the die pad, a solder wafer coupled to the TVS device, and a glass passivation tray (GPP) device coupled to the solder wafer.

Drawings

The accompanying drawings illustrate an exemplary method of the present disclosure, including a practical application of its principles, as follows:

fig. 1 is a side view of a semiconductor package according to an embodiment of the present disclosure;

fig. 2 is a top view of a first leadframe of a semiconductor package according to an embodiment of the present disclosure;

fig. 3 is a side view of a first leadframe of a semiconductor package according to an embodiment of the present disclosure;

fig. 4 is a top view of a clip of a semiconductor package according to an embodiment of the present disclosure;

fig. 5 is a side view of a clip of a semiconductor package according to an embodiment of the present disclosure;

fig. 6 is a top view of a Glass Passivation Process (GPP) chip of a semiconductor package according to an embodiment of the present disclosure;

FIG. 7 is a side view of a GPP chip of a semiconductor package according to an embodiment of the present disclosure;

fig. 8 is a flow chart of a method according to an embodiment of the present disclosure.

The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict typical embodiments of the disclosure, and therefore should not be considered as limiting the scope. In the drawings, like numbering represents like elements.

In addition, for clarity of illustration, certain elements in some of the figures may be omitted, or may not be drawn to scale. For clarity of illustration, the cross-sectional view may be in the form of a "slice" or "near-sighted" cross-sectional view, omitting certain background lines that would otherwise be visible in a "true" cross-sectional view. Moreover, some reference numerals may be omitted from some drawings for clarity.

Detailed Description

Apparatus, packages, and methods according to the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the systems and methods are shown. The apparatus, packages, and methods may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the devices, packages, and methods to those skilled in the art.

One recent development in power semiconductor discrete packages is faster recovery capability. To improve this capability, embodiments of the present disclosure are directed to low capacity and high power TVS SMC products manufactured on a production line. More specifically, the package structure of the present disclosure reduces chip capacitance values by using a Glass Passivation Process (GPP) chip. The GPP chip has the characteristics of low capacity value and high reliability. To avoid the solder voiding problem inherent in larger SMC packages, embodiments of the present disclosure include a stacked structure in which the first chip is a GPP chip and the second chip is a planar Transient Voltage Suppression (TVS) chip. The third chip may be a solder wafer sandwiched between the first chip and the second chip. By replacing the solder paste with a solder wafer, the void area of the stack can be eliminated.

In some embodiments, the package structure may include a lead frame including a recessed pad, which increases solder retention. Further, the package structure may include improved clips for increased heat dissipation and faster recovery capability.

Referring to fig. 1, an exemplary embodiment of a semiconductor device or package structure 100 according to the present disclosure is shown. An exemplary package structure (hereinafter "structure") 100 may include a first leadframe 102 and a second leadframe 104. The first leadframe 102 may include a first end 105 and a second end 106. Although not shown, the first end 105 may be coupled to a substrate, PCB, or the like. The second end 106 may include a die pad 108 coupled to a chip stack 110 by solder 112. In other embodiments, the die pad 108 is attached to the chip stack 110 using a conductive epoxy or another suitable material. Although not limiting, first leadframe 102 and second leadframe 104 may be made of a conductive material (e.g., copper alloy, silver, etc.) and configured to provide electrical connections between die pads 108 and the circuits to which structure 100 is to be connected.

In some embodiments, chip stack 110 may include a TVS device/chip 114 coupled to die pad 108, a conductive wafer 116 coupled to TVS device 114, and a glass passivation tray (GPP) device 118 coupled to conductive wafer 116. In some embodiments, the conductive wafer 116 is a solder wafer. As shown, GPP device 118 may be coupled to clip 120 by solder 122. The clip 120 may be coupled to the second leadframe 104 by solder 124. In some embodiments, clip 120 is a conductive material (e.g., copper alloy, silver, etc.) that provides a direct electrical path between the substrate, die pad 108, and first and

second leadframes

102, 104. As further shown, the structure 100 may include an encapsulation 128 (e.g., an epoxy) surrounding the chip stack 110 and the clip 120. In some embodiments, the first and

second leadframes

102, 104 may extend outside of the encapsulant 128.

Turning now to fig. 2-3, the first leadframe 102 according to embodiments of the present disclosure will be described in more detail. As shown, the second end 106 of the first leadframe 102, including the first side 132 opposite the second side 134, may be generally planar. Coupled to the first side 132 is a die pad 108. In some embodiments, the die pad 108 may include one or more recessed channels 136. As shown, each recessed channel 136 includes a set of walls 140 defining a u-shaped or v-shaped cross-sectional profile. The recessed channels 136 allow for the ingress of solder 112, thereby improving the adhesion of the chip stack 110 and the die pad 108 during thermal cycling. In addition, recessed channels 136 reduce stress buildup during thermal cycling. Although two recessed channels 136 are shown in the pane configuration, it should be understood that the number and configuration of recessed channels 136 is non-limiting. As further shown, the first leadframe 102 may include a locking hole 138 and a set of corner notches 139, which provide flexibility to the first leadframe 102.

Turning now to fig. 4-5, the clip 120 according to embodiments of the present disclosure will be described in more detail. As shown, clip 120 may include a first contact region 142 at a first end 143 and a second contact region 144 at a second end 145. In some embodiments, the first contact region 142 is generally planar to increase contact with the GPP device 118. The second contact region 144 may extend generally perpendicular to the first contact region 142. The second contact region 144 may be electrically connected to the second leadframe 104. As further shown, the clip 120 may also include a set of clip gates (gates) 146 on opposite sides.

Turning now to fig. 6-7, GPP device 118 will be described in more detail in accordance with embodiments of the present disclosure. As shown, the GPP device 118 can include a passivation layer 150 (which can be a chip glass region) and a mesa region 152. Surrounding the mesa region 152 is a cutting region 156. In an exemplary embodiment, the passivation layer 150 may be electrically connected to the clip 120 (not shown) by solder 122.

Turning now to fig. 8, a method 200 for forming a package structure in accordance with an embodiment of the present disclosure will be described. At block 201, the method 200 may include providing a first leadframe including a die pad. At block 202, method 200 may include coupling a chip stack to the first leadframe, wherein the chip stack includes a TVS device coupled to the die pad, a solder wafer coupled to the TVS device, and a GPP device coupled to the solder wafer.

In some embodiments, at block 203, method 200 may optionally include coupling a clip to the GPP device and connecting the second leadframe to the clip. In some embodiments, the method may include providing an encapsulant (e.g., epoxy) around the chip stack and the clip, wherein the first and second lead frames extend outside of the encapsulant. In some embodiments, the method may include providing a first solder between the TVS device and the die pad, wherein the first solder extends within a recessed channel of the die pad. In some embodiments, the method may include connecting the first contact region of the clip to a GPP device with a second solder, and connecting the second contact region of the clip to the second leadframe with a third solder.

Although the illustrative method 100 is described above as a series of acts or events, the present disclosure is not limited by the illustrated ordering of such acts or events, unless otherwise specified. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the disclosure. Moreover, not all illustrated acts or events may be required to implement a methodology in accordance with the present disclosure. Further, method 100 may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated.

As used herein, an element or step recited in the singular and proceeded with the word "a" or "an" should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to "one embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

The use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Thus, the terms "comprising," "including," or "having," and variations thereof, are open-ended expressions and may be used interchangeably herein.

The phrases "at least one," "one or more," and/or "as used herein are open-ended expressions that are both conjunctive and disjunctive in operation. For example, the expressions "at least one of A, B and C", "at least one of A, B or C", "one or more of A, B and C", "one or more of A, B or C", and "A, B and/or C" refer to a alone, B alone, C, A alone and B together, a and C together, B and C together, or A, B and C together.

All directional references (e.g., proximal, distal, up, down, left, right, lateral, longitudinal, front, back, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are only used for identification purposes to aid the reader's understanding of the present disclosure. Directional references do not create limitations, particularly as to position, orientation, or use of the disclosure. Joinder references (e.g., attached, coupled, connected, and joined) are to be construed broadly and may include intermediate members between a collection of elements and relative movement between elements unless otherwise indicated. Thus, joinder references do not necessarily infer that two elements are directly connected and in fixed relation to each other.

Moreover, identifying references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority, but rather are used to distinguish one feature from another. The drawings are for illustration purposes only and the dimensions, positions, order and relative sizes as reflected in the accompanying drawings herein may vary.

Further, the terms "substantially" or "approximately" and the terms "approximately" or "approximately" may be used interchangeably in some embodiments and may be described using any relative metric acceptable to one of ordinary skill in the art. For example, these terms can be used as a comparison with reference parameters to indicate a deviation from a desired function. Although not limiting, deviations from the reference parameters can be, for example, within an amount of less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so forth.

The foregoing description of the example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in different ways and may generally include any set of one or more limitations that are disclosed or otherwise demonstrated in various ways herein.

Claims

1. A package structure, comprising:

a first lead frame including a die pad; and

a chip stack coupled to the first leadframe, wherein the chip stack comprises:

a Transient Voltage Suppression (TVS) device coupled to the die pad;

a conductive wafer coupled to the TVS device; and

a glass passivation tray (GPP) device coupled to the conductive wafer.

2. The package structure of claim 1, further comprising:

a clip coupled to a GPP device; and

a second leadframe connected to the clip.

3. The package structure of claim 2, further comprising an encapsulant surrounding the stack of chips and the clip, wherein the first and second lead frames extend outside of the encapsulant.

4. The package structure of claim 2, further comprising a first solder between the TVS device and the die pad.

5. The package structure of claim 4, wherein the die pad comprises a recessed channel, and wherein the first solder extends within the recessed channel.

6. The packaging structure of claim 5, wherein the recessed channel comprises a set of walls defining a u-shaped profile or a v-shaped profile.

7. The package structure of claim 4, wherein the clip comprises a first contact region and a second contact region, wherein the first contact region is connected to the GPP device by a second solder, and wherein the second contact region is connected to the second leadframe by a third solder.

8. The package structure of claim 1, wherein the conductive die is sandwiched between the TVS device and the GPP device.

9. A semiconductor package, comprising:

a first lead frame including a die pad; and

a chip stack coupled to the first leadframe, wherein the chip stack includes a solder wafer sandwiched between a Transient Voltage Suppression (TVS) chip and a glass passivation tray (GPP) chip.

10. The semiconductor package of claim 9, wherein TVS chip is coupled to the die pad by a first solder.

11. The semiconductor package of claim 10, further comprising:

a clip coupled to the GPP chip; and

a second leadframe connected to the clip.

12. The semiconductor package of claim 11, further comprising an encapsulant surrounding the chip stack and the clip, wherein the first and second lead frames extend outside of the encapsulant.

13. The semiconductor package of claim 11, wherein the die pad comprises a recessed channel, wherein the first solder extends within the recessed channel, and wherein the recessed channel comprises a set of walls defining a u-shaped profile or a v-shaped profile.

14. The semiconductor package of claim 11, wherein the clip comprises a first contact region and a second contact region, wherein the first contact region is connected to the GPP chip by a second solder, and wherein the second contact region is connected to the second leadframe by a third solder.