CN212341833U - Power supply buffer system - Google Patents
Power supply buffer system Download PDFInfo
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- CN212341833U CN212341833U CN202021374286.7U CN202021374286U CN212341833U CN 212341833 U CN212341833 U CN 212341833U CN 202021374286 U CN202021374286 U CN 202021374286U CN 212341833 U CN212341833 U CN 212341833U
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Abstract
The utility model relates to a power buffer system belongs to data storage protection technical field. The power buffering system includes: the main control circuit comprises a processor and a memory and is used for realizing the power-down protection of the memory; a power supply circuit; a tank circuit; the anti-surge circuit is arranged between the power supply circuit and the energy storage electric energy and is used for reducing the charging current of the energy storage circuit during power-on; the input end of the power supply detection circuit is connected with the output end of the power supply circuit and the power supply end of the processor in a sampling manner; the output end of the power supply detection circuit is connected with the processor. The utility model discloses a set up the anti-surge circuit between power supply circuit and tank circuit, can reduce the charging current to tank circuit when power supply buffer system goes up the electricity, make power supply circuit work within the design range to protective apparatus does not damage because of the too big of last electric surge, improves power buffer system's reliability.
Description
Technical Field
The utility model relates to a power buffer system belongs to data storage protection technical field.
Background
The Flash memory (Flash memory for short) in the power buffer system is a Non-Volatile (Non-Volatile) memory, can also hold data for a long time without power supply, and has a storage characteristic equivalent to a hard disk, which is the basis of the Flash memory becoming a storage medium of various digital devices such as mobile phones, flat panels, digital cameras, communication devices and the like. However, in the running process of the digital device, when the commercial power is suddenly cut off or the user unplugs the adapter, the digital device is abnormally powered off, and if the Flash memory has data read-write operation, the Flash data may be damaged.
In order to solve the problems of abnormal power failure of equipment and damage of Flash data, a power supply voltage monitor is generally adopted to monitor the power supply condition, and the level of a WP (write protect) pin of a Flash memory is pulled down when the power supply condition is abnormal, so that Flash write protection is realized and the Flash data can be recovered.
There are two ways to realize the pulling down of the WP pin level: firstly, a power supply voltage monitor directly triggers a protection circuit to directly pull down the level of a WP pin, so that the real-time performance is good; the method has the defects that the efficiency is low, the Flash memory can still perform read-write operation at the moment of pulling down, and the read-write operation cannot be stopped in time, so that the Flash memory cannot timely and clearly know which data read-write is finished, and the read-write operation needs to be performed again in the follow-up process; secondly, the power supply voltage monitor firstly alarms to the Flash memory, and then the Flash memory pulls down the level of the WP pin; the defect is that the Flash memory needs a period of operation time from alarm discovery to pull-down completion, the real-time performance is poor, and Flash data damage still exists even though write protection cannot be effectively realized.
In order to overcome the technical defects that the real-time performance and the efficiency cannot be achieved simultaneously in the prior art, a power-down protection circuit is proposed, for example, a chinese patent application with application publication No. CN 107910034 a, and the application discloses a power-down protection circuit for a Flash memory, which comprises a processor, a voltage stabilizing circuit, a comparator and an energy storage unit, wherein after a power-down occurs, on one hand, the processor and the Flash memory are maintained to work through the energy storage unit, and on the other hand, a power-down trigger signal generated in case of abnormal power-down of a power supply is timely sent to the processor through the comparator to alarm the processor, so that the processor can timely complete the operation of stopping reading and writing the Flash memory, and the Flash memory can be timely and effectively protected from being damaged in case of abnormal power-down of the power supply, and.
However, when the device is powered on, the overcurrent phenomenon is easy to occur, so that the power supply is damaged, and the reliability of the whole power supply system is poor.
SUMMERY OF THE UTILITY MODEL
An object of the present application is to provide a power buffering system for solving the problem of poor reliability of the existing power buffering system.
In order to achieve the above object, the present application provides a power buffering system, including:
the main control circuit comprises a processor and a memory and is used for realizing the power-down protection of the memory;
the power supply circuit is used for providing power supply for the main control circuit;
the energy storage circuit is used for continuously supplying power to the main control circuit after the power supply circuit is powered off;
the anti-surge circuit is arranged between the power supply circuit and the energy storage electric energy and is used for reducing the charging current of the energy storage circuit during power-on;
the input end of the power supply detection circuit is connected with the output end of the power supply circuit and the power supply end of the processor in a sampling manner; the output end of the power supply detection circuit is connected with the processor, so that when the power supply detection circuit detects that the power supply circuit is powered down, the processor performs power-down protection on the memory.
The utility model discloses a power buffering system's technical scheme's beneficial effect is: the utility model discloses set up energy memory between master control circuit and power supply circuit, realized that power supply circuit falls the power supply that lasts of back energy memory to master control circuit for the power fail safeguard of memory is accomplished to the treater. And the anti-surge circuit is arranged between the power supply circuit and the energy storage circuit, so that the charging current of the energy storage circuit can be reduced when the power supply buffer system is electrified, the power supply circuit works within a design range, the equipment is protected from being damaged due to overlarge electrification surge, and the reliability of the power supply buffer system is improved.
Furthermore, in order to improve the reliability of the operation of the anti-surge circuit, the anti-surge circuit comprises a switching tube, and a capacitor and a resistor which are connected in series; one end of the series circuit of the capacitor and the resistor is used for being connected with the output end of the power supply circuit, and the other end of the series circuit of the capacitor and the resistor is grounded; the switching tube is connected in series between the power supply circuit and the energy storage circuit, and the control end of the switching tube is connected with the connection point of the capacitor and the resistor.
Further, the switching tube is an MOS tube.
Further, in order to avoid interference, the power supply circuit further comprises a filter circuit, and the filter circuit is arranged between the power supply circuit and the anti-surge circuit.
Furthermore, in order to ensure the reliability of energy storage of the energy storage circuit, the energy storage circuit comprises a plurality of capacitors connected in parallel.
Furthermore, in order to ensure the reliability of the detection of the power supply voltage, the power supply detection circuit comprises an LM358 chip and a peripheral circuit thereof, wherein the inverting input end of the LM358 chip is connected with the power supply end of the processor in a sampling manner; the in-phase input end of the LM358 chip is connected with the output end of the power supply circuit in a sampling mode, and the LM358 chip compares the two voltages to detect whether the power supply circuit is powered down or not.
Further, in order to ensure the reliability of voltage acquisition, a first voltage division circuit is arranged between the inverting input end of the LM358 chip and the power supply end of the processor, and the inverting input end is connected with a voltage division point of the first voltage division circuit; and a second voltage division circuit is arranged between the in-phase input end of the LM358 chip and the output end of the power supply circuit, and the in-phase input end is connected with a voltage division point of the second voltage division circuit.
Furthermore, in order to avoid the abnormal starting phenomenon of the processor, the master control circuit further comprises a master control time sequence processing circuit, the input end of the master control time sequence processing circuit is connected with the power supply end of the processor, and the output end of the master control time sequence processing circuit is connected with the reset end of the processor to send a reset signal to the processor so as to start the processor.
Further, in order to improve the reliability of processor startup, the master timing processing circuit is UM803 RS.
Drawings
Fig. 1 is a schematic block diagram of a power buffering system of the present invention;
fig. 2 is a circuit structure diagram of the filter circuit and the surge protection circuit of the present invention;
fig. 3 is a circuit structure diagram of the energy storage circuit of the present invention;
fig. 4 is a circuit structure diagram of the power detection circuit of the present invention;
fig. 5 is a schematic diagram of the branch circuit of the master control timing sequence processing system of the present invention.
Detailed Description
Power supply buffer system embodiment:
the power supply buffer system is shown in fig. 1 and comprises a power supply circuit, a filter circuit, an anti-surge circuit, an energy storage circuit, a main control circuit and a power supply detection circuit. The main control circuit comprises a main control unit and a main control time sequence processing circuit, wherein the main control unit comprises a processor (CPU), a DDR memory, a Flash memory (the DDR memory and the Flash memory are collectively called as the memory), and a WiFi module.
The connection relationship of each circuit in the power supply buffer system is as follows: the filter circuit, the anti-surge circuit and the energy storage circuit which are connected in sequence are arranged between the power supply circuit and the main control circuit; in the main control unit, the memory and the WiFi module are both connected with the processor; the master control time sequence processing circuit is connected with a power supply end of a processor in the master control unit in a sampling mode, and outputs a reset end connected with the processor; the input end of the power supply detection circuit is connected with the power supply end of the processor in the main control unit and the output end of the power supply circuit, and the output end of the power supply detection circuit is connected with the processor.
The power supply circuit is used for supplying power for the main control circuit, and specifically is a USB circuit, and the output voltage of the USB circuit is 5V.
The filter circuit is used for filtering the power supply circuit, and the circuit structure of the filter circuit is as shown in fig. 2, and includes a capacitor C21, a resistor R58, and a capacitor C25. Wherein: the capacitor C21 is connected with the resistor R58 in series, one end of a series circuit of the capacitor C21 and the resistor R58 is connected with the output end of the USB circuit, and the other end of the series circuit is grounded; one end of the capacitor C25 is connected with the output end of the USB circuit, and the other end is grounded; the type of the capacitor C21 is 10 nF/25V-5%/C0402, the type of the resistor R58 is 2.2R-1%/R0603, and the type of the capacitor C25 is 0.1 uF/10%/0402/16V.
The anti-surge circuit is used for weakening the charging current of the energy storage circuit during power-on so as to weaken the impact of instantaneous large current for charging the energy storage element during power-on the power supply circuit, so that the power supply buffer system works within a design range, thereby protecting equipment and avoiding the damage of the equipment due to overlarge power-on surge, and the circuit structure of the anti-surge circuit is shown in figure 2: the circuit comprises a capacitor C90, a resistor R56 and a MOS transistor Q7; the capacitor C90 is connected with the resistor R56 in series, one end of a series circuit of the capacitor C90 and the resistor R56 is connected with the output end of the USB circuit, and the other end of the series circuit is grounded; the MOS tube Q7 is connected in series between the filter circuit and the energy storage circuit, the connection point of the capacitor C90 and the resistor R56 is connected with the G pole of the MOS tube Q7, the S pole of the MOS tube Q7 is connected with the output end of the USB circuit, and the D pole of the MOS tube Q7 is connected with the energy storage circuit. The MOS transistor Q7 is a PMOS transistor, and the type selection of the PMOS transistor is AO3407A, AO3413, UT2301G and HM 4407; the type of the capacitor C90 is 1 mu F/10%/0402/16V; the resistor R56 was used in the form of 100 k/5%/R0402. When the USB circuit is electrified, the current of the PMOS tube is zero, the capacitor C90 is conducted to start charging, and the voltage of the G pole of the PMOS tube is reduced; when the capacitor C90 is charged, the voltage of the G pole of the PMOS tube is zero, the PMOS tube is slowly opened in the process, and the damage to the USB circuit (namely an adapter) caused by overlarge surge current at the moment of electrifying the USB circuit is reduced.
The energy storage circuit is used for supplying power to the main control circuit when the power supply circuit is powered off and supporting the main control unit to perform corresponding protection processing so as to realize power-off protection; the circuit structure of the energy storage circuit is shown in fig. 3, and includes a plurality of capacitors connected in parallel, specifically, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C87, and a capacitor C91, wherein the capacitor C1, the capacitor C2, the capacitor C3, the capacitor C87, and the capacitor C91 are connected in parallel, one end of a parallel line of the energy storage circuit is connected with the D electrode of a MOS transistor Q7 in the anti-surge circuit through an anti-reverse diode D1, and the other end of the parallel line is grounded. The anti-reverse diode D1 is an IN5822 schottky diode.
The power supply detection circuit is used for detecting the power failure condition of the USB circuit and outputting a corresponding power failure trigger signal to the processor; the circuit structure of the power detection circuit is shown in fig. 4, and includes an LM358 chip (U3) and a peripheral circuit of the LM358 chip;
the peripheral circuit is a signal conversion circuit and comprises a resistor R12, a triode Q1, a resistor R8 and a resistor R9; the resistor R12 is 1K/5%/0402; the model of the triode Q1 is MMBT8050/SOT 23; the resistor R8 is 100K/5%/0402; the resistor R9 is 4.7K/5%/0402;
the LM358 chip comprises 8 pins, wherein the pin 1 is connected with a signal conversion circuit and is used for converting TTL level signals output by the pin 1 into CMO3.3V signals and outputting the signals to the processor; the pin 8 is connected with a power supply; the pin 4 is grounded; the pin 2 is an inverting input end, the pin 2 is connected with a power supply end VCC _ IO of the processor through a first voltage division circuit for sampling, the voltage of the processor is acquired, specifically, the pin 2 is connected with a voltage division point of the voltage division circuit for sampling, and the voltage (1.9V) of the voltage division point U3_2 is acquired, and the voltage division circuit is a voltage division circuit consisting of a resistor R14 and a resistor R15; the pin 3 is a non-inverting input end, the pin 3 is connected with an output end VCC5V0_ IN of the USB circuit through a second voltage division circuit for sampling, and is used for collecting the output voltage of the USB circuit, specifically, the pin 3 is connected with a voltage division point of the voltage division circuit for sampling, and collecting the voltage (1.9V) of the voltage division point U3_3, and the voltage division circuit is a voltage division circuit consisting of a resistor R22 and a resistor R25; the type of the resistor R14 is 2K/1%/0402, the type of the resistor R15 is 2.55K/1%/0603, the type of the resistor R22 is 3.3K/1%/0603, and the type of the resistor R25 is 2.4K/1%/0603;
in a short time after the power supply circuit is powered off, the voltage value (1.9V) of the voltage division point U3_2 of the first voltage division circuit is slowly converted and is acquired after voltage division; under the normal condition of the voltage of the power supply circuit, the voltage value of a voltage division point U3_3 acquired by the LM358 chip is 1.9V (theoretically, the voltage of a VCC5V0_ IN end is 5V, actually, the voltage is generally less than 5V, and under the condition that the voltage of a VCC5V0_ IN end is 4.8V, the voltage of the voltage division point is 2.2V), and if the power supply circuit is powered off, the voltage value of the acquired voltage division point U3_3 is 0V; the LM358 chip compares the voltage value of the voltage dividing point U3_2 with the voltage value of the voltage dividing point U3_3, under the condition that the power supply circuit is electrified, the voltage value of VCC5V0_ IN is not less than 4.525V, a high level signal is output through a pin 1, and a low level is output to the processor by a triode Q1; under the condition that the power supply circuit is not powered, the voltage value of VCC5V0_ IN is less than 4.525V, a low level signal is output through a pin 1, and a triode Q1 outputs a high level to the processor.
The main control time sequence processing circuit is used for outputting a reset signal to the processor of the main control unit after the power supply of the power supply buffer system is stable, so that the main control unit is normally started, and the phenomenon that the power supply of the main control unit is abnormal and the starting of the main control unit is abnormal because the electric energy stored in the energy storage circuit cannot be consumed in time when the power supply unit is repeatedly powered on/off can be avoided. As shown in fig. 5, the main control timing processing circuit includes a 3-pin microprocessor reset chip UM803RS, where pin 3 is used to collect the voltage of a power supply terminal VCC _ IO of the processor, pin 1 is grounded, and pin 2 is a reset signal output terminal, and outputs a reset signal to the reset terminal of the processor to start the processor (i.e., start the main control unit).
The working process of the power supply buffer system is as follows: when the power supply buffer system works normally, the power supply detection circuit acquires the voltage of the power supply end of the processor and the voltage of the output end of the power supply circuit in real time, if the power supply circuit is powered down, the power supply detection circuit feeds back and outputs a high-level signal (namely a power-down trigger signal) to the processor of the main control unit, the processor closes a non-essential module with larger power consumption, namely a WIFI module, and then the read-write protection processing of the memory is carried out;
when the system is powered on again, firstly, anti-surge treatment is carried out to eliminate startup surge; then, the master control time sequence is processed, so that the problem that the master control unit cannot be normally started is solved, and the stability of the whole system is improved; meanwhile, in order to save the time of inquiring the PID when the power is off, the PID number of the process needing to be closed is preprocessed and recorded in advance, so that the time of executing special storage of the CPU when the power is off abnormally is saved.
In the above embodiments, the energy storage circuit is a plurality of capacitors connected in parallel, and as another embodiment, the energy storage circuit may also be a plurality of storage batteries connected in series/parallel.
In the above-mentioned embodiment, anti-surge circuit simple structure, including electric capacity, resistance and MOS pipe, as other implementation modes, anti-surge circuit also can be for resistant excessive pressure surge circuit etc. realize corresponding function can, the utility model discloses do not restrict to anti-surge circuit's concrete structure. And the MOS tube is used as one kind of switching tube, and can also be replaced by a triode and other controllable switching tubes.
In the above embodiments, the output voltage of the power supply circuit is filtered by the filter circuit in order to avoid interference, and as another embodiment, the filter circuit may not be provided in a case where the output voltage is ensured to be reliable.
In the above embodiment, the power detection circuit employs the LM358 chip and its peripheral circuit, and the voltages collected by the non-inverting input terminal and the inverting input terminal are the voltages of the voltage dividing points, as other embodiments, other comparators with corresponding functions, such as LM339, LM393, TL081, may also be employed as the power detection circuit, and the voltage dividing circuit may not be provided under the condition that the detection result is accurate, and the voltage of the corresponding circuit may be directly collected.
In the above-mentioned embodiment, in order to avoid passing repeatedly the power on/off and make the treater start abnormity, still include master control sequential processing circuit among the master control circuit to adopt UM803RS as master control sequential processing circuit, as other implementation modes, the utility model discloses do not restrict master control sequential processing circuit's concrete implementation form, realize corresponding function can, and under the normal circumstances of assurance start-up, master control sequential processing circuit also can not set up.
The utility model realizes the continuous power supply of the main control circuit after the power supply circuit is powered down through the energy storage circuit, so that the processor completes the power down protection of the memory; the anti-surge circuit can reduce the charging current to the energy storage circuit when the power supply buffer system is electrified, so that the power supply circuit works in a design range, thereby protecting equipment from being damaged due to overlarge electrification surge and improving the reliability of the power supply buffer system; the problem of abnormal starting of the processor is solved through the master control time sequence processing circuit. The utility model discloses well main control circuit's treater can also realize a lot of other control functions except the power down protection function who realizes the memory, can be arranged in the well accuse host computer of intelligent house, realizes the control of intelligent house.
Claims (9)
1. A power buffering system, comprising:
the main control circuit comprises a processor and a memory and is used for realizing the power-down protection of the memory;
the power supply circuit is used for providing power supply for the main control circuit;
the energy storage circuit is used for continuously supplying power to the main control circuit after the power supply circuit is powered off;
the anti-surge circuit is arranged between the power supply circuit and the energy storage electric energy and is used for reducing the charging current of the energy storage circuit during power-on;
the input end of the power supply detection circuit is connected with the output end of the power supply circuit and the power supply end of the processor in a sampling manner; the output end of the power supply detection circuit is connected with the processor, so that when the power supply detection circuit detects that the power supply circuit is powered down, the processor performs power-down protection on the memory.
2. The power buffering system of claim 1, wherein the anti-surge circuit comprises a switching tube, and a capacitor and a resistor connected in series; one end of the series circuit of the capacitor and the resistor is used for being connected with the output end of the power supply circuit, and the other end of the series circuit of the capacitor and the resistor is grounded; the switching tube is connected in series between the power supply circuit and the energy storage circuit, and the control end of the switching tube is connected with the connection point of the capacitor and the resistor.
3. The power buffering system of claim 2, wherein the switching transistor is a MOS transistor.
4. The power buffering system of claim 1, further comprising a filter circuit disposed between the power supply circuit and the anti-surge circuit.
5. The power buffering system of claim 1, wherein the tank circuit comprises a plurality of capacitors connected in parallel.
6. The power buffering system according to claim 1 or 2, wherein the power detection circuit comprises an LM358 chip and its peripheral circuits, and the inverting input terminal of the LM358 chip samples the power terminal connected to the processor; the in-phase input end of the LM358 chip is connected with the output end of the power supply circuit in a sampling mode, and the LM358 chip compares the two voltages to detect whether the power supply circuit is powered down or not.
7. The power buffering system according to claim 6, wherein a first voltage dividing circuit is disposed between an inverting input terminal of the LM358 chip and a power supply terminal of the processor, the inverting input terminal being connected to a voltage dividing point of the first voltage dividing circuit; and a second voltage division circuit is arranged between the in-phase input end of the LM358 chip and the output end of the power supply circuit, and the in-phase input end is connected with a voltage division point of the second voltage division circuit.
8. The power buffering system of claim 1 or 2, wherein the master control circuit further comprises a master timing processing circuit, an input terminal of the master timing processing circuit is connected to a power terminal of the processor, and an output terminal of the master timing processing circuit is connected to a reset terminal of the processor to send a reset signal to the processor to start the processor.
9. The power buffering system of claim 8, wherein the master timing processing circuit is UM803 RS.
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| CN202021374286.7U CN212341833U (en) | 2020-07-13 | 2020-07-13 | Power supply buffer system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113886325A (en) * | 2021-11-04 | 2022-01-04 | 珠海奔图电子有限公司 | On-chip system, circuit, image forming device and power supply method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113886325A (en) * | 2021-11-04 | 2022-01-04 | 珠海奔图电子有限公司 | On-chip system, circuit, image forming device and power supply method |
| CN113886325B (en) * | 2021-11-04 | 2024-01-02 | 珠海奔图电子有限公司 | System on chip, circuit, image forming device and power supply method |
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