CN212341328U

CN212341328U - Ethernet return loss testing device and testing system

Info

Publication number: CN212341328U
Application number: CN202020680870.9U
Authority: CN
Inventors: 陈四平
Original assignee: Hefei Kangxinwei Storage Technology Co Ltd
Current assignee: Hefei Kangxinwei Storage Technology Co Ltd
Priority date: 2020-04-28
Filing date: 2020-04-28
Publication date: 2021-01-12
Anticipated expiration: 2030-04-28

Abstract

The utility model provides an Ethernet return loss testing device and a testing system, wherein the Ethernet return loss testing device comprises a testing board; a connector disposed on the test board; the balance converter is arranged on the test board; the address switch selector is arranged on the test board; the network interface is arranged on the test board and is connected with equipment to be tested; the network interface is connected with a pair of differential pins of the balance converter through the address switch selector, a single-ended pin of the balance converter is connected with the connector, and the communication state of each pin of the network interface and the balance converter is controlled through the address switch selector. Utilize the utility model discloses, not only can effectively avoid SMA coaxial cable and test fixture's damage, improve the efficiency of ethernet return loss test moreover.

Description

Ethernet return loss testing device and testing system

Technical Field

The utility model relates to an ethernet return loss detection technical field especially relates to an ethernet return loss testing arrangement and test system.

Background

Ethernet Return Loss (RL) refers to a Loss that measures the proportion of a transmission signal that is reflected to the transmitting end. In the physical layer interface performance of ethernet, return loss is an important indicator. By measuring the return loss, the relationship between the impedance designed by the single board and the characteristic impedance of the twisted pair can be clarified, and the smaller the return loss of the tested network port of the single board is, the better the input impedance characteristic of the single board is matched with the impedance of the twisted pair.

The existing ethernet return loss test fixture respectively leads out the 4 pairs of differential signals, and then is sequentially connected to a network analyzer through an SMA (complementary-A) coaxial cable to test the signals pair by pair. However, in the using process, the SMA coaxial cable is inconvenient to connect to the test fixture, and the cable is often easily damaged; after the test of one pair of differential signals, the other pair is changed, and the speed of repeatedly changing the SMA coaxial cable is low, so that the test efficiency is low.

SUMMERY OF THE UTILITY MODEL

In view of the above prior art's shortcoming, the utility model aims to provide an ethernet return loss testing arrangement and test system for it is inconvenient to solve the ethernet return loss test fixture test among the prior art, leads to the cable to damage and the technical problem that efficiency of software testing is low easily.

In order to achieve the above objects and other related objects, the present invention provides an ethernet return loss testing apparatus, which includes:

a test board;

a connector disposed on the test board;

the balance converter is arranged on the test board;

the address switch selector is arranged on the test board; and

the network interface is arranged on the test board and is connected with equipment to be tested;

the network interface is connected with a pair of differential pins of the balance converter through the address switch selector, a single-ended pin of the balance converter is connected with the connector, and the communication state of each pin of the network interface and the balance converter is controlled through the address switch selector.

In an alternative embodiment, the address switch selector comprises a dip switch.

In an optional embodiment, any pin of the network interface is connected with a first pin of a dial key of the dial switch, and a second pin of the dial key is connected with a differential pin of the balance converter.

In an optional embodiment, the network interface comprises 4 pairs of pins, and the dial switch at least comprises 8 dial keys in one-to-one correspondence with the 4 pairs of pins of the network interface; each pair of pins of the network interface is respectively connected with first pins of two dial keys in the dial switch, and second pins of the two dial keys are respectively connected with two differential pins of the balance converter.

In an optional embodiment, the address switch selector comprises a single chip controller.

In an optional embodiment, the single chip microcomputer controller comprises a single chip microcomputer and two analog switches, and control ends of the analog switches are connected with the single chip microcomputer.

In an alternative embodiment, the connectors are connected to the baluns, the baluns are connected to the address switch selectors, and the address switch selectors are connected to the network interfaces through wires disposed on the test board.

In order to achieve the above objects and other related objects, the present invention also provides an ethernet return loss test system, which comprises:

the Ethernet return loss testing device comprises a testing board, a connector, a balance converter, an address switch selector and a network interface, wherein the connector, the balance converter, the address switch selector and the network interface are arranged on the testing board, the network interface is connected with equipment to be tested, the network interface is connected with a pair of differential pins of the balance converter through the address switch selector, a single-ended pin of the balance converter is connected with the connector, and the communication state of each pin of the network interface and the balance converter is controlled through the address switch selector;

a network analyzer connected with the connector.

In an optional embodiment, the test system further comprises an oscilloscope or a computer.

In an optional embodiment, the test system further comprises an adapter, and the network analyzer is connected with the oscilloscope or the computer through the adapter.

The Ethernet return loss testing device and the testing system of the utility model can solve the problem that the SMA coaxial cable is repeatedly twisted during the existing Ethernet return loss test, thereby effectively avoiding the damage of the SMA coaxial cable and the testing jig;

the utility model discloses an ethernet return loss testing arrangement and test system owing to adopt dial switch or single chip controller control each pin of network interface with the intercommunication state of balun, switching speed is faster, consequently can improve the efficiency of ethernet return loss test.

Drawings

Fig. 1 is a schematic structural diagram of an exemplary ethernet return loss test system.

Fig. 2 shows a schematic structural diagram of the ethernet return loss testing apparatus of the present invention.

Fig. 3 is a schematic structural diagram of the ethernet return loss test system of the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

Fig. 1 shows a frame diagram of an ethernet return loss test system, and referring to fig. 1, the ethernet return loss test system includes a test fixture 100 ', a Network Analyzer 200 ' (Vector Network Analyzer), and an oscilloscope 300 '. The test fixture 100 'includes a test board 105', and 4 pairs of first SMA (complementary-a) connectors 102 '(SMA connectors DA +/DA-, DB +/DB-, DC +/DC-, DD +/DD-), an RJ45 interface 101', a Balun 103 'module (Balun, transliteration is Balun), and second SMA connectors (SMA connectors 104 a', 104b ', and 104 c') connected to respective pins of the Balun 103 'disposed on the test board 105'; the 4 pairs of the first SMA connectors 102 ' are connected to the 4 pairs of pins of the RJ45 interface 101 ' through wires (not shown) disposed on the test board 105 ', respectively, and are used for leading out four pairs of differential signals (differential signals DA +/DA-, differential signals DB +/DB-, differential signals DC +/DC-, and differential signals DD +/DD-) of ethernet; the balun 103 'has three pins, which are a single-ended pin and two differential pins, the single-ended pin of the balun 103' is connected to the SMA connector 104c 'through a wiring (not shown) disposed on the test board 105', the other two differential pins are connected to the SMA connectors 104a 'and 104 b' through wirings (not shown) disposed on the test board 105 ', the SMA connectors 104 a' and 104b 'are connected to one of the 4 pairs of first SMA connectors 102' through SMA coaxial cables, the single-ended pin of the balun 103 'is connected to the network analyzer 200' through the SMA connector 104c ', and the network analyzer 200' is connected to the infinium Oscilloscope 300 '(oscillososcope) through a GPIB (General-Purpose Interface Bus) -USB adapter 400'.

The test principle of the test system shown in fig. 1 is as follows: the network analyzer 200 'will send out a single-ended signal, convert the single-ended signal into a differential signal through the balun 103', and then connect to one of the 4 pairs of first SMA connectors 102 'of the test fixture 100', and then connect to the DUT of the device under test 500 'through the RJ45 interface 101'; the reference receiver is arranged in the network analyzer 200 'and can track the result of the energy reflection of the transmitted signal and calculate the return loss, and the oscilloscope 300' can be used for displaying and analyzing the test result. Basic definition of return loss: return loss is 20lg (| Vr/Vi |), where Vi is the incident voltage and Vr is the reflected voltage.

Specifically, when the test system shown in fig. 1 is used to perform the ethernet return loss test, 4 pairs of differential signals led out through 4 pairs of first SMA connectors 102' are tested pair by pair. That is, only one pair of differential signals can be analyzed at a time when the test is performed, that is, the SMA connectors 104a ' and 104b ' are connected to only one of the 4 pairs of first SMA connectors 102 ' through the SMA coaxial cables, respectively, when the test is performed. By way of example, starting from DA +/DA-, going to DB +/DB-, DC +/DC-, DD +/DD-, when testing the extracted differential signal DA +/DA-, it is necessary to connect SMA connectors DA + and DA-to SMA connectors 104a ' and 104b ' of two differential pins of the balun 103 ' through SMA coaxial cables, after the return loss of the differential signal DA +/DA-is tested, it is necessary to first unscrew the SMA coaxial cables connected to SMA connectors DA + and DA-, then insert and screw on the SMA connectors DB + and DB-corresponding to the next pair of differential signals DB +/DB-to be tested, and so on, until the test and analysis of the differential signal DD +/DD-are completed. It should be noted that, during the switching process of the SMA coaxial cable, the SMA coaxial cable needs to be unscrewed and screwed, which is time consuming, and the SMA coaxial cable and the test fixture 100' are easily damaged, and the test efficiency is delayed.

In order to solve the above problem, an embodiment of the present invention provides a novel ethernet return loss testing apparatus 100 and testing system, wherein fig. 2 shows a schematic structural diagram of the ethernet return loss testing apparatus 100 of this embodiment, and fig. 3 shows a schematic structural diagram of the ethernet return loss testing system of this embodiment.

Referring to fig. 2, the ethernet return loss testing apparatus 100 includes a testing board 105, and a balun 103, an address switch selector, a network interface, and a connector 104 disposed on the testing board 105; the network interface is connected with the device under test 500, the network interface is connected with a pair of differential pins of the balun 103 through the address switch selector, a single-ended pin of the balun 103 is connected with the connector 104, the communication state of each pin of the network interface and the balance converter 103 can be controlled by the address switch selector, thereby controlling the on and off of the four pairs of differential signals of the Ethernet, eliminating the process that the test fixture 100' shown in FIG. 1 needs to frequently switch channels when performing the Ethernet return loss test (each switching is accompanied by the loosening/tightening process of the SMA connecting cable), therefore, the channel switching time is saved, the testing efficiency is improved, and the damage to the SMA connection cable and the testing jig 100' in the process of unscrewing/screwing the SMA connection cable can be avoided.

Referring to fig. 2 and fig. 3, in this embodiment, the network interface may adopt, for example, an RJ45 interface 101, the RJ45 interface 101 is the most commonly used interface for ethernet, and has eight total pairs of pins (corresponding to DA +, DA-, DB +, DB-, DC +, DC-, DD +, DD- "in fig. 2, respectively), the device 500 to be tested is plugged on the test board 105 through the RJ45 interface 101, and four pairs of differential signals (differential signals DA +/DA-, differential signals DB +/DB-, differential signals DC +/DC-, and differential signals DD +/DD-) of the ethernet may be respectively led out through 8 pins of the RJ45 interface 101, so as to perform the echo loss test of the ethernet. It should be noted that, although the RJ45 interface 101 is used as the network interface in this embodiment, it is understood that, in other embodiments, the network interface may also be one of an RJ-11 interface, an SC fiber interface, an FDDI interface, an AUI interface, a BNC interface, and a Console interface.

Referring to fig. 2 and 3, in the present embodiment, the address switch selector includes a dial switch 102, where the dial switch 102 is also called a DIP switch, a toggle switch, an over-frequency switch, an address switch, a DIP switch, a digital switch, and a DIP switch, and is an address switch for operation control, and adopts a binary coding principle of 0/1. As an example, in terms of a foot position, the dial switch 102 may be a direct-insertion (DIP) dial switch or a surface-mounted device (SMD) dial switch, and in terms of a dial manner, the dial switch 102 may be a flat dial switch or a side dial switch; in terms of pin pitch, the dip switch 102 may be a 2.54mm pin pitch dip switch or a 1.27mm pin pitch dip switch. By way of example, the dip switch 102 may be an 8-bit or greater than 8-bit dip switch, for example, to ensure that each RJ45 interface 101 has a unique corresponding dip key. As an example, as shown in fig. 2-3, the dial switch 102 is an 8-bit dial switch, and includes 8 dial keys, which correspond to 8 switches, respectively corresponding to switches 1-8 in the figure.

Referring to fig. 2 and 3, in the present embodiment, each pair of pins (DA +/DA-, DB +/DB-, DC +/DC-, or DD +/DD-) of the RJ45 interface 101 is respectively connected to first pins (located at each key) of two keys (two pins for each key) in the dial switch 102, and second pins of the two keys are respectively connected to two differential pins (located at lower side leads of the balun 103 in fig. 2 and 3) of the balun 103. As an example, as shown in fig. 2-3, the positive pins DA +, DB +, DC +, and DD + of each pair of pins (DA +/DA-, DB +/DB-, DC +/DC-, or DD +/DD-) of the RJ45 interface 101 are commonly connected to the differential pin on the bottom left side (with respect to the orientation in fig. 2) of the balun 103 through

switches

1, 3, 5, 7 of the dip switch 102, respectively, the negative pins DA-, DB-, DC-, and DD-of each pair of pins (DA +/DA-, DB +/DB-, DC +/DC-, or DD +/DD-) of the RJ45 interface 101 are connected in common to the differential pins on the bottom-to-side (with respect to the orientation in FIG. 2) of the balun 103 through switches 2, 4, 6, and 8, respectively. As an example, as shown in fig. 2 and 3, when performing the test, the switch states of the switches (i.e., the dial keys) of the dip switch 102 are as follows: when DA +/DA-is tested, the switches 1 and 2 are turned on, and other switches are turned off; when testing DB +/DB-, switches 3 and 4 are opened, and other switches are closed; when testing DC +/DC-, switches 5 and 6 are opened, and other switches are closed; when the DD +/DD-is tested, the switches 7 and 8 are opened, and other switches are closed.

Referring to fig. 2 and 3, in the present embodiment, the Balun 103 is a Balance-unbalance (Balun), and a single-ended pin of the Balun 103 (located at a right lead of the Balun 103 in fig. 2 and 3) is connected to the connector 104 through a lead disposed on the test board 105. In this embodiment, the balun 103 may convert a single-ended signal sent by the network analyzer 200 to be mentioned later into a pair of differential signals, and transmit the pair of differential signals from two differential pins of the balun 103 to DA/DB/DC/DD pins of the RJ45 interface 101; and a pair of differential signals, which are derived through DA, DB, DC or DD pins of RJ45 interface 101, may be converted to single-ended signals for transmission to network analyzer 200 for return loss analysis.

Referring to fig. 2 and 3, in the present embodiment, the connector 104 may adopt an SMA connector for connecting with the network analyzer 200 through an SMA connection cable to achieve good connection performance. The SMA connector is a coaxial connector with a small-sized threaded connection, which is widely applied, is suitable for the application in the microwave field with the frequency range from direct current to 26.5GHz, such as telecommunication communication, network, wireless communication, detection and measurement instruments, and is suitable for connecting a radio frequency cable or a microstrip line in a radio frequency loop of microwave equipment and a digital communication system. It should be noted that the connector 104 may also be a radio frequency/microwave connector in other forms.

Referring to fig. 3, fig. 3 shows an ethernet return loss testing system of the present invention, the testing system includes the ethernet return loss testing apparatus 100 described above, and a network analyzer 200 used in cooperation with the testing system, the ethernet return loss testing apparatus 100 refers to the above description in detail, and details are not repeated herein, and the network analyzer 200 is connected to the connector 104 of the ethernet return loss testing apparatus 100. As an example, the network Analyzer 200 may be, for example, a Vector Network Analyzer (VNA).

Referring to fig. 3, in the present embodiment, the ethernet return loss test system further includes an adapter 400, and an oscilloscope 300 or a computer; the network analyzer 200 is connected to the oscilloscope 300 or the computer through the adapter 400. By way of example, the adapter 400 may be, for example, a USB-GPIB adapter 400, and the oscilloscope 300 may be, for example, an Infiniium oscilloscope 300.

During testing, the network analyzer 200 sends out a single-ended signal, converts the single-ended signal into a differential signal through the balun 103 of the ethernet return loss testing apparatus 100, switches and connects to a pair of designated pins of the RJ45 interface 101 through state change of each switch in the dial switch 102, and transmits the differential signal to the device 500 to be tested through the RJ45 interface 101; the network analyzer 200 is internally provided with a reference receiver, and can track the result of the energy reflection of the transmitted signal and calculate the return loss. The oscilloscope 300 or computer (with corresponding computer program stored thereon) may be used to display and analyze test results.

It should be noted that, in other embodiments, the address switch selector may also adopt a single chip controller. Specifically, the single chip microcomputer controller may be, for example, two analog switches controlled by a single chip microcomputer to implement the above-mentioned function of the 8-bit dial switch 102, so as to respectively control four pairs of differential signals of DA/DB/DC/DD, thereby implementing more efficient test efficiency. As an example, the analog switch may be, for example, a single-ended 4-channel analog switch (such as RS550, FSA550), a common input/output pin of each 4-channel analog switch is directly connected to a differential pin of the balun 103, an input/output pin of each 4-channel analog switch is connected to a pin of the RJ45 interface 101, and then the on state of each channel in the 2 single-ended 4-channel switches is controlled by a single-chip microcomputer, so that the pair of differential pins of the balun 103 is simultaneously connected to a pair of pins (DA +/DA-, DB +/DB-, DC +/DC-, or DD +/DD-) of the RJ45 interface 101. By way of example, the analog switch may also employ a single-ended 8-channel multiplexer (such as CD4051), but each single-ended 8-channel multiplexer uses only 4 of the 8 channels. It should be noted that other single chip controllers capable of implementing 8-way in/2-way out switching functions are also suitable for the technical solution of the present invention.

The ethernet return loss test apparatus 100 of the present invention includes a test board 105; a connector 104 disposed on the test board 105; a balun 103 disposed on the test board 105; an address switch selector disposed on the test board 105; the network interface is arranged on the test board 105 and is connected with the equipment to be tested 500; the network interface is connected with a pair of differential pins of the balun 103 through the address switch selector, a single-ended pin of the balun 103 is connected with the connector 104, and the connection state of each pin of the network interface and the balun 103 is controlled through the address switch selector. Utilize the utility model discloses, not only can effectively avoid SMA coaxial cable and test fixture's damage, improve the efficiency of ethernet return loss test moreover.

In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

Reference throughout this specification to "one embodiment," "an embodiment," or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.

It will also be appreciated that one or more of the elements shown in the figures can also be implemented in a more separated or integrated manner, or even removed for inoperability in some circumstances or provided for usefulness in accordance with a particular application.

Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.

As used in the description herein and throughout the claims that follow, "a", "an", and "the" include plural references unless otherwise indicated. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in …" includes "in …" and "on … (on)".

The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the invention and are to be included within the spirit and scope of the present invention.

The system and method have been described herein in general terms as providing details to facilitate the understanding of the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

Thus, although the present invention has been described herein with reference to particular embodiments thereof, freedom of modification, various changes and substitutions are intended in the foregoing disclosure, and it should be understood that in some instances some features of the present invention will be employed without a corresponding use of other features without departing from the scope and spirit of the present invention as set forth. Accordingly, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.

Claims

1. An Ethernet return loss testing device, characterized in that the Ethernet return loss testing device comprises:

a test board;

a connector disposed on the test board;

the balance converter is arranged on the test board;

the address switch selector is arranged on the test board; and

2. An ethernet return loss test apparatus according to claim 1, wherein said address switch selector comprises a dip switch.

3. An Ethernet return loss test device according to claim 2, wherein any pin of said network interface is connected to a first pin of a dial key of said dial switch, and a second pin of said dial key is connected to a differential pin of said balun.

4. An ethernet return loss test apparatus according to claim 3, wherein said network interface comprises 4 pairs of pins, and said dial switch comprises at least 8 dial keys in one-to-one correspondence with the 4 pairs of pins of said network interface; each pair of pins of the network interface is respectively connected with first pins of two dial keys in the dial switch, and second pins of the two dial keys are respectively connected with two differential pins of the balance converter.

5. An ethernet return loss test device according to claim 1, wherein said address switch selector comprises a single chip controller.

6. The Ethernet return loss testing device of claim 5, wherein the single-chip microcomputer controller comprises a single-chip microcomputer and two analog switches, and control ends of the analog switches are connected with the single-chip microcomputer;

each pin of the network interface is respectively connected with one input/output end of the analog switch; and the common input/output ends of the two analog switches are respectively connected with two differential pins of the balance converter.

7. An Ethernet return loss testing device according to claim 1, wherein said connector is connected to said balun, said balun is connected to said address switch selector, and said address switch selector is connected to said network interface via wiring disposed on said test board.

8. An Ethernet return loss test system, the test system comprising:

a network analyzer connected with the connector.

9. The Ethernet return loss test system of claim 8, wherein the test system further comprises an oscilloscope or a computer.

10. The ethernet return loss test system of claim 9, further comprising an adapter through which said network analyzer is connected to said oscilloscope or said computer.