CN212323987U - Current-limiting circuit applied to bidirectional load and bidirectional load voltage stabilizer - Google Patents
Current-limiting circuit applied to bidirectional load and bidirectional load voltage stabilizer Download PDFInfo
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- CN212323987U CN212323987U CN202020973681.0U CN202020973681U CN212323987U CN 212323987 U CN212323987 U CN 212323987U CN 202020973681 U CN202020973681 U CN 202020973681U CN 212323987 U CN212323987 U CN 212323987U
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Abstract
A current limiting circuit and a bidirectional load voltage stabilizer applied to a bidirectional load are provided, wherein the current limiting circuit clamps a source current below a first target value and clamps a sink current below a second target value by adding a first current limiting sub-circuit and a second current limiting sub-circuit, so that the clamping effect of the source current and the sink current of the bidirectional load is achieved, the phenomenon that the bidirectional load is damaged due to the fact that the current value of the source current or the sink current of the bidirectional load is too large is avoided, only the first current limiting sub-circuit and the second current limiting sub-circuit are added, large-size devices such as a comparator and an output voltage logic processing circuit do not need to be added, the circuit is simple and suitable for the bidirectional load, and the problems that a circuit structure is complex and the bidirectional load is not suitable in a traditional current limiting circuit are solved.
Description
Technical Field
The application belongs to the technical field of current-limiting circuits, and particularly relates to a current-limiting circuit applied to a bidirectional load and a bidirectional load voltage stabilizer.
Background
With the improvement of semiconductor technology and the rapid development of the integrated circuit industry, the power management chip has also made great progress. The voltage regulator, which is a kind of power management chip, plays a very important role in the power market. Because the voltage stabilizer needs to drive the load, when the current at the load end exceeds the rated bearing capacity of the chip and lasts for a period of time, avalanche breakdown of the driving tube can be caused, and therefore the chip fails. Therefore, in practical applications, designers may add a current limiting circuit to the chip to improve the reliability and the service life of the chip.
The traditional current limiting circuit generally adopts a sampling tube to mirror the current in a driving tube, the current flows through a resistor to generate a voltage, the voltage is compared with a reference voltage through a comparator, and the output voltage controls the grid end voltage of the driving tube through a logic processing circuit, so that the current limiting function is achieved. However, the circuit structure of the scheme is complex, the occupied chip area is large, and the scheme is only suitable for application of a unidirectional load, for example, when the scheme is applied to a bidirectional load, a sampling tube, a comparator, a resistor, an output voltage and a logic processing circuit are added in both directions, so that the small area of the chip is not facilitated.
Therefore, the traditional current limiting circuit has the problems of complex circuit structure and unsuitability for bidirectional loads.
SUMMERY OF THE UTILITY MODEL
An object of the application is to provide a current-limiting circuit and a bidirectional load voltage regulator for bidirectional load, which aim at solving the problem of large occupied area in the conventional technical scheme.
A first aspect of an embodiment of the present application provides a current limiting circuit, where the bidirectional load includes an output terminal, a first switch circuit for transmitting a source current to the output terminal, and a second switch circuit for transmitting a sink current to the output terminal, and the current limiting circuit includes:
a first current limiting sub-circuit connected to the first switching circuit, the first current limiting sub-circuit to clamp the source current below a first target value; and
a second current limiting sub-circuit connected to the second switching circuit, the second current limiting sub-circuit configured to clamp the sink current below a second target value.
In one embodiment, the first current limiting sub-circuit comprises:
the first detection circuit is connected with the input end of the first switch circuit and a power supply, and is used for detecting the source current and outputting a first detection electric signal; and
a pull-up circuit connected to the power supply and the first switch circuit, the pull-up circuit being configured to turn on and control an on-degree of the first switch circuit under control of the first detection electrical signal to clamp the pull current below the first target value.
In one embodiment, the first detection circuit includes a first resistor, a first terminal of the first resistor is a first terminal of the first detection circuit, the first terminal of the first detection circuit is connected to the power supply, a second terminal of the first resistor is a second terminal of the first detection circuit, and the second terminal of the first detection circuit is connected to the input terminal of the first switch circuit and the control terminal of the pull-up circuit.
In one embodiment, the pull-up circuit comprises a first switch tube, the high potential end of the first switch tube is the input end of the pull-up circuit, the input end of the pull-up circuit is connected with the power supply, the control end of the first switch tube is the control end of the pull-up circuit, the control end of the pull-up circuit is connected with the second end of the first detection circuit and the input end of the first switch circuit, the low potential end of the first switch tube is the output end of the pull-up circuit, and the output end of the pull-up circuit is connected with the control end of the first switch circuit.
In one embodiment, the second current limiting sub-circuit comprises:
the second detection circuit is connected with the output end of the second switch circuit and the ground, and is used for detecting the size of the current and outputting a second detection electric signal; and
and the pull-down circuit is connected with the second detection circuit and the second switch circuit, and is used for conducting under the control of a second detection electric signal and controlling the conducting degree of the second switch circuit so as to clamp the sink current below the second target value.
In one embodiment, the second detection circuit comprises: the first end of the second resistor is the first end of the second detection circuit, the first end of the second detection circuit is connected with the output end of the second switch circuit and the control end of the pull-down circuit, the second end of the second resistor is the second end of the second detection circuit, and the second end of the second detection circuit is connected with the ground.
In one embodiment, the pull-down circuit includes a second switch tube, the high potential end of the second switch tube is the input end of the pull-down circuit, the input end of the pull-down circuit is connected with the control end of the second switch circuit, the control end of the second switch tube is the control end of the pull-down circuit, the control end of the pull-down circuit is connected with the first end of the second detection circuit and the output end of the second switch circuit, the low potential end of the second switch tube is the output end of the pull-down circuit, and the output end of the pull-down circuit is connected with the ground.
In one embodiment, the first switch circuit includes a PMOS transistor, a source of the PMOS transistor is an input terminal of the first switch circuit, a gate of the PMOS transistor is a control terminal of the first switch circuit, and a drain of the PMOS transistor is an output terminal of the first switch circuit.
In one embodiment, the second switch circuit includes an NMOS transistor, a drain of the NMOS transistor is an input terminal of the second switch circuit, a gate of the NMOS transistor is a control terminal of the second switch circuit, and a source of the NMOS transistor is an output terminal of the second switch circuit.
A second aspect of an embodiment of the present application provides a bidirectional load regulator, including: a current limiting circuit as described in the first aspect of an embodiment of the present application.
According to the current limiting circuit applied to the bidirectional load, the source current is clamped below the first target value and the sink current is clamped below the second target value by adding the first current limiting sub-circuit and the second current limiting sub-circuit, so that the clamping effect of the source current and the sink current of the bidirectional load is achieved, the phenomenon that the bidirectional load is damaged due to the fact that the current value of the source current or the sink current of the bidirectional load is too large is avoided, only the first current limiting sub-circuit and the second current limiting sub-circuit are added, a comparator, a logic processing circuit and other large-volume devices are not needed to be added for output voltage, the circuit is simple and applicable to the bidirectional load, and the problems that the circuit structure is complex and the bidirectional load is not applicable in the traditional current limiting circuit are solved.
Drawings
Fig. 1 is a circuit diagram of a current limiting circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic circuit diagram of a first current limiting sub-circuit and a second current limiting sub-circuit of the current limiting circuit shown in FIG. 1;
fig. 3 is an exemplary circuit schematic of the current limiting circuit shown in fig. 2.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 1 shows a schematic structural diagram of a current limiting circuit provided in a first aspect of an embodiment of the present application, and for convenience of description, only a part related to the embodiment is shown, and details are as follows:
in the current limiting circuit applied to the bidirectional load in this embodiment, the bidirectional load includes an output terminal, a first switch circuit 100 for transmitting a pull-up current IOUT1 to the output terminal, and a second switch circuit 200 for outputting a sink current IOUT2 to the output terminal, and optionally, the output terminal of the first switch circuit 100 and the input terminal of the second switch circuit 200 are connected in common as the output terminal of the bidirectional load.
It should be understood that the first switching circuit 100 of the bidirectional load may be constituted by a switching tube; the second switching circuit 200 of the bidirectional load may be formed of a switching tube; the first switch circuit 100 and the second switch circuit 200 are not turned on at the same time, that is, only one of the first switch circuit 100 and the second switch circuit 200 can be turned on at the same time, wherein the first switch circuit 100 is driven by the first driving signal Vdrive _ p, the second switch circuit is driven by the second driving signal Vdrive _ n, and the first driving signal Vdrive _ p and the second driving signal Vdrive _ n may be level signals.
The current limiting circuit includes: a first current limiting sub-circuit 300 and a second current limiting sub-circuit 400, the first current limiting sub-circuit 300 being connected to the first switching circuit 100, the second current limiting sub-circuit 400 being connected to the second switching circuit 200, the first current limiting sub-circuit 300 being configured to clamp the source current IOUT1 below a first target value; the second current limiting sub-circuit 400 is used to clamp the sinking current IOUT2 below a second target value.
It should be understood that the first current-limiting current may be composed of a sampling resistor and a switching tube; the second current limiting sub-circuit 400 may be composed of a sampling resistor and a switching tube. The first target value is the maximum current value of the source current IOUT1 of the bidirectional load, the second target value is the maximum current value of the sink current IOUT2 of the bidirectional load, and the first target value and the second target value can be the same value.
In the current limiting circuit applied to the bidirectional load in the embodiment, by adding the first current limiting sub-circuit 300 and the second current limiting sub-circuit 400, the purpose of clamping the source current IOUT1 below a first target value and clamping the sink current IOUT2 below a second target value is achieved, so that the clamping effect on the source current IOUT1 and the sink current IOUT2 of the bidirectional load is achieved, the phenomenon that the bidirectional load is damaged due to the fact that the current value of the source current IOUT1 or the sink current IOUT2 of the bidirectional load is too large is avoided, only the first current limiting sub-circuit 300 and the second current limiting sub-circuit 400 are added, large-size devices such as a comparator and an output voltage logic processing circuit do not need to be added, the circuit is simple and suitable for the bidirectional load, and the problems that a circuit structure is complex and the traditional current limiting circuit is not suitable for the bidirectional load are solved.
Referring to fig. 2, in one embodiment, the first current limiting sub-circuit 300 includes: the first detection circuit 310 is connected with the input end of the first switch circuit 100 and the power supply VIN, the pull-up circuit 320 is connected with the power supply VIN and the first switch circuit 100, and the first detection circuit 310 is used for detecting a pull current IOUT1 and outputting a first detection electrical signal; the pull-up circuit 320 is configured to turn on under control of the first detection electrical signal and to control the degree of turn-on of the first switch circuit 100 to clamp the pull-current IOUT1 below a first target value. Alternatively, the first detection electrical signal may be a voltage signal, a current signal, or the like.
It should be understood that the first detection circuit 310 in this embodiment may be formed by a sampling resistor, and the pull-up circuit 320 may be formed by a switch tube. The first current limiting sub-circuit 300 in this embodiment realizes the limitation of the output current of the bidirectional load by adding the first detection circuit 310 and the pull-up circuit 320, has a simple circuit structure, and solves the problem of complex circuit existing in the conventional technical problem.
Referring to fig. 3, in an embodiment, the first detection circuit 310 includes a first resistor R1, a first terminal of the first resistor R1 is a first terminal of the first detection circuit 310, the first terminal of the first detection circuit 310 is connected to the power source VIN, a second terminal of the first resistor R1 is a second terminal of the first detection circuit 310, and the second terminal of the first detection circuit 310 is connected to the input terminal of the first switch circuit 100 and the control terminal of the pull-up circuit 320.
It should be understood that the first detection electrical signal output by the first resistor R1 in this embodiment is a voltage signal, i.e., a voltage drop signal of the first resistor R1.
It should be understood that if the pull-up current IOUT1 is small, the current flowing through the first resistor R1 is small, and the voltage of the first resistor R1 is reduced, so that the pull-up circuit 320 is turned off, the size of the pull-up current IOUT1 is not changed, and the pull-up circuit 320 does not operate, so that additional static power is not consumed; if the source current IOUT1 is large, the current flowing through the first resistor R1 is large, and the voltage drop of the first resistor R1 is high, so that the pull-up circuit 320 is turned on, and the first driving signal Vdrive _ p is pulled up, so that the first switch circuit 100 is clamped, and the source current IOUT1 is not greater than the first target value; the magnitude of the first target value may be set by setting the magnitude of the resistance value of the first resistor R1, that is, the first resistor R1 may select a resistor having a smaller resistance value if the first target value is larger, and a resistor having a larger resistance value if the first target value is smaller.
Referring to fig. 3, in an embodiment, the pull-up circuit 320 includes a first switch tube Q1, a high potential terminal of the first switch tube Q1 is an input terminal of the pull-up circuit 320, an input terminal of the pull-up circuit 320 is connected to the power source VIN, a control terminal of the first switch tube Q1 is a control terminal of the pull-up circuit 320, the control terminal of the pull-up circuit 320 is connected to the second terminal of the first detection circuit 310 and the input terminal of the first switch circuit 100, a low potential terminal of the first switch tube Q1 is an output terminal of the pull-up circuit 320, and an output terminal of the pull-up circuit 320 is connected to the control terminal of the first switch circuit 100.
It should be understood that the on degree of the first switch circuit 100 is controlled by controlling the conduction of the first switch tube Q1 in this embodiment.
It should be understood that the first switch Q1 in this embodiment may be a PNP transistor, the base of the PNP transistor is the control terminal of the first switch Q1, the emitter of the PNP transistor is the high potential terminal of the first switch Q1, and the collector of the PNP transistor is the low potential terminal of the first switch Q1.
Referring to fig. 3, in an embodiment, the first switch circuit 100 includes a PMOS transistor Q3, a source of the PMOS transistor Q3 is an input terminal of the first switch circuit 100, a gate of the PMOS transistor Q3 is a control terminal of the first switch circuit 100, and a drain of the PMOS transistor Q3 is an output terminal of the first switch circuit 100. It should be understood that when the first driving signal Vdrive _ p is active low, that is, when the first driving signal Vdrive _ p is active low, the PMOS transistor Q3 is turned on, and the bidirectional load outputs the pull-out current IOUT1 through the first switch circuit 100.
It should be understood that the on-state of the first switch circuit 100 in this embodiment can be represented by the conducting width of the PMOS transistor Q3, and the conducting width of the PMOS transistor Q3 is controlled by controlling the gate-source voltage of the PMOS transistor Q3, for example, by controlling the gate-source voltage of the PMOS transistor Q3 to become smaller, and further controlling the conducting width of the PMOS transistor Q3 to become narrower, so as to clamp the pull-up current IOUT1 flowing through the PMOS transistor Q3 within a first target value, which is the maximum current value that the PMOS transistor Q3 can flow through under the clamping action.
Referring to fig. 2, in one embodiment, the second current limiting sub-circuit 400 includes: the second detection circuit 410 and the pull-down circuit 420, the output ends of the second detection circuit 410 and the second switch circuit 200 are connected with the ground, and the pull-down circuit 420 is connected with the second detection circuit 410 and the second switch circuit 200; the second detection circuit 410 is used for detecting the magnitude of the sink current IOUT2 and outputting a second detection electric signal; the pull-down circuit 420 is used to turn on and control the on-degree of the second switch circuit 200 under the control of the second detection electrical signal to clamp the sink current IOUT2 below the second target value. Alternatively, the second detection electrical signal may be a voltage signal, a current signal, or the like.
It should be understood that the second detection circuit 410 in this embodiment may be formed by a sampling resistor, and the pull-down circuit 420 may be formed by a switch tube. The second current limiting sub-circuit 400 in this embodiment realizes the limitation of the output current of the bidirectional load by adding the second detection circuit 410 and the pull-down circuit 420, has a simple circuit structure, and solves the problem of complex circuit existing in the conventional technical problem.
Referring to fig. 3, in one embodiment, the second detection circuit 410 includes: a second resistor R2, wherein a first terminal of the second resistor R2 is a first terminal of the second detection circuit 410, the first terminal of the second detection circuit 410 is connected to the output terminal of the second switch circuit 200 and the control terminal of the pull-down circuit 420, a second terminal of the second resistor R2 is a second terminal of the second detection circuit 410, and the second terminal of the second detection circuit 410 is connected to ground.
It should be understood that the second detection electrical signal output by the second resistor R2 in this embodiment is a voltage signal, i.e., a voltage drop signal of the second resistor R2.
It should be understood that if the sinking current IOUT2 is small, the current flowing through the second resistor R2 is small, and the voltage drop across the second resistor R2 is low, so that the pull-down circuit 420 is turned off, the size of the sinking current IOUT2 is not changed, and the pull-down circuit 420 does not operate, so that no additional static power is consumed; if the sinking current IOUT2 is large, the current flowing through the second resistor R2 is large, and the voltage drop of the second resistor R2 is high, so that the pull-down circuit 420 is turned on, and the second driving signal Vdrive _ n is pulled down, so as to clamp the second switch circuit 200, and the sinking current IOUT2 is not greater than the second target value; the magnitude of the second target value may be set by setting the magnitude of the resistance value of the second resistor R2, that is, the second resistor R2 may select a resistor having a smaller resistance value if the second target value is larger, and a resistor having a larger resistance value if the second target value is smaller.
Referring to fig. 3, in an embodiment, the pull-down circuit 420 includes a second switch Q2, the high potential terminal of the second switch Q2 is the input terminal of the pull-down circuit 420, the input terminal of the pull-down circuit 420 is connected to the control terminal of the second switch circuit 200, the control terminal of the second switch Q2 is the control terminal of the pull-down circuit 420, the control terminal of the pull-down circuit 420 is connected to the first terminal of the second detection circuit 410 and the output terminal of the second switch circuit 200, the low potential terminal of the second switch Q2 is the output terminal of the pull-down circuit 420, and the output terminal of the pull-down circuit 420 is connected to ground. It should be understood that in the present embodiment, the conduction of the second switch tube Q2 is controlled to control the on degree of the second switch circuit 200.
It should be understood that the second switch Q2 in this embodiment may be an NPN transistor, the base of the NPN transistor is the control terminal of the second switch Q2, the collector of the NPN transistor is the high potential terminal of the second switch Q2, and the emitter of the PNP transistor is the low potential terminal of the second switch Q2.
Referring to fig. 3, in one embodiment, the second switch circuit 200 includes an NMOS transistor Q4, a drain of the NMOS transistor Q4 is an input terminal of the second switch circuit 200, a gate of the NMOS transistor Q4 is a control terminal of the second switch circuit 200, and a source of the NMOS transistor Q4 is an output terminal of the second switch circuit 200. It should be understood that when the second driving signal Vdrive _ n is active high, i.e. when the second driving signal Vdrive _ n is active high, the NMOS transistor Q4 is turned on, and the bidirectional load outputs the sinking current IOUT2 through the second switch circuit 200.
It should be understood that the on-state of the second switch circuit 200 in this embodiment may be represented by the conducting channel width of the NMOS transistor Q4, and the conducting channel width of the NMOS transistor Q4 is controlled by controlling the gate-source voltage of the NMOS transistor Q4, for example, by controlling the gate-source voltage of the NMOS transistor Q4 to be smaller, so as to control the conducting channel width of the NMOS transistor Q4 to be narrower, and further clamp the sink current IOUT2 flowing through the NMOS transistor Q4 within a second target value, where the second target value is the maximum current value that the NMOS transistor Q4 can flow through under the clamping action.
With reference to fig. 3, a first operation process of the current limiting circuit is briefly described as follows:
1. when the output current of the bidirectional load is the pull-up current IOUT1, that is, when the output terminal of the bidirectional load pulls up the current IOUT 1:
1) if the source current IOUT1 is small, the current flowing through the first resistor R1 is also small, the voltage drop across the first resistor R1 is also low, the voltage at the point a is high, the bias voltage VBE of the base and emitter terminals of the first switch tube Q1 is small, the first switch tube Q1 is not conductive, and the signal of the first drive signal Vdrive _ p is not affected;
2) if the source current IOUT1 increases, the current flowing through the first resistor R1 also increases, the voltage drop across the first resistor R1 increases, the voltage at the point a decreases, the bias voltage VBE at the base and emitter terminals of the first switch Q1 increases, and when the VBE of the first switch Q1 is greater than the turn-on voltage of the first switch Q1, the first switch Q1 is turned on, the first drive signal Vdrive _ p is pulled high, the gate-source voltage VGS of the PMOS Q3 is decreased, so as to limit the source current IOUT1 to a first target value, it should be understood that the PMOS Q3 is still in the on state but the conducting channel of the PMOS Q3 is narrowed, and the first target value is the maximum current that the PMOS Q3 can flow under the clamping action, and even if the power VIN continues to increase, the current output by the PMOS Q3 does not exceed the first target value, that is the source current IOUT1 is clamped below the first target value, so as to achieve the current limiting protection.
2. Similarly, when the output current of the bidirectional load is the sinking current IOUT2, that is, when the output terminal of the bidirectional load sinks the current IOUT2 inward:
1) if the sinking current IOUT2 is small, the current flowing through the second resistor R2 is also small, the voltage drop across the second resistor R2 is also low, the voltage at the point B is low, the bias voltage VBE of the base and emitter terminals of the second switching tube Q2 is small, the second switching tube Q2 is not turned on, and the signal of the second driving signal Vdrive _ n is not affected;
2) if the sinking current IOUT2 increases, the current flowing through the second resistor R2 also increases, the voltage drop across the second resistor R2 increases, the voltage at the point B increases, the bias voltage VBE at the base and emitter terminals of the second switch Q2 increases, when the bias voltage VBE at the base and emitter terminals of the second switch Q2 is greater than the turn-on voltage of the second switch Q2, the second switch Q2 turns on, the second drive signal Vdrive _ n is pulled down, the gate-source voltage VGS of the NMOS Q4 is reduced, so as to limit the sinking current IOUT2 to a second target value, it should be understood that, at this time, the NMOS Q4 continues to be in a conducting state but the conducting channel of the NMOS Q4 becomes narrow, the second target value is the maximum current that the NMOS Q4 can flow under the clamping action, even if the current input to the input end of the bidirectional load continues to increase, the current output by the NMOS Q4 does not exceed the second target value, that is the sinking current IOUT2 or less, thereby realizing current-limiting protection.
It should be understood that, in the above operation process, the current limiting circuit of this embodiment changes the gate voltage values of the PMOS transistor Q3 and the NMOS transistor Q4 by applying the voltage generated by the output current of the bidirectional load through the sampling resistor between the base and the emitter of the transistor (Q1 and Q2) and controlling whether the transistor (Q1 and Q2) is turned on or not, instead of the conventional voltage comparator, without mirroring the output current, the circuit is simple; and in normal operation, the first switch tube Q1 and the second switch tube Q2 are in an off state, so that the static current of the chip is not increased. That is, the current limiting circuit in this embodiment has a simple circuit and a small occupied area, and does not increase the static power consumption of the chip, thereby solving the problems of a complex circuit, a large occupied area, and a large power consumption in the conventional scheme.
A second aspect of an embodiment of the present application provides a bidirectional load regulator, including: a current limiting circuit as in the first aspect of an embodiment of the present application.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A current limiting circuit for application to a bi-directional load, the bi-directional load including an output terminal, a first switching circuit for sourcing the output terminal, and a second switching circuit for sinking the output terminal, the current limiting circuit comprising:
a first current limiting sub-circuit connected to the first switching circuit, the first current limiting sub-circuit to clamp the source current below a first target value; and
a second current limiting sub-circuit connected to the second switching circuit, the second current limiting sub-circuit configured to clamp the sink current below a second target value.
2. The current-limiting circuit of claim 1, wherein the first current-limiting sub-circuit comprises:
the first detection circuit is connected with the input end of the first switch circuit and a power supply, and is used for detecting the source current and outputting a first detection electric signal; and
a pull-up circuit connected to the power supply and the first switch circuit, the pull-up circuit being configured to turn on and control an on-degree of the first switch circuit under control of the first detection electrical signal to clamp the pull current below the first target value.
3. The current-limiting circuit of claim 2, wherein the first detection circuit comprises a first resistor, a first terminal of the first resistor is a first terminal of the first detection circuit, the first terminal of the first detection circuit is connected to the power supply, a second terminal of the first resistor is a second terminal of the first detection circuit, and the second terminal of the first detection circuit is connected to the input terminal of the first switch circuit and the control terminal of the pull-up circuit.
4. The current-limiting circuit of claim 2, wherein the pull-up circuit comprises a first switch tube, the high potential terminal of the first switch tube is an input terminal of the pull-up circuit, the input terminal of the pull-up circuit is connected to the power supply, the control terminal of the first switch tube is a control terminal of the pull-up circuit, the control terminal of the pull-up circuit is connected to the second terminal of the first detection circuit and the input terminal of the first switch circuit, the low potential terminal of the first switch tube is an output terminal of the pull-up circuit, and the output terminal of the pull-up circuit is connected to the control terminal of the first switch circuit.
5. The current-limiting circuit of claim 1, wherein the second current-limiting sub-circuit comprises:
the second detection circuit is connected with the output end of the second switch circuit and the ground, and is used for detecting the size of the current and outputting a second detection electric signal; and
and the pull-down circuit is connected with the second detection circuit and the second switch circuit, and is used for conducting under the control of a second detection electric signal and controlling the conducting degree of the second switch circuit so as to clamp the sink current below the second target value.
6. The current limiting circuit of claim 5, wherein the second detection circuit comprises: the first end of the second resistor is the first end of the second detection circuit, the first end of the second detection circuit is connected with the output end of the second switch circuit and the control end of the pull-down circuit, the second end of the second resistor is the second end of the second detection circuit, and the second end of the second detection circuit is connected with the ground.
7. The current-limiting circuit of claim 5, wherein the pull-down circuit comprises a second switch tube, the high potential terminal of the second switch tube is an input terminal of the pull-down circuit, the input terminal of the pull-down circuit is connected to a control terminal of the second switch circuit, the control terminal of the second switch tube is a control terminal of the pull-down circuit, the control terminal of the pull-down circuit is connected to the first terminal of the second detection circuit and the output terminal of the second switch circuit, the low potential terminal of the second switch tube is an output terminal of the pull-down circuit, and the output terminal of the pull-down circuit is connected to the ground.
8. The current-limiting circuit of any one of claims 1 to 7, wherein the first switch circuit comprises a PMOS transistor, a source of the PMOS transistor is an input terminal of the first switch circuit, a gate of the PMOS transistor is a control terminal of the first switch circuit, and a drain of the PMOS transistor is an output terminal of the first switch circuit.
9. The current-limiting circuit of any one of claims 1 to 7, wherein the second switch circuit comprises an NMOS transistor, a drain of the NMOS transistor is an input terminal of the second switch circuit, a gate of the NMOS transistor is a control terminal of the second switch circuit, and a source of the NMOS transistor is an output terminal of the second switch circuit.
10. A bi-directional load regulator, comprising: the current limiting circuit of any of claims 1-9.
Priority Applications (1)
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| CN202020973681.0U CN212323987U (en) | 2020-06-01 | 2020-06-01 | Current-limiting circuit applied to bidirectional load and bidirectional load voltage stabilizer |
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| CN202020973681.0U CN212323987U (en) | 2020-06-01 | 2020-06-01 | Current-limiting circuit applied to bidirectional load and bidirectional load voltage stabilizer |
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