CN212322111U

CN212322111U - Digital signal conditioning device

Info

Publication number: CN212322111U
Application number: CN202021599330.4U
Authority: CN
Inventors: 冯英本; 庞长巍; 屠星星
Original assignee: Shanghai Yisu Information Technology Co ltd
Current assignee: Shanghai Yisu Information Technology Co ltd
Priority date: 2020-08-05
Filing date: 2020-08-05
Publication date: 2021-01-08
Anticipated expiration: 2030-08-05

Abstract

The utility model discloses a digital signal conditioning device, including connecting real-time system and the test mainboard by the measurement and control system, install real-time system butt joint circuit, control circuit, microcontroller, interface circuit, a plurality of sampling circuit and a plurality of drive circuit, every on the test mainboard respectively real-time system butt joint circuit and interface circuit are connected respectively to the sampling circuit, every drive circuit electric connection control circuit and interface circuit respectively, real-time system butt joint circuit, microcontroller and interface circuit are connected respectively to control circuit. The utility model discloses a control circuit receives the control command that microcontroller sent and control real-time system butt joint circuit, drive circuit and interface circuit and realize mode conversion, drive circuit output mode conversion and interface circuit's input/output mode respectively to the circuit form of correspondence difference improves the flexibility of system.

Description

Digital signal conditioning device

Technical Field

The utility model relates to a digital signal observes and controls the field, especially relates to a digital signal conditioning device.

Background

The typical controller comprises a computing core CPU, a digital interface, an analog interface, a driving interface, a bus interface and the like for transmitting information with the outside, wherein the digital interface can be subdivided into an input channel and an output channel, the output channel is divided into a pull-up channel, a pull-down channel, a push-pull output channel and the like, and for different circuit forms, the general controller can fix each channel into a specific circuit form to be butted with the outside environment according to design requirements.

Because the external digital sensors or devices to be butted by the controller have different interface forms, the digital interfaces of the controller correspond to the external digital sensors or devices, different voltage ranges and circuit forms need to be designed, the flexibility of the system is reduced, meanwhile, the test system of the controller also has the corresponding interface circuit form, in order to be compatible with the tests of different controllers, the test system also needs to have more digital channels with different interface forms, the flexibility of the system is seriously reduced, and the system is huge and the cost is increased.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the problem that different circuit forms exist in the prior art and need design specific circuit and external environment butt joint, reducing the shortcoming of system flexibility, and the digital signal conditioning device who provides.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model provides a digital signal conditioning device, is including connecting real-time system and the test mainboard of being observed and controlled the controller, install real-time system butt joint circuit, control circuit, microcontroller, interface circuit, a plurality of sampling circuit and a plurality of drive circuit, every on the test mainboard respectively real-time system butt joint circuit and interface circuit, every are connected respectively to the sampling circuit drive circuit electric connection control circuit and interface circuit respectively, real-time system butt joint circuit, microcontroller and interface circuit are connected respectively to control circuit, real-time system butt joint circuit connects real-time system, interface circuit connects and is observed and controlled the controller.

Preferably, the driving circuit includes a pre-driver chip U1, a capacitor C1 is connected in parallel to a VDD port and a VSS port of the pre-driver chip U1, a capacitor C2 is connected in parallel to a HB port and an HS port of the pre-driver chip U1, a resistor R1 and a MOS transistor Q1 are connected in series in sequence to a HO port of the pre-driver chip U1, a diode D1 is connected in parallel to the resistor R1, a diode D3 is connected in parallel to an S pole and a D pole of the MOS transistor Q1, a resistor R2 and a MOS transistor Q2 are connected in series in sequence to an LO port of the pre-driver chip U1, a diode D2 is connected in parallel to the resistor R2, a diode D4 is connected in parallel to an S pole and a D pole of the MOS transistor Q2, and a diode D5 is connected in common to the MOS transistor Q1 and the D pole of the MOS transistor Q2.

Preferably, the sampling circuit comprises a comparator U2, a resistor R3, a resistor R4 and a capacitor C3 are respectively connected to an IN + port of the comparator U2, one ends, far away from the resistor R3, of the resistor R4 and one end, far away from the resistor R3, of the capacitor C3 are commonly connected to a GND port of the comparator U2, and a resistor R5 is connected to an OUT port of the comparator U2.

Preferably, the interface circuit includes a bidirectional controllable switch S, a terminal C of the bidirectional controllable switch S is sequentially connected in series with a resistor R6 and a capacitor C4, a terminal a of the bidirectional controllable switch S is connected with a current-limiting fuse F, a terminal Vout is led out from the current-limiting fuse F, a terminal Vin is led out from a terminal b of the bidirectional controllable switch S, a terminal S _ ecu is led out from a terminal C of the resistor R6 close to the bidirectional controllable switch S, and the capacitor C4 is grounded.

Preferably, a Vcc end is led out from a VDD port of the pre-driver chip U1, an H _ Ctrl end is led out from a HI port of the pre-driver chip U1, an L _ Ctrl end is led out from an LI port of the pre-driver chip U1, a Vhb end is led out from an HS port of the capacitor C2, which is far away from the pre-driver chip U1, a Vbus end is led out from an S-pole of the MOS transistor Q1, an S-pole of the MOS transistor Q2 is grounded, and a V _ out end is led out from a D-pole of the MOS transistor Q2.

Preferably, a V _ IN terminal is led OUT from one end of the resistor R3 far away from the IN + port of the comparator U2, a Vref terminal is led OUT from the IN-port of the comparator U2, an S _ DI terminal is led OUT from one end of the resistor R5 far away from the OUT port of the comparator U2, the GND port of the comparator U2 is grounded, and a Vdc terminal is led OUT from the power supply terminal of the comparator U2.

The utility model discloses following beneficial effect has:

1. the control circuit and the microcontroller control the real-time system docking circuit, the driving circuit and the interface circuit, so that the test mainboard can change the test mode of the test mainboard according to the test instruction of the upper computer, and the flexibility of the system is improved.

2. The real-time system butt-joint circuit receives digital signals sent by the real-time system, transmits the digital signals to the control circuit after isolation processing and transmits the digital signals obtained by the sampling circuit to the real-time system after processing, so that the applicability of system testing is improved.

3. The drive circuit provides pull-up output, pull-down output and push-pull output mode switching through a MOS tube Q1 and a MOS tube Q2, and the applicability of system testing is further increased.

To sum up, the utility model discloses a control circuit receives the control command that microcontroller sent and control real-time system butt joint circuit, drive circuit and interface circuit and realize mode conversion, drive circuit output mode conversion and interface circuit's input/output mode respectively to the circuit form of correspondence difference improves the flexibility of system.

Drawings

Fig. 1 is a system block diagram of a digital signal conditioning device according to the present invention;

fig. 2 is a schematic diagram of a driving circuit of a digital signal conditioning device according to the present invention;

fig. 3 is a schematic diagram of a sampling circuit of the digital signal conditioning device according to the present invention;

fig. 4 is a schematic diagram of an interface circuit of the digital signal conditioning device according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.

Referring to fig. 1-4, a digital signal conditioning device comprises a test mainboard connected with a real-time system and a measured controller, wherein the test mainboard is respectively provided with a real-time system butt circuit, a control circuit, a microcontroller, an interface circuit, a plurality of sampling circuits and a plurality of driving circuits, each sampling circuit is respectively connected with the real-time system butt circuit and the interface circuit, each driving circuit is respectively and electrically connected with the control circuit and the interface circuit, the control circuit is respectively connected with the real-time system butt circuit, the microcontroller and the interface circuit, the real-time system butt circuit is connected with the real-time system, and the interface circuit is connected with the measured controller.

The driving circuit comprises a pre-driving chip U1, a capacitor C1 is connected in parallel with a VDD port and a VSS port of the pre-driving chip U1, a capacitor C2 is connected in parallel with a HB port and a HS port of the pre-driving chip U1, a resistor R1 and a MOS tube Q1 are sequentially connected in series with an HO port of the pre-driving chip U1, a diode D1 is connected in parallel with a resistor R1, a diode D3 is connected in parallel with an S pole and a D pole of the MOS tube Q1, a resistor R2 and an MOS tube Q2 are sequentially connected in series with an LO port of the pre-driving chip U1, a diode D2 is connected in parallel with a resistor R2, a diode D4 is connected in parallel with an S pole and a D pole of the MOS tube Q2, and a diode D5 is connected together with a D pole of the MOS tube Q.

The sampling circuit comprises a comparator U2, a resistor R3, a resistor R4 and a capacitor C3 are connected to an IN + port of the comparator U2 respectively, one ends, far away from the resistor R3, of the resistor R4 and one end, far away from the resistor R3, of the capacitor C3 are connected to a GND port of the comparator U2 IN a common mode, and a resistor R5 is connected to an OUT port of the comparator U2.

The interface circuit comprises a bidirectional controllable switch S, wherein a resistor R6 and a capacitor C4 are sequentially connected in series at the end C of the bidirectional controllable switch S, a current-limiting fuse F is connected at the end a of the bidirectional controllable switch S, a Vout end is led out of the current-limiting fuse F, a Vin end is led out of the end b of the bidirectional controllable switch S, an S _ ecu end is led out of the end C of the resistor R6 close to the bidirectional controllable switch S, and the capacitor C4 is grounded;

the interface circuit realizes the connection of the measured controller, the sampling circuit and the driving circuit, and the working mode of the interface circuit is controlled by the control circuit and mainly comprises two working modes: the input mode is used for connecting the tested controller and the input end V _ in of the sampling circuit; and the output mode is used for connecting the tested controller and the output V _ out of the driving circuit.

A Vcc end is led out from a VDD port of the pre-drive chip U1, an H _ Ctrl end is led out from an HI port of the pre-drive chip U1, an L _ Ctrl end is led out from an LI port of the pre-drive chip U1, a Vhb end is led out from an HS port of the capacitor C2 far away from the pre-drive chip U1, a Vbus end is led out from an S pole of the MOS tube Q1, an S pole of the MOS tube Q2 is grounded, and a V _ out end is led out from a D pole of the MOS tube Q2;

by controlling the constant turn-off of the upper bridge arm MOS tube Q1, only the lower bridge arm MOS tube Q2 acts, and the pull-down output is performed; by controlling the lower bridge arm MOS tube Q2 to be closed, only the upper bridge arm MOS tube Q1 acts, and pull-up output is performed; the push-pull output is realized by the action of the MOS transistor Q1 of the upper and lower bridge arms and the action of the MOS transistor Q2.

A V _ IN end is led OUT from one end, away from an IN + port, of the resistor R3, a Vref end is led OUT from an IN-port of the comparator U2, an S _ DI end is led OUT from one end, away from an OUT port, of the resistor R5, of the comparator U2, a GND port of the comparator U2 is grounded, and Vdc is led OUT from a power supply end of the comparator U2.

The utility model discloses when using, microcontroller receives the instruction that upstream control system sent through the CAN bus, translates it into rear end control circuit's instruction, gives control circuit for, and control circuit further resolves it into real-time system butt joint circuit, drive circuit and interface circuit's control instruction according to this instruction, and control circuit receives the real-time system digital signal that real-time system butt joint circuit forwarded, translates it into drive circuit's control instruction.

The HI port and the LI port of the driving circuit receive control instructions sent by the control circuit and input from the H _ Ctrl end and the L _ Ctrl end, the control instructions are amplified by the pre-driving chip into control signals of a subsequent MOS tube Q1 and an MOS tube Q2, the MOS tube Q1 and the MOS tube Q2 are driven to act, the output is converted into digital signals and output from the V _ out end, the upper bridge arm MOS tube Q1 is controlled to be constantly turned off, and only the lower bridge arm MOS tube Q2 acts, so that the pull-down output is realized; by controlling the lower bridge arm MOS tube Q2 to be closed, only the upper bridge arm MOS tube Q1 acts, and pull-up output is performed; the push-pull output is realized by the action of the MOS transistor Q1 of the upper and lower bridge arms and the action of the MOS transistor Q2.

The digital signal output by the measured controller is input through an S _ ecu end, is processed by an interface circuit and then reaches a sampling circuit from a Vin end, the sampling circuit inputs the digital signal to a V _ in end and compares the digital signal with the reference voltage of a Vref end, if the digital signal is higher than the reference voltage of the Vref end, the output of the S _ DI end is 1, and the voltage is in a TTL specification; and if the reference voltage is lower than the Vref end, the output of the S _ DI end is 0, and the digital signal is transmitted to the real-time system from the S _ DI end through the real-time system butt joint circuit.

The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.

Claims

1. The utility model provides a digital signal conditioning device, is including connecting real-time system and the test mainboard of being observed and controlled the controller, a serial communication port, install real-time system butt joint circuit, control circuit, microcontroller, interface circuit, a plurality of sampling circuit and a plurality of drive circuit, every on the test mainboard respectively real-time system butt joint circuit and interface circuit are connected respectively to the sampling circuit, every drive circuit electric connection control circuit and interface circuit respectively, real-time system butt joint circuit, microcontroller and interface circuit are connected respectively to control circuit, real-time system butt joint circuit connects real-time system, interface circuit connects by the controller of being observed and controlled.

2. The digital signal conditioning device according to claim 1, wherein the driving circuit comprises a pre-driver chip U1, a capacitor C1 is connected in parallel to a VDD port and a VSS port of the pre-driver chip U1, a capacitor C2 is connected in parallel to a HB port and a HS port of the pre-driver chip U1, a resistor R1 and a MOS transistor Q1 are sequentially connected in series to a HO port of the pre-driver chip U1, a diode D1 is connected in parallel to the resistor R1, a diode D3 is connected in parallel to an S pole and a D pole of the MOS transistor Q1, a resistor R2 and a MOS transistor Q2 are sequentially connected in series to an LO port of the pre-driver chip U1, a diode D2 is connected in parallel to the resistor R2, a diode D4 is connected in parallel to an S pole and a D pole of the MOS transistor Q2, and a diode D5 is connected in common to a D pole of the MOS transistor Q1 and a D2.

3. The digital signal conditioning device according to claim 1, wherein the sampling circuit comprises a comparator U2, a resistor R3, a resistor R4 and a capacitor C3 are respectively connected to an IN + port of the comparator U2, ends of the resistor R4 and the capacitor C3 far away from the resistor R3 are commonly connected to a GND port of the comparator U2, and an OUT port of the comparator U2 is connected to the resistor R5.

4. The digital signal conditioning device according to claim 1, wherein the interface circuit comprises a bidirectional controllable switch S, a terminal C of the bidirectional controllable switch S is sequentially connected in series with a resistor R6 and a capacitor C4, a terminal a of the bidirectional controllable switch S is connected with a current-limiting fuse F, a terminal Vout is led out from the current-limiting fuse F, a terminal Vin is led out from a terminal b of the bidirectional controllable switch S, a terminal S _ ecu is led out from the resistor R6 near the terminal C of the bidirectional controllable switch S, and the capacitor C4 is grounded.

5. The digital signal conditioning device according to claim 2, wherein a Vcc terminal is led out from a VDD port of the pre-driver chip U1, an H _ Ctrl terminal is led out from a HI port of the pre-driver chip U1, an L _ Ctrl terminal is led out from an LI port of the pre-driver chip U1, a Vhb terminal is led out from an HS port of the capacitor C2 far from the pre-driver chip U1, a Vbus terminal is led out from an S-pole of the MOS transistor Q1, an S-pole of the MOS transistor Q2 is grounded, and a V _ out terminal is led out from a D-pole of the MOS transistor Q2.

6. The digital signal conditioning device according to claim 3, wherein a V _ IN terminal is led OUT from an end of the resistor R3 far from an IN + port of the comparator U2, a Vref terminal is led OUT from an IN-port of the comparator U2, an S _ DI terminal is led OUT from an end of the resistor R5 far from an OUT port of the comparator U2, a GND port of the comparator U2 is grounded, and a Vdc is led OUT from a power supply terminal of the comparator U2.