CN212302553U

CN212302553U - Radio frequency chip system for adjusting receiving sensitivity

Info

Publication number: CN212302553U
Application number: CN202020952352.8U
Authority: CN
Inventors: 石雄书
Original assignee: Shenzhen Fosin Micro Technology Co ltd
Current assignee: Shenzhen Fosin Micro Technology Co ltd
Priority date: 2020-05-29
Filing date: 2020-05-29
Publication date: 2021-01-05
Anticipated expiration: 2030-05-29

Abstract

The embodiment of the application discloses a radio frequency chip system for adjusting receiving sensitivity, which comprises: the device comprises a delay register combination used for storing the digital quantity of the received signal, an adder circuit combination used for carrying out accumulation operation on the digital quantity of the received signal and a digital decision device used for comparing and judging the RSSI value of the accumulated received signal with a preset decision threshold value; the delay register combination, the adder circuit combination and the digital decision device are connected. By adopting the radio frequency chip system for adjusting the receiving sensitivity, the same chip can be used for adjusting and receiving signals with different intensities in different scenes, the success rate of highway subsection charging is convenient to improve, and the economic loss caused by missing fee is reduced.

Description

Radio frequency chip system for adjusting receiving sensitivity

Technical Field

The embodiment of the application relates to the technical field of intelligent Internet of things communication, in particular to a radio frequency chip system for adjusting receiving sensitivity.

Background

With the rapid development of scientific technology, an automatic Electronic Toll Collection (ETC) system is gradually perfected and matured, and is more and more widely applied to the field of automobile traffic Toll Collection. The automatic electronic toll collection system for highway, bridge and tunnel adopts automatic vehicle identification technology to complete the radio data communication between vehicle and toll station, and makes automatic vehicle induction identification and relevant toll data exchange, and based on computer network to process toll data so as to implement automatic electronic toll collection system without stopping vehicle and setting toll window.

At present, in the field of electronic toll collection systems ETC, two application scenes are usually faced, one is the process that an automobile is at an entrance and an exit of a highway, and the other is the process that the automobile normally runs on the highway. Since the vehicle speeds in these two scenarios are usually different, for example, at the entrance, the vehicle speed is generally within 30Km/h, and most of the vehicle speeds are greater than 80Km/h during normal driving on the highway. In the two application scenes, the requirements for the chip receiving sensitivity are different generally, the receiving sensitivity is reduced frequently to prevent car following when the entrance and exit are realized, the sensitivity is not high enough often due to too fast speed on a highway, the transaction success rate is reduced, the adjustable sensitivity of the chip is only 5-7 dB generally in the prior art, and the requirement of 30dB is not met. In order to solve the above technical problem, at least two rf chips capable of receiving different signal strengths are required to work in the prior art, such as obu (on Board unit) and cpc (compound Pass card). However, the implementation process of this design is complicated, the use cost is increased, and the power consumption is increased. Therefore, how to realize the adjustment of the signal reception sensitivity based on a single chip becomes a major research point for those skilled in the art.

SUMMERY OF THE UTILITY MODEL

Therefore, the embodiment of the application provides a radio frequency chip system for adjusting receiving sensitivity, so as to solve the problem that the radio frequency chip in the prior art cannot adjust the signal receiving intensity, so that the success rate of charging at different road sections of an expressway is low.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

in a first aspect, an embodiment of the present application provides a radio frequency chip system for adjusting a receiving sensitivity, including: the device comprises a delay register combination used for storing the digital quantity of the received signal, an adder circuit combination used for carrying out accumulation operation on the digital quantity of the received signal and a digital decision device used for comparing and judging the RSSI value of the accumulated received signal with a preset decision threshold value; the delay register combination, the adder circuit combination and the digital decision device are connected.

Further, the delay register combination includes: the first delay register, the second delay register, the third delay register, the fourth delay register, the fifth delay register and the sixth delay register; the first delay register, the second delay register, the third delay register, the fourth delay register, the fifth delay register and the sixth delay register are connected in sequence.

Further, the adder circuit combination comprises: a first adder circuit, a second adder circuit, a third adder circuit, a fourth adder circuit, and a fifth adder circuit; the first adder circuit, the second adder circuit, the third adder circuit, the fourth adder circuit, and the fifth adder circuit are connected in sequence.

Further, the first delay register, the second delay register, the third delay register, the fourth delay register, the fifth delay register, and the sixth delay register are respectively connected to one of the input ends of the first adder circuit, the second adder circuit, the third adder circuit, the fourth adder circuit, and the fifth adder circuit through a second output end.

Further, the output end of the fifth adder circuit is connected with the input end of the digital decision device.

Further, the radio frequency chip system for adjusting the receiving sensitivity further comprises an analog-to-digital conversion circuit for converting the input signal into a digital quantity of the received signal.

By adopting the radio frequency chip system for adjusting the receiving sensitivity, signals with different strengths can be adjusted and received by using the same chip under different scenes, the success rate of highway subsection charging is convenient to improve, the economic loss caused by missing deduction fee is reduced, and the use experience of a user is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.

Fig. 1 is a schematic structural diagram of a radio frequency chip system for adjusting a receiving sensitivity according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a radio frequency chip system according to an embodiment of the present disclosure;

wherein 101 is a first delay register, 102 is a second delay register, 103 is a third delay register, 104 is a fourth delay register, 105 is a fifth delay register, 106 is a sixth delay register, 107 is a first adder circuit, 108 is a second adder circuit, 109 is a third adder circuit, 110 is a fourth adder circuit, 111 is a fifth adder circuit, and 112 is a digital decision device.

Detailed Description

The present disclosure is not intended to be limited to the particular embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The following describes an embodiment of a radio frequency chip system for adjusting receiving sensitivity based on the present application. As shown in fig. 1, a schematic structural diagram of a radio frequency chip system for adjusting a receiving sensitivity according to an embodiment of the present application includes the following steps: a delay register combination for storing the digital quantity of the received signal, an adder circuit combination for performing an accumulation operation on the digital quantity of the received signal, and a digital decision device 112 for comparing and judging the RSSI value (received signal strength value) of the accumulated received signal with a preset decision threshold value; the delay register combination, the adder circuit combination, and the digital decision device 112 are connected, and the decision threshold refers to a signal strength value allowed to be received, which can be adjusted and set as needed.

Wherein the delay register combination at least comprises: a first delay register 101, a second delay register 102, a third delay register 103, a fourth delay register 104, a fifth delay register 105, and a sixth delay register 106; the first delay register 101, the second delay register 102, the third delay register 103, the fourth delay register 104, the fifth delay register 105, and the sixth delay register 106 are connected in sequence. As shown in fig. 1, a first output end 1 of the first delay register 101 is connected to an input end of the second delay register 102, a first output end 1 of the second delay register 102 is connected to an input end of the third delay register 103, a first output end 1 of the third delay register 103 is connected to an input end of the fourth delay register 104, a first output end 1 of the fourth delay register 104 is connected to an input end of the fifth delay register 105, and a first output end 1 of the fifth delay register 105 is connected to an input end of the sixth delay register 106, which is not described in detail herein.

The adder circuit combination comprises at least: a first adder circuit 107, a second adder circuit 108, a third adder circuit 109, a fourth adder circuit 110, and a fifth adder circuit 111. The first adder circuit 107, the second adder circuit 108, the third adder circuit 109, the fourth adder circuit 110, and the fifth adder circuit 111 are connected in sequence, and a specific connection manner is shown in fig. 1, which is not described in detail herein. Further, the first delay register 101, the second delay register 102, the third delay register 103, the fourth delay register 104, the fifth delay register 105, and the sixth delay register 106 are respectively connected to one input terminal of the first adder circuit 107, the second adder circuit 108, the third adder circuit 109, the fourth adder circuit 110, and the fifth adder circuit 111 through a second output terminal 2. An output terminal of the fifth adder circuit 111 is connected to an input terminal of the digital decision device 112.

Fig. 2 is a schematic structural diagram of a radio frequency chip system according to an embodiment of the present disclosure. The radio frequency chip system for adjusting the receiving sensitivity further comprises an analog-to-digital conversion circuit ADC for converting an input signal into a digital quantity of a received signal, an SPI communication controller module for providing data communication with an external host, an RSSI receiving module for receiving a road side antenna transmission signal, a decoding module for decoding frame data of the received signal, a state controller module for judging whether the received signal is a valid received signal and controlling the running state of the radio frequency chip, a timer module for recording elapsed time information and a clock circuit module for generating a clock running signal. The decoding module, the RSSI receiving module, the state controller module, the SPI communication controller module, the timer module, and the clock circuit module are connected in the manner shown in fig. 2, and realize signal transmission. The SPI communication controller module is provided with an SPI interface used for carrying out data communication with an external host. The state controller module comprises a receiving unit and a transmitting unit, and is respectively used for receiving and transmitting transaction data of an ETC system roadside antenna, and processing and judging signals or the transaction data. Further, the radio frequency chip system for adjusting the receiving sensitivity further includes: the specific connection relationship between the programmable gain amplifier module disposed at the signal input end of the rf chip and the digital-to-analog converter module disposed at the signal output end of the rf chip can refer to fig. 2, and is not described in detail herein. Furthermore, the decoding module comprises a first decoding module and a second decoding module; the first decoding module is arranged at the signal input end of the radio frequency chip and is connected with the output end of the analog-to-digital converter module; the second decoding module is arranged at the output end of the radio frequency chip and connected with the input end of the digital-to-analog converter module.

Those skilled in the art will recognize that the functions described in this invention may be implemented in a combination of hardware in one or more of the examples described above. The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.

Claims

1. A radio frequency chip system for adjusting a reception sensitivity, comprising: the device comprises a delay register combination used for storing the digital quantity of the received signal, an adder circuit combination used for carrying out accumulation operation on the digital quantity of the received signal and a digital decision device used for comparing and judging the RSSI value of the accumulated received signal with a preset decision threshold value; the delay register combination, the adder circuit combination and the digital decision device are connected.

2. The rf chip system for adjusting a receiving sensitivity according to claim 1, wherein the delay register combination includes: the first delay register, the second delay register, the third delay register, the fourth delay register, the fifth delay register and the sixth delay register; the first delay register, the second delay register, the third delay register, the fourth delay register, the fifth delay register and the sixth delay register are connected in sequence.

3. The rf chip system for adjusting a receiving sensitivity according to claim 2, wherein the adder circuit comprises, in combination: a first adder circuit, a second adder circuit, a third adder circuit, a fourth adder circuit, and a fifth adder circuit; the first adder circuit, the second adder circuit, the third adder circuit, the fourth adder circuit, and the fifth adder circuit are connected in sequence.

4. The rf chip system for adjusting receiving sensitivity according to claim 3, wherein the first delay register, the second delay register, the third delay register, the fourth delay register, the fifth delay register and the sixth delay register are respectively connected to one of the inputs of the first adder circuit, the second adder circuit, the third adder circuit, the fourth adder circuit and the fifth adder circuit through a second output terminal.

5. The RF chip system for adjusting receiving sensitivity according to claim 4, wherein an output terminal of the fifth adder circuit is connected to an input terminal of the digital decision device.

6. The radio frequency chip system for adjusting reception sensitivity according to claim 1, further comprising an analog-to-digital conversion circuit for converting an input signal into a digital quantity of the reception signal.