CN212255696U - Digital module of microminiature SAR system - Google Patents

Abstract

The utility model relates to a digital module of microminiature SAR system. The system comprises an FPGA chip serving as a main chip, a dual-channel analog-to-digital conversion chip ADC used for sampling an external radio frequency echo signal and a single-channel digital-to-analog conversion chip DAC used for playing a radio frequency signal, wherein the dual-channel analog-to-digital conversion chip ADC and the single-channel digital-to-analog conversion chip DAC are electrically connected with the FPGA chip; the system also comprises a first differential clock crystal oscillator OSC and a second differential clock crystal oscillator OSC, wherein the first differential clock crystal oscillator OSC is used as a reference clock of the SATA interface, and the second differential clock crystal oscillator OSC is used as a local clock of the system; the device also comprises a Flash memory chip for storing the FPGA program, a first DDR3 memory for real-time imaging processing, a second DDR3 memory for data caching and a pluggable memory module for storing data; the device also comprises an interface module; the power supply chip is used for supplying power to the chips. The digital module meets the requirements of miniaturization and light weight, and has high integration level and low power consumption.

Description

Digital module of microminiature SAR system

Technical Field

The utility model belongs to the technical field of microminiature synthetic aperture radar, a digital module of microminiature SAR system is related to.

Background

The micro SAR (micro synthetic aperture radar) system is different from the traditional pulse system Synthetic Aperture (SAR) system, and is a miniaturized SAR system realized on the FMCW-SAR system on the basis of the Frequency Modulation Continuous Wave (FMCW) technology. The FMCW-SAR realizes a microminiature SAR system with small volume, light weight and low power consumption by transmitting a linear frequency modulation continuous wave signal, sampling and storing a received echo signal after self-mixing and combining the frequency modulation continuous wave with a synthetic aperture imaging technology. The microminiature SAR system can be widely applied to small platforms such as unmanned aerial vehicles and the like, obtains high-resolution earth observation images, has the capability of all-weather observation in all-weather, realizes an unmanned aerial vehicle microwave remote sensing system, and has the characteristics of cost, flexibility in maneuvering, detection in high-risk areas and the like.

The microminiature SAR system is widely applied to various fields due to the characteristics of small volume, light weight, low power consumption, high integration degree and the like, and can realize reconnaissance and detection of special areas. With the development of modern information technology, various performance indexes of a microminiature SAR system are continuously improved, and a digital module is used as an important component of the system, and the development direction of the system is continuously improved towards microminiaturization, light weight, high integration and low power consumption.

At present, the imaging algorithm of the micro-miniature SAR system is researched more, but the research on the hardware building implementation mode of the digital module of the system is less, namely the current micro-miniature SAR system cannot meet the requirements of miniaturization, light weight, high integration and low power consumption, and still has a larger development space.

SUMMERY OF THE UTILITY MODEL

The utility model provides a miniaturized, lightweight, integrated level is high and the digital module of the microminiature SAR system that the consumption is low for solving the technical problem that exists among the well-known technique.

The utility model discloses a solve the technical scheme that technical problem that exists among the well-known technique took and be: a digital module of a microminiature SAR system comprises an FPGA chip as a main chip, a dual-channel analog-to-digital conversion chip ADC for sampling external radio frequency echo signals and a single-channel digital-to-analog conversion chip DAC for playing radio frequency signals, wherein the dual-channel analog-to-digital conversion chip ADC and the single-channel digital-to-analog conversion chip DAC are electrically connected with the FPGA chip; the system also comprises a first differential clock crystal oscillator OSC and a second differential clock crystal oscillator OSC, wherein the first differential clock crystal oscillator OSC is used as a reference clock of the SATA interface, and the second differential clock crystal oscillator OSC is used as a local clock of the system; the device also comprises a Flash memory chip for storing the FPGA program, a first DDR3 memory for real-time imaging processing, a second DDR3 memory for data caching and a pluggable memory module for storing data; the device also comprises an interface module; the power supply chip is used for supplying power to the chips.

The utility model has the advantages that: the utility model provides a rational in infrastructure design's microminiature SAR system's digital module has realized functions such as microminiature SAR system's high-speed data acquisition and broadcast, data storage and unloading, remote control, time service, timing pulse production and system monitoring. Compared with the digital module of the prior system, the utility model adopts a plurality of low-power chips to reduce the power consumption of the whole module; various high performance chips are employed to improve the performance of the overall module. The utility model discloses a digital module has improved the degree of integrating of module, and then reduces the volume and the weight of whole module, can satisfy current microminiature SAR system to digital module's miniaturization, lightweight requirement.

Preferably: the storage module comprises 2 pieces of electrically erasable and programmable read-only memory (EEPROM) connected with the FPGA chip through an I2C bus, 2 pieces of non-volatile existing memory (NOR FLASH) connected with the FPGA chip through an SPI bus and 1 piece of solid state disk (MSATA SSD) connected with the FPGA chip through a GTX bus.

Preferably: the interface module comprises TTL, LVTTL, RS232 and RS422 interfaces, each interface is connected to a J30J connector, and the J30J connector is connected with the FPGA chip through an SPI bus and a CAN bus.

Preferably: the J30J connector is connected to the XADC module of the FPGA chip through the voltage division chip.

Preferably: the USB interface is connected with the FPGA chip through a USB FX3 controller.

Drawings

Fig. 1 is a block diagram of the present invention.

Detailed Description

For further understanding of the contents, features and effects of the present invention, the following embodiments are described in detail.

Please refer to fig. 1, the digital module of the micro-miniature SAR system of the present invention includes the FPGA chip as the main chip, the dual-channel analog-to-digital conversion chip ADC for sampling the external rf echo signal and the single-channel digital-to-analog conversion chip DAC for playing the rf signal, and both the dual-channel analog-to-digital conversion chip ADC and the single-channel digital-to-analog conversion chip DAC are electrically connected to the FPGA chip.

The FPGA chip is responsible for realizing management of all control logics and processing flows, the double-channel analog-to-digital conversion chip ADC is responsible for sampling and receiving external radio-frequency echo analog signals, converting the analog signals into digital signals and then sending the digital signals to the FPGA chip for processing, and the single-channel digital-to-analog conversion chip DAC is used for converting radio-frequency signal digital quantity output by the FPGA chip into analog quantity and playing the analog quantity.

The system also comprises a first differential clock crystal oscillator OSC and a second differential clock crystal oscillator OSC, wherein the first differential clock crystal oscillator OSC is used as a reference clock of the SATA interface, and the second differential clock crystal oscillator OSC is used as a local clock of the system. The first differential clock oscillator OSC and the second differential clock oscillator OSC form two LVDS low-voltage differential signals. LVDS (Low-Voltage Differential Signaling) Low-Voltage Differential Signaling is a Differential Signaling technology with Low power consumption, Low error rate, Low crosstalk and Low radiation, the transmission technology can reach over 155Mbps, the core of the LVDS technology is to adopt high-speed Differential data transmission with extremely Low Voltage swing, and point-to-point or point-to-multipoint connection can be realized, and a transmission medium of the LVDS technology can be a copper PCB (printed Circuit Board) connecting wire or a balanced cable.

The device also comprises a Flash memory chip for storing the FPGA program, a first DDR3 memory for real-time imaging processing, a second DDR3 memory for data caching and a pluggable memory module for storing data.

The Flash storage chip is connected with the FPGA chip through the SPI bus, a program of the FPGA chip is stored on the Flash storage chip, and the FPGA program is automatically loaded when being electrified.

In this embodiment, the storage module includes 2 pieces of electrically erasable and programmable read only memory EEPROM connected to the FPGA chip through I2C bus, 2 pieces of non-volatile existing memory NOR FLASH connected to the FPGA chip through SPI bus, and 1 piece of solid state disk MSATA SSD connected to the FPGA chip through GTX bus, and the three kinds of memories are respectively used for storing echo data, auxiliary data, and data index information in real time.

The interface module comprises TTL, LVTTL, RS232 and RS422 interfaces, each interface is connected to a J30J connector, the J30J connector is connected with the FPGA chip through an SPI bus and a CAN bus, and each interface forms an interface with other external equipment.

The USB interface is connected with the FPGA chip through a USB FX3 controller. The ultra-high-speed USB3.0 interface chip is used for providing a USB interface with a computer to realize data playback and debugging control.

The power supply chip is used for supplying power to the chips.

The J30J connector is connected to the XADC module of the FPGA chip through the voltage division chip.

It can be seen from the hardware composition block diagram that the module adopts a programmable logic device as a core, externally expands A/D, D/A, a storage medium and various digital interfaces, and completes various acquisition, playing and control functions depending on the programmable characteristics of the FPGA.

In the aspect of the structure, the utility model discloses a digital module adopts single shell structure, mainly forms by cavity, storage module and PCB board assembly, and storage module adopts embedded mode to install. In order to facilitate the plugging and unplugging of the data module and protect the storage module, the storage module can be packaged in a small metal box and plugged as a whole when in use, and meanwhile, the plugging and unplugging assisting device is added, so that the plugging and unplugging can be easily completed.

The digital module has two working modes: the real-time collection play mode and the data playback mode, and the specific working flow thereof is as follows.

The working process of collecting the playing mode in real time is as follows:

1) after the digital module is powered on, system initialization is carried out, and all hardware interfaces are started;

2) according to the preset starting condition, the following steps are executed concurrently:

a) generating and playing a waveform;

b) receiving GPS time information and POS attitude information;

c) after the echo data are collected by the A/D, the echo data are recorded into a storage module in real time on one hand, and are transmitted outside through a data transmission interface on the other hand;

d) recording various auxiliary data such as temperature, voltage and the like in real time;

3) and stopping the flow according to a preset ending condition, and enabling the system to stand by.

The work flow of the data playback flow mode is as follows:

after the digital module finishes data acquisition on the machine, the storage module is pulled out and installed on a transfer device on the ground, and then the digital module is connected with a computer through a USB interface to read echo data and auxiliary data in the storage module for subsequent processing.

Claims (5)

1. A digital module of a microminiature SAR system is characterized in that: the system comprises an FPGA chip serving as a main chip, a dual-channel analog-to-digital conversion chip ADC used for sampling an external radio frequency echo signal and a single-channel digital-to-analog conversion chip DAC used for playing a radio frequency signal, wherein the dual-channel analog-to-digital conversion chip ADC and the single-channel digital-to-analog conversion chip DAC are electrically connected with the FPGA chip; the system also comprises a first differential clock crystal oscillator OSC and a second differential clock crystal oscillator OSC, wherein the first differential clock crystal oscillator OSC is used as a reference clock of the SATA interface, and the second differential clock crystal oscillator OSC is used as a local clock of the system; the device also comprises a Flash memory chip for storing the FPGA program, a first DDR3 memory for real-time imaging processing, a second DDR3 memory for data caching and a pluggable memory module for storing data information; the device also comprises an interface module; the power supply chip is used for supplying power to the chips.

2. The digital module of the micro-miniature SAR system of claim 1, wherein: the storage module comprises 2 pieces of electrically erasable and programmable read-only memory (EEPROM) connected with the FPGA chip through an I2C bus, 2 pieces of non-volatile existing memory (NOR FLASH) connected with the FPGA chip through an SPI bus and 1 piece of solid state disk (MSATA SSD) connected with the FPGA chip through a GTX bus.

3. The digital module of the micro-miniature SAR system of claim 2, wherein: the interface module comprises TTL, LVTTL, RS232 and RS422 interfaces, each interface is connected to a J30J connector, and the J30J connector is connected with the FPGA chip through an SPI bus and a CAN bus.

4. The digital module of the micro-miniature SAR system of claim 3, wherein: the J30J connector is connected to the XADC module of the FPGA chip through the voltage division chip.

5. The digital module of the micro-miniature SAR system of claim 4, wherein: the USB interface is connected with the FPGA chip through a USB FX3 controller.

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