CN212211229U - AVS 2-H.2654K ultra-high-definition dual-decoder - Google Patents
AVS 2-H.2654K ultra-high-definition dual-decoder Download PDFInfo
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- CN212211229U CN212211229U CN202021453562.9U CN202021453562U CN212211229U CN 212211229 U CN212211229 U CN 212211229U CN 202021453562 U CN202021453562 U CN 202021453562U CN 212211229 U CN212211229 U CN 212211229U
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Abstract
The utility model relates to a broadcasting digital television technical field, concretely relates to AVS2 to H.2654K super high definition double code converter, it is including setting up mainboard, front panel and the power strip in the casing, the mainboard includes master control CPU unit, AVS 24K decoding unit, H.265 coding unit, code stream processing unit, ASI IP input/output unit; the AVS 24K code stream signal is decoded into a baseband video and audio signal through a built-in AVS 24K decoding unit and a built-in H.265 encoding unit, then the video signal is re-encoded into H.2652160P50 and H.2652160P304K code streams, the audio signal is re-encoded into an MPEG1_ L2 code stream, simultaneously HDR information embedded in the AVS2 video code stream is extracted and re-embedded into the H.265 video code stream, and the video and audio code streams are output through an ASI/IP interface after being multiplexed, so that the AVS 24K code stream is simultaneously transcoded into the H.2652160P50 and 2160P 304K code streams for output, and the high integration and low cost of the product are realized.
Description
Technical Field
The utility model relates to a broadcast digital television technical field, concretely relates to clear double code converter of AVS2 to H.2654K superelevation.
Background
A central broadcast television head office broadcasts a first staring ultra-high definition television channel-CCTV 4K ultra-high definition channel in China in 2018, 10 and 1, a 16 Guangdong comprehensive 4K ultra-high definition channel in 2018, 10 and 16, and an implementation guide of an IPTV service system AVS2 (2018) is formally released.
In order to meet the requirement of national television stations, radio and television cable networks, IPTV and OTT front-end receiving and transferring AVS 24K ultra-high definition channels and facilitate users of H.2652160P50 and P304K stock set-top boxes to watch 4K channels, I independently develop AVS2 to H.2654K ultra-high definition double decoders.
Disclosure of Invention
An object of the utility model is to provide an AVS2 to H.2654K ultra-high definition dual code converter to prior art's defect and not enough.
The utility model discloses an AVS2 to H.2654K super high definition double code converter, it includes mainboard, front panel and the power strip that sets up in the casing, there is the power strip on the left side, the front panel of mainboard is provided with the front panel, this front panel and power strip pass through the wire and link to each other with the mainboard;
the main board comprises a main control CPU unit, an AVS 24K decoding unit, an H.265 encoding unit, a code stream processing unit and an ASI/IP input/output unit;
the main control CPU unit is electrically connected with the AVS 24K decoding unit, the H.265 encoding unit, the code stream processing unit, the ASI/IP input/output unit and the front panel; the AVS 24K decoding unit is respectively connected with the main control CPU unit, the H.265 coding unit and the code stream processing unit through data conductors; the H.265 coding unit is respectively connected with the main control CPU unit, the AVS 24K decoding unit and the code stream processing unit through data conductors; the code stream processing unit is respectively connected with the main control CPU unit, the AVS 24K decoding unit, the H.265 coding unit and the ASI/IP input and output unit through data conductors; and the ASI/IP input/output unit is respectively connected with the main control CPU unit and the code stream processing unit through data wires.
Furthermore, the AVS 24K decoding unit comprises an AVS2 code stream input processing unit, an AVS2 decoding unit and a baseband video and audio signal processing unit.
Further, the h.265 coding unit includes a coding parameter configuration processing unit, an h.2652160p50 video coding unit, an h.2652160p30 video coding unit, an audio coding unit, and a code stream multiplexing unit.
Furthermore, the code stream processing unit comprises a code stream switching processing unit, a PSI/SI parameter configuration processing unit and a code rate control processing unit.
Furthermore, the ASI/IP input/output unit includes a code stream ASI input/output processing unit and a code stream IP input/output processing unit.
After the structure is adopted, the utility model discloses beneficial effect does: an AVS2 to H.2654K superelevation clear double code converter, it is through built-in AVS 24K decoding unit and H.265 coding unit, decode AVS 24K code stream signal to baseband video audio signal, then recode video signal for H.2652160P50 and 2160P 304K code stream, audio signal recodes for MPEG1_ L2 code stream, and simultaneously, draw out the embedded HDR information of AVS2 video code stream, imbed again in the H.265 video code stream, export through ASI/IP interface after the video audio code stream is multiplexing, thereby realize transcoding H.2652160P50 and 2160P 304K code stream output simultaneously with AVS 24K code stream, through embedded IC integrated circuit, realize the high integration, low cost of product.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, do not constitute a limitation of the invention, and in which:
fig. 1 is a schematic structural diagram of the present invention;
fig. 2 is a functional schematic diagram of the present invention.
Description of reference numerals:
1. a housing; 2. a main board; 21. a main control CPU unit; 22. AVS 24K decoding unit; 221. AVS2 code stream input processing unit; 222. an AVS2 decoding unit; 223. a baseband video and audio signal processing unit; 23. h.265 coding unit; 231. a coding parameter configuration processing unit; 232. h.2652160p50 video coding unit; 233. h.2652160p30 video coding unit; 234. an audio encoding unit; 235. a code stream multiplexing unit; 24. a code stream processing unit; 241. a code stream switching processing unit; 242. PSI/SI parameter configuration processing unit; 243. a code rate control processing unit; 25. an ASI/IP input/output unit; 251. a code stream ASI input and output processing unit; 252. a code stream IP input/output processing unit; 3. a front panel; 4. a power panel.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1, the AVS 2-h.2654k ultra high definition dual transcoder according to this embodiment includes a main board 2, a front panel 3 and a power board 4, which are disposed in a housing 1, wherein the front panel 3 is disposed in front of the main board 2, the power board 4 is disposed on the left side of the main board 2, and the front panel 3 and the power board 4 are connected to the main board 2 through wires;
the mainboard 1 comprises a main control CPU unit 21, an AVS 24K decoding unit 22, an H.265 encoding unit 23, a code stream processing unit 24 and an ASI/IP input and output unit 25;
the main control CPU unit 21 is electrically connected with the AVS 24K decoding unit 22, the H.265 encoding unit 23, the code stream processing unit 24, the ASI/IP input/output unit 25 and the front panel 3; the AVS 24K decoding unit 22 is respectively connected with the main control CPU unit 21, the H.265 encoding unit 23 and the code stream processing unit 24 through data conductors; the H.265 encoding unit 23 is respectively connected with the main control CPU unit 21, the AVS 24K decoding unit 24 and the code stream processing unit 25 through data conductors; the code stream processing unit 24 is respectively connected with the main control CPU unit 21, the AVS 24K decoding unit 22, the H.265 encoding unit 23 and the ASI/IP input/output unit 25 through data conductors; the ASI/IP input/output unit 25 is connected to the main control CPU unit 21 and the code stream processing unit 24 through data wires, respectively.
Further, the AVS 24K decoding unit 22 includes an AVS2 code stream input processing unit 221, an AVS2 decoding unit 222, and a baseband video/audio signal processing unit 223.
Further, the h.265 encoding unit 23 includes an encoding parameter configuration processing unit 231, an h.2652160p50 video encoding unit 232, an h.2652160p30 video encoding unit 233, an audio encoding unit 234, and a code stream multiplexing unit 235.
Further, the code stream processing unit 24 includes a code stream switching processing unit 241, a PSI/SI parameter configuration processing unit 242, and a code rate control processing unit 243.
Further, the ASI/IP input/output unit 25 includes a code stream ASI input/output processing unit 251 and a code stream IP input/output processing unit 252.
Further, the main control CPU unit 21 and the AVS 24K decoding unit 22 use haisi Hi3796MV200 chips, the h.265 encoding unit 23 uses suxi SC2M50 chips, and the code stream processing unit 24 and the ASI/IP input/output processing unit 25 use FPGA chips.
Further, the chassis 1 adopts a chassis with 19 inches of width and 1U of height.
As shown in fig. 1, the design is composed of a main board, a front panel and a power board. The mainboard is connected with power panel, front panel respectively. The power panel converts 220V alternating current signals input from the urban network into +5V and +12V direct current voltages required by the system, and provides power for the whole transcoder; the front panel provides LCD liquid crystal display and key operation; the mainboard realizes decoding the AVS 24K code stream signal into baseband video and audio signals, then recoding the baseband video and audio signals into H.2652160P50 and H.2652160P304K code stream signals, outputting through an ASI/IP interface, and outputting HDR information in a transparent transmission mode.
As shown in fig. 2, the main board of the embodiment of the present invention includes a main control CPU unit, an AVS 24K decoding unit, an h.265 encoding unit, a code stream processing unit, and an ASI/IP input/output unit. Under the control of a main control CPU unit, AVS 24K code stream signals are subjected to format conversion through an ASI/IP input/output unit and then sent to a code stream processing unit, the AVS 24K decoding unit is subjected to time sequence adjustment and then sent to a baseband video/audio signal, HDR data information is extracted, then the baseband video/audio signal is sent to an H.265 encoding unit, the video signal is re-encoded into H.2652160P50 and H.2652160P304K code streams, the audio signal is re-encoded into MPEG1_ L2 code streams, the HDR data information is re-embedded into the H.265 video code streams, and the video/audio code streams are output through an ASI/IP interface after being multiplexed, so that the AVS 24K code streams are simultaneously transcoded into H.265216050 and 2160P 304K codes and output.
The utility model discloses in, the casing adopts the professional type casing design of 19 cun width, 1U height of standard, is applicable to 19 cun standard rack installation and uses. The height occupied by equipment installation in a 19 inch standard cabinet is represented by a special unit "U", 1U =44.45 mm.
The utility model discloses in, master control CPU and AVS2 decode and adopt haisi Hi3796MV200 chip, and H.265 looks audio coding adopts suo xi SC2M50 chip, and code stream processing and ASI IP input/output processing adopt the FPGA chip.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (5)
1. An AVS2 to H.2654K ultra-high-definition dual-decoder comprises a mainboard, a front panel and a power panel which are arranged in a casing, wherein the front of the mainboard is provided with the front panel, the left side of the mainboard is provided with the power panel, and the front panel and the power panel are connected with the mainboard through wires;
the method is characterized in that: the main board comprises a main control CPU unit, an AVS 24K decoding unit, an H.265 encoding unit, a code stream processing unit and an ASI/IP input/output unit;
the main control CPU unit is electrically connected with the AVS 24K decoding unit, the H.265 encoding unit, the code stream processing unit, the ASI/IP input/output unit and the front panel; the AVS 24K decoding unit is respectively connected with the main control CPU unit, the H.265 coding unit and the code stream processing unit through data conductors; the H.265 coding unit is respectively connected with the main control CPU unit, the AVS 24K decoding unit and the code stream processing unit through data conductors; the code stream processing unit is respectively connected with the main control CPU unit, the AVS 24K decoding unit, the H.265 coding unit and the ASI/IP input and output unit through data conductors; and the ASI/IP input/output unit is respectively connected with the main control CPU unit and the code stream processing unit through data wires.
2. An AVS 2-h.2654k ultra high definition dual decoder of claim 1, wherein: the AVS 24K decoding unit comprises an AVS2 code stream input processing unit, an AVS2 decoding unit and a baseband video and audio signal processing unit.
3. An AVS 2-h.2654k ultra high definition dual decoder of claim 1, wherein: the H.265 coding unit comprises a coding parameter configuration processing unit, an H.2652160P50 video coding unit, an H.2652160P30 video coding unit, an audio coding unit and a code stream multiplexing unit.
4. An AVS 2-h.2654k ultra high definition dual decoder of claim 1, wherein: the code stream processing unit comprises a code stream switching processing unit, a PSI/SI parameter configuration processing unit and a code rate control processing unit.
5. An AVS 2-h.2654k ultra high definition dual decoder of claim 1, wherein: the ASI/IP input/output unit comprises a code stream ASI input/output processing unit and a code stream IP input/output processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021453562.9U CN212211229U (en) | 2020-07-22 | 2020-07-22 | AVS 2-H.2654K ultra-high-definition dual-decoder |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021453562.9U CN212211229U (en) | 2020-07-22 | 2020-07-22 | AVS 2-H.2654K ultra-high-definition dual-decoder |
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| CN202021453562.9U Active CN212211229U (en) | 2020-07-22 | 2020-07-22 | AVS 2-H.2654K ultra-high-definition dual-decoder |
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Address after: Room b-0103, 2 / F, building 3, yard 30, Shixing street, Shijingshan District, Beijing 100041 Patentee after: Beijing Golden Age Media Technology Co.,Ltd. Address before: Room b-0103, 2 / F, building 3, yard 30, Shixing street, Shijingshan District, Beijing 100041 Patentee before: GOLDEN TIMES CULTURE COMMUNICATIONS Corp.,Ltd. |
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