CN212210949U

CN212210949U - Shared circuit and electronic device

Info

Publication number: CN212210949U
Application number: CN202021176018.4U
Authority: CN
Inventors: 郭富祥
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-06-22
Filing date: 2020-06-22
Publication date: 2020-12-22
Anticipated expiration: 2030-06-22

Abstract

The embodiment of the application discloses a shared circuit and electronic equipment, wherein the shared circuit comprises a crystal oscillator, a filter circuit, a first bias circuit and a second bias circuit, the crystal oscillator comprises an input end and an output end, the filter circuit is connected with the input end of the crystal oscillator and is used for filtering clutter signals in electric signals input to the crystal oscillator, the signal input end of the first bias circuit is connected with the output end of the crystal oscillator, and the signal output end of the first bias circuit is connected with a first chip and is used for improving the driving capability of the crystal oscillator to the first chip; and the signal input end of the second biasing circuit is connected with the output end of the crystal oscillator, and the signal output end of the second biasing circuit is connected with the second chip and used for improving the driving capability of the crystal oscillator to the second chip. The shared circuit can realize that one crystal oscillator drives a plurality of chips to work normally.

Description

Shared circuit and electronic device

Technical Field

The present application relates to the field of electronic circuit technology, and in particular, to a sharing circuit and an electronic device.

Background

When having a plurality of chips on present electronic equipment, often can set up crystal oscillator and keep the stability of circuit, but when having a plurality of chips on electronic equipment, often can adopt a plurality of crystal oscillators, every crystal oscillator drives a chip alone, to each chip and the crystal oscillator that this chip corresponds, all need design corresponding circuit to make the drive chip that the crystal oscillator can be normal. When the internal space of the electronic equipment is small, the area for arranging the circuit is limited, and the internal space of the electronic equipment does not meet the requirement of arranging a plurality of crystal oscillators.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a shared circuit and electronic equipment, wherein the shared circuit comprises a crystal oscillator and a plurality of chips, and the crystal oscillator can drive the chips to normally work in the shared circuit.

In a first aspect, the shared circuitry comprises:

the crystal oscillator comprises an input end and an output end;

the filter circuit is connected with the input end of the crystal oscillator and is used for filtering clutter signals in the electric signals input to the crystal oscillator;

a signal input end of the first bias circuit is connected with an output end of the crystal oscillator, and a signal output end of the first bias circuit is connected with the first chip and used for improving the driving capability of the crystal oscillator to the first chip;

and the signal input end of the second biasing circuit is connected with the output end of the crystal oscillator, and the signal output end of the second biasing circuit is connected with the second chip and used for improving the driving capability of the crystal oscillator to the second chip.

Specifically, the common circuit further includes a first adjusting module and a second adjusting module, the first adjusting module is connected in series between the output terminal of the crystal oscillator and the signal input terminal of the first bias circuit, the second adjusting module is connected in series between the output terminal of the crystal oscillator and the signal input terminal of the second bias circuit, the first adjusting module is configured to isolate signal interference of the first bias circuit to the second chip, and the second adjusting module is configured to isolate signal interference of the second bias circuit to the first chip.

Wherein, first regulating module still is used for keeping apart first bias circuit right crystal oscillator's signal interference and filtering the clutter signal of crystal oscillator output, second regulating module still is used for keeping apart second bias circuit right crystal oscillator's signal interference and filtering the clutter signal of crystal oscillator output.

In a second aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes the shared circuit provided in the embodiment of the present application.

The sharing circuit provided by the embodiment of the application can realize that one crystal oscillator drives a plurality of chips to normally work, can reduce the number of components in the circuit, and simultaneously reduces the occupied area of the circuit inside the electronic equipment.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a first circuit diagram of a shared circuit provided in an embodiment of the present application.

Fig. 2 is a second circuit diagram of a shared circuit provided in an embodiment of the present application.

Fig. 3 is a third circuit diagram of a shared circuit provided in an embodiment of the present application.

Fig. 4 is a fourth circuit diagram of a shared circuit provided in an embodiment of the present application.

Fig. 5 is a fifth circuit diagram of a shared circuit provided in an embodiment of the present application.

Fig. 6 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the related art, in some electronic devices, an ac signal with a highly stable frequency is required, and the LC oscillator has poor stability and easily drifts in frequency (i.e., the frequency of the generated ac signal easily changes). Thus, a highly stable signal can be generated by using a quartz crystal in a crystal oscillator, which is called a crystal oscillator.

Generally, a crystal oscillator drives a chip, and different chips require different clock circuits, so that with the adoption of the crystal oscillator, each chip needs to be adjusted by the corresponding crystal oscillator, and if the crystal oscillator is directly connected to different chips, signal crosstalk between different chips can be caused, so that the chips cannot normally work. Meanwhile, if each chip is provided with a corresponding crystal oscillator and a corresponding circuit, the circuit design needs to occupy a large space inside the electronic device, for example, the space in the smart watch is very narrow, and the weight and the circuit design cost of the electronic device can be increased if more circuit components are arranged.

In view of the above problems, the present application provides a common circuit, which includes a crystal oscillator and a plurality of chips, wherein the crystal oscillator can drive the plurality of chips to operate normally in the common circuit. For a detailed description of the circuit principle, please refer to the following.

Referring to fig. 1, fig. 1 is a first circuit diagram of a common circuit according to an embodiment of the present disclosure.

The common circuit includes a filter circuit 10, a crystal oscillator 20, a first bias circuit 30, a second bias circuit 40, a first chip 50, and a second chip 60. Wherein, the crystal oscillator 20 can simultaneously drive the first chip 50 and the second chip 60 to work normally.

The filter circuit 10 is arranged between the first power supply input X1 and the input 21 of the crystal oscillator 20, i.e. the filter circuit 10 is connected in series with the crystal oscillator 20 and the first power supply input X1. When the first power input terminal X1 inputs an electrical signal, the filter circuit 10 can process a noise signal in the input electrical signal, for example, when the first power input terminal X1 inputs an electrical signal, a noise signal that interferes with the normal operation of the crystal oscillator 20 may exist in the electrical signal, and the filter circuit 10 may filter out the noise signal in a certain frequency range, so that the electrical signal input to the crystal oscillator 20 does not include the noise signal.

In some embodiments, the filter circuit 10 includes a filter module 11 and a third capacitor C1, one end of the filter module 11 is connected to the first power input terminal X1, the other end of the filter module 11 is connected to the input terminal 21 of the crystal oscillator 20, the third capacitor C1 is connected in parallel between the input terminal 21 and the filter module, and the other end of the third capacitor C1 is connected to the first ground point G1. Both the filtering module 11 and the third capacitor C1 may function as a filter. The filter module 11 may be formed by a whole filter circuit, or may be formed by separately provided components.

The Crystal oscillator 20 may be a conventional Crystal oscillator (XO), a Temperature Compensated Crystal oscillator (TCXO), or a Voltage Controlled Temperature Compensated Crystal oscillator (VCTCXO). The crystal oscillator 20 is capable of generating clock signals and providing reference signals for the first chip 50 and the second chip 60 in a circuit.

The output 22 of the crystal oscillator 20 is connected to the signal input 31 of the first bias circuit 30, while the output 22 of the crystal oscillator 20 is connected to the input 41 of the second bias circuit 40, i.e. the first bias circuit 30 and the second bias circuit 40 are connected in parallel.

The crystal oscillator 20 further includes a first ground terminal 23 and a second ground terminal 24, the first ground terminal 23 being connected to a second ground point G2, and the second ground terminal 24 being connected to a third ground point G3.

The signal output end 32 of the first bias circuit 30 is connected to the first chip 50, the signal input by the crystal oscillator 20 is processed by the first bias circuit 30, the signal processed by the first bias circuit 30 is transmitted to the first chip 50 through the signal output end 32, and the first chip 50 can normally operate according to the signal processed by the first bias circuit 30, that is, the crystal oscillator 20 can drive the first chip 50 to normally operate.

The signal output end 42 of the second bias circuit 40 is connected to the second chip 60, the signal input by the crystal oscillator 20 is processed by the second bias circuit 40, the signal processed by the second bias circuit 40 is transmitted to the second chip 60 through the signal output end 42 thereof, and the second chip 60 can normally operate according to the signal processed by the second bias circuit 40, that is, the crystal oscillator 20 can drive the second bias circuit 40 to normally operate.

In some embodiments, the first bias circuit 30 includes a second power input terminal X2, a first resistor R1, and a second resistor R2, the first resistor R1 and the second resistor R2 are connected in parallel to the signal input terminal 31 of the first bias circuit 30, the other end of the first resistor R1 is connected to the second power input terminal X2, and the other end of the second resistor R2 is connected to the fourth ground point G4. The first resistor R1 and the second resistor R2 may cooperate to adjust the dc bias voltage of the first chip 50.

In some embodiments, the second bias circuit 40 includes a third power input terminal X3, a third resistor R3, and a fourth resistor R4, the third resistor R3 and the fourth resistor R4 are connected in parallel to the signal input terminal 41 of the second bias circuit 40, the other end of the third resistor R3 is connected to the third power input terminal X3, and the other end of the fourth resistor R4 is connected to the fifth ground point G5. The third resistor R3 and the fourth resistor R4 may cooperate to adjust the dc bias voltage of the second chip 60.

For example, if the voltage output by the crystal oscillator 20 is 0-1V and the high level required by the first chip 50 is 1.1V, the first chip 50 requires a dc bias voltage of 0.1V, and the first bias circuit 30 is used to generate a dc bias voltage of 0.1V, which is added to the voltage 1V output by the crystal oscillator 20, and the high level input to the first chip 50 is 1.1V.

Similarly, since the corresponding crystal oscillator of the second chip 60 is also the crystal oscillator 20, when the high level required by the second chip 60 is 1.3V, the second chip 60 requires a dc bias voltage of 0.3V, the second bias circuit 40 is configured to provide the dc bias voltage of 0.3V, and the high level finally input to the second chip 60 is 1.3V by adding the 1V output by the crystal oscillator 20.

When the voltage input value of the second power input terminal X2 of the first bias circuit 30 and the required dc bias voltage of the first bias circuit 30 are determined, the resistance values of the first resistor R1 and the second resistor R2 may be calculated according to the voltage input value of the second power input terminal X2 and the required dc bias voltage of the first bias circuit 30.

Similarly, when the voltage input value of the third power input terminal X3 of the second bias circuit 40 is determined, the resistance values of the third resistor R3 and the fourth resistor R4 may be calculated based on the voltage input value of the third power input terminal X3.

In some embodiments, the Power required by the first Power input terminal X1 may be provided by a Power Management IC (PMIC) of an electronic device or a separate corresponding Power supply. If there is a power management chip inside the first chip 50 or the second chip 60, the power provided by the first chip 50 or the second chip 60 may be directly used.

Similarly, the second Power input terminal X2 may adopt a first bias Power supply provided by a Power Management IC (PMIC) of an electronic device or a corresponding first bias Power supply, and the second Power input terminal X2 may also adopt the first bias Power supply provided by the first chip 50. The third Power input terminal X3 may employ a second bias Power supply provided by a Power Management IC (PMIC) of an electronic device or a separate corresponding second bias Power supply, and the third Power input terminal X3 may also employ the second bias Power supply provided by the second chip 60.

Referring to fig. 2, fig. 2 is a second circuit diagram of a common circuit according to an embodiment of the present disclosure.

In some embodiments, the common circuit further comprises a first adjusting module 70 and a second adjusting module 80, wherein the first adjusting module 70 is connected in series between the output terminal 22 of the crystal oscillator 20 and the signal input terminal 31 of the first bias circuit 30, and the second adjusting module 80 is connected in series between the output terminal 22 of the crystal oscillator 20 and the signal input terminal 41 of the second bias circuit 40. I.e. the first and

second conditioning modules

70 and 80 are connected in parallel at the output 22 of the crystal oscillator 20.

The first adjusting module 70 can filter the signal input from the crystal oscillator 20 to the first bias circuit 30. Meanwhile, the first adjusting module 70 can also isolate the signal interference of the first bias circuit 30 to the crystal oscillator 20, thereby avoiding the operation interference of the direct-current voltage of the first bias circuit 30 to the crystal oscillator 20 and the device damage of the crystal oscillator 20.

The first adjusting module 70 can also isolate the signal interference of the first bias circuit 30 to the second chip 60, and because the first bias circuit 30 uses a dc bias voltage, the first adjusting module 70 can isolate the dc signal of the first bias circuit 30, so that the signal entering the second chip 60 is not interfered.

The second conditioning module 80 is capable of filtering the signal input to the second bias circuit 40 from the crystal oscillator 20. Meanwhile, the second adjusting module 80 can also isolate the signal interference of the second bias circuit 40 to the crystal oscillator 20, thereby avoiding the working interference of the direct-current voltage of the second bias circuit 40 to the crystal oscillator 20 and the device damage of the crystal oscillator 20.

The second adjusting module 80 can also isolate the signal interference of the second bias circuit 40 to the first chip 50, and because the second bias circuit 40 uses a dc bias voltage, the second adjusting module 80 can isolate the dc signal of the second bias circuit 40, so that the signal entering the first chip 50 is not interfered.

Referring to fig. 3, fig. 3 is a third circuit diagram of the common circuit according to the embodiment of the present disclosure.

In some embodiments, the first adjusting module 70 may employ a fourth capacitor C2, the fourth capacitor C2 is disposed between the output terminal 22 of the crystal oscillator 20 and the signal input terminal 31 of the first bias circuit 30, the fourth capacitor C2 is capable of isolating the direct current of the first bias circuit 30, and the fourth capacitor C2 is capable of isolating the signal interference of the first bias circuit 30 to the crystal oscillator 20 and the second chip 60.

The second adjusting module 80 may employ a fifth capacitor C3, the fifth capacitor C3 is disposed between the output terminal 22 of the crystal oscillator 20 and the signal input terminal 41 of the second bias circuit 40, the fifth capacitor C3 is capable of isolating the direct current of the second bias circuit 40, and the fifth capacitor C3 is capable of isolating the signal interference of the second bias circuit 40 to the crystal oscillator 20 and the first chip 50.

In some embodiments, the first and

second adjusting modules

70 and 80 may also be well-designed circuits, such as resonant circuits designed after the output 22 of the crystal oscillator 20, which may filter out spurious signals outside the operating frequency of the first or

second chip

50 and 60.

In some embodiments, the filter module 11 in the filter circuit 10 may use the inductor L1, or may also use magnetic beads for filtering, and the filter module 11 may also be a filter circuit for filtering a specific frequency range, for example, if the high frequency spurious signal has a large influence on the operation of the crystal oscillator 20, the filter module 11 may be configured as a high frequency filter circuit to filter the high frequency spurious signal. The filtering module 11 may also be a resistor connected in series between the first power input terminal X1 and the input terminal 21 of the crystal oscillator 20, and capacitors are connected in parallel to two sides of the resistor to form the filtering module, so as to filter the electrical signal input by the first power input terminal X1.

Referring to fig. 4, fig. 4 is a fourth circuit diagram of the common circuit according to the embodiment of the disclosure.

In some embodiments, in the first bias circuit 30, it is also possible that the first capacitor C4 and the first resistor R1 are connected in parallel to the signal input terminal 31 of the first bias circuit 30, wherein one end of the first resistor R1 is connected to the signal input terminal 31 of the first bias circuit 30, and the other end of the first resistor R1 is connected to the second power input terminal X2. The first capacitor C4 is connected to the signal input terminal 31 of the first bias circuit 30, and the other end of the first capacitor C4 is connected to the fourth ground terminal G4. The first resistor R1 and the first capacitor C4 can adjust the dc bias voltage output by the first bias circuit 30, so that the high level output by the crystal oscillator 20 and the bias voltage output by the first bias circuit 30 can normally drive the first chip 50 to operate normally.

In some embodiments, the first resistor R1, the second resistor R2, and the first capacitor C4 may be connected in parallel to the signal input terminal 31 of the first bias circuit 30. Specifically, one end of the first resistor R1 is connected to the signal input terminal 31 of the first bias circuit 30, and the other end of the first resistor R1 is connected to the second power input terminal X2. The first capacitor C4 is connected to the signal input terminal 31 of the first bias circuit 30, and the other end of the first capacitor C4 is connected to the fourth ground terminal G4. The second resistor R2 is connected to the signal input terminal 31 of the first bias circuit 30, and the other end of the second resistor R2 is connected to the fourth ground terminal G4. The first resistor R1, the second resistor R2 and the first capacitor C4 may adjust the dc bias voltage output by the first bias circuit 30, so that the high level output by the crystal oscillator 20 and the bias voltage output by the first bias circuit 30 can normally drive the first chip 50 to normally operate.

In some embodiments, in the second bias circuit 40, it is also possible that the second capacitor C5 and the third resistor R3 are connected in parallel to the signal input terminal 41 of the second bias circuit 40, wherein one end of the third resistor R3 is connected to the signal input terminal 41 of the second bias circuit 40, and the other end of the third resistor R3 is connected to the third power input terminal X3. The second capacitor C5 is connected to the signal input terminal 41 of the second bias circuit 40, and the other end of the second capacitor C5 is connected to the fifth ground terminal G5. The third resistor R3 and the second capacitor C5 can adjust the dc bias voltage output by the second bias circuit 40, so that the high level output by the crystal oscillator 20 and the bias voltage output by the second bias circuit 40 can normally drive the second chip 60 to normally operate.

In some embodiments, the third resistor R3, the fourth resistor R4, and the second capacitor C5 may be connected in parallel to the signal input terminal 41 of the second bias circuit 40. Specifically, one end of the third resistor R3 is connected to the signal input terminal 41 of the second bias circuit 40, and the other end of the third resistor R3 is connected to the third power input terminal X3. The second capacitor C5 is connected to the signal input terminal 41 of the second bias circuit 40, and the other end of the second capacitor C5 is connected to the fifth ground terminal G5. The fourth resistor R4 is connected to the signal input terminal 41 of the second bias circuit 40, and the other end of the fourth resistor R4 is connected to the fifth ground terminal G5. The third resistor R3, the fourth resistor R4 and the second capacitor C5 may adjust the dc bias voltage output by the second bias circuit 40, so that the high level output by the crystal oscillator 20 and the bias voltage output by the second bias circuit 40 can normally drive the second chip 60 to normally operate.

Referring to fig. 5, fig. 5 is a fifth circuit diagram of the common circuit according to the embodiment of the disclosure.

In some embodiments, the first chip 50 and the second chip 60 may be connectable, and one of the first chip 50 and the second chip 60 may be a master chip and the other may be a slave chip. For example, the first chip 50 is a Micro Controller Unit (MCU), which may also be referred to as a single chip microcomputer. The second chip 60 is a radio frequency Transceiver chip, which may also be called a Transceiver (Transceiver) or a radio frequency Transceiver. The micro control chip can make the radio frequency transceiver chip a master chip, and the radio frequency transceiver chip is a slave chip.

In some embodiments, since the first chip 50 and the second chip 60 share the crystal oscillator 20, the first chip 50 and the second chip 60 are synchronous, and when the first chip 50 is a master chip, the state of the second chip 60 can be determined according to the clock signal of the first chip 50 itself, so as to better control the operating state of the second chip 60.

For example, because the micro control chip and the radio frequency transceiver chip use the same crystal oscillator (i.e. crystal oscillator 20), the clock signals of the micro control chip and the radio frequency transceiver chip are synchronous, the micro control chip can set automatic sleep and wake-up for the radio frequency transceiver chip, because the clocks of the micro control chip and the radio frequency transceiver chip are synchronous, the micro control chip can accurately know whether the radio frequency transceiver chip is in a sleep or wake-up state according to the clock signal of the micro control chip and the radio frequency transceiver chip, and does not need to inquire the radio frequency transceiver chip.

In practical applications, since the same crystal oscillator 20 is used in the first chip 50 and the second chip 60, the clock signals of the two are synchronous, which is more beneficial for the first chip 50 to control the second chip 60.

Meanwhile, the first chip 50 and the second chip 60 share the crystal oscillator 20, so that the cost required for designing the circuit is saved, and the occupied area for designing the circuit is also saved.

The common circuit can be applied to a plurality of scenes, for example, various electronic devices which need the oscillation circuit, such as televisions, computers, remote controllers, smart phones and intelligent wearable devices, and the common circuit can provide needed frequency for a communication system and generate clock signals and reference signals needed in the system for the electronic devices.

Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device including the common circuit according to an embodiment of the disclosure. Wherein the electronic device 90 comprises: an input unit 91, a display unit 92, a central processing unit 93, a power supply 94, a sensor 95 and a memory 96. Those skilled in the art will appreciate that the electronic device configuration shown in fig. 6 does not constitute a limitation of the electronic device and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.

The input unit 91 may be used to receive input numeric or character information and generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control. In particular, in one particular embodiment, the input unit 91 may include a touch-sensitive surface as well as other input devices. The input unit transmits the input data to the central processor 93, and can receive and execute commands from the central processor 93. In addition, touch sensitive surfaces may be implemented using various types of resistive, capacitive, infrared, and surface acoustic waves. The input unit 91 may include other input devices in addition to the touch-sensitive surface. In particular, other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like.

The display unit 92 may be used to display information input by or provided to a user and various graphical user interfaces of the electronic device, which may be made up of graphics, text, icons, video, and any combination thereof. The Display unit 92 may include a Display panel, and optionally, the Display panel may be configured in the form of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like.

The memory 96 may be used to store software programs and modules, and the central processor 93 executes various functional applications and data processing by operating the software programs and modules stored in the memory 96. The memory 96 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the electronic device, and the like. Further, the memory 96 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device. Accordingly, the memory 96 may further include a memory controller to provide the central processor 93 and the input unit 91 access to the memory 96.

The cpu 93 is a control center of the electronic device, connects various parts of the entire electronic device by using various interfaces and lines, and performs various functions of the electronic device and processes data by operating or executing software programs and/or modules stored in the memory 96 and calling data stored in the memory 96, thereby integrally monitoring the electronic device.

The electronic device also includes a power supply 94 (e.g., a battery) for powering the various components, which is preferably logically connected to the central processor 93 via a power management system, such that the functions of managing charging, discharging, and power consumption are performed via the power management system. The power supply 94 may also include any component including one or more dc or ac power sources, recharging systems, power failure detection circuitry, power converters or inverters, power status indicators, and the like.

The electronic device may also include at least one sensor 95, such as a light sensor, motion sensor, image sensor, and other sensors. In particular, the light sensor may include an ambient light sensor that may adjust the brightness of the display panel according to the brightness of ambient light, and a proximity sensor that may turn off the display panel and/or the backlight when the electronic device is moved to the ear. As one of the motion sensors, the gravity acceleration sensor can detect the magnitude of acceleration in each direction (generally, three axes), detect the magnitude and direction of gravity when the motion sensor is stationary, and can be used for applications (such as horizontal and vertical screen switching, related games, magnetometer attitude calibration) for recognizing the attitude of an electronic device, vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which may be further configured to the electronic device, detailed descriptions thereof are omitted.

Although not shown, the electronic device may further include a camera, a bluetooth module, and the like, which are not described in detail herein. Specifically, in this embodiment, the electronic device includes the sharing circuit provided in the above embodiments, and one crystal oscillator in the sharing circuit can be connected to a plurality of chips, so that the plurality of chips can operate normally. Because the shared circuit components are few in number and small in occupied area, the shared circuit components are easy to arrange in electronic equipment with small internal area, and meanwhile, the cost for manufacturing the electronic equipment is saved.

The common circuit provided by the embodiments of the present application is described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A shared circuit, the shared circuit comprising:

the crystal oscillator comprises an input end and an output end;

2. The sharing circuit of claim 1, further comprising a first adjusting module and a second adjusting module, wherein the first adjusting module is connected in series between the output of the crystal oscillator and the signal input of the first bias circuit, wherein the second adjusting module is connected in series between the output of the crystal oscillator and the signal input of the second bias circuit, wherein the first adjusting module is configured to isolate signal interference of the first bias circuit to the second chip, and wherein the second adjusting module is configured to isolate signal interference of the second bias circuit to the first chip.

3. The common circuit of claim 2, wherein the first adjusting module is further configured to isolate the signal interference of the first biasing circuit to the crystal oscillator and filter out the spurious signal output by the crystal oscillator, and wherein the second adjusting module is further configured to isolate the signal interference of the second biasing circuit to the crystal oscillator and filter out the spurious signal output by the crystal oscillator.

4. The common circuit of claim 1, wherein the first bias circuit comprises a first resistor and a second resistor, the first resistor and the second resistor are connected in parallel to a signal input terminal of the first bias circuit, the first resistor is connected to a first bias power supply, the second resistor is connected to ground, and the first resistor and the second resistor are used for adjusting a dc bias voltage of the first chip.

5. The common circuit of claim 4, wherein the first bias circuit further comprises a first capacitor, the first resistor and the first capacitor are connected in parallel to a signal input terminal of the first bias circuit, the first resistor is connected to a first bias power supply, and the first resistor and the first capacitor are used for adjusting a dc bias voltage of the first chip.

6. The common circuit of claim 1, wherein the second bias circuit comprises a third resistor and a fourth resistor, the third resistor and the fourth resistor are connected in parallel to a signal input terminal of the second bias circuit, the third resistor is connected to a second bias power supply, the fourth resistor is connected to ground, and the third resistor and the fourth resistor are used for adjusting a dc bias voltage of the second chip.

7. The common circuit of claim 6, wherein the second bias circuit further comprises a second capacitor, the third resistor and the second capacitor are connected in parallel to a signal input terminal of the second bias circuit, the third resistor is connected to a second bias power supply, and the third resistor and the second capacitor are used for adjusting the dc bias voltage of the first chip.

8. The sharing circuit according to any of claims 1 to 7, wherein the filtering circuit comprises a third capacitor and a filtering module, the filtering module is connected in series with the input terminal of the crystal oscillator, and the third capacitor is connected in parallel between the filtering module and the input terminal of the crystal oscillator.

9. The common circuit of claim 8, wherein the filtering module comprises an inductor or a magnetic bead, and the filtering module is configured to filter out spurious signals in the electrical signal when the electrical signal is input to the crystal oscillator.

10. An electronic device, characterized in that the electronic device comprises the common circuit of any of claims 1-9.