CN212033994U

CN212033994U - Based on two PWM ripples equalizer circuit that connect in parallel of DCDC

Info

Publication number: CN212033994U
Application number: CN202020044966.6U
Authority: CN
Inventors: 刘梦花; 梁光耀; 刘红伟; 郁建周
Original assignee: Jiaxing Fuer Electronic Technology Co ltd; Shanghai Baozhun Power Technology Co ltd
Current assignee: Jiaxing Fuer Electronic Technology Co ltd; Shanghai Baozhun Power Technology Co ltd
Priority date: 2020-01-09
Filing date: 2020-01-09
Publication date: 2020-11-27
Anticipated expiration: 2030-01-09

Abstract

The utility model discloses a based on parallelly connected equalizer circuit of two PWM ripples of DCDC, including the current detection circuit, the current detection circuit includes voltage input end, inductance L1, inductance L2, first IGBT (insulated gate bipolar transistor), second IGBT, the anodal one end electric connection with inductance L1 of voltage input end, inductance L1 is kept away from the anodal one end of voltage input end and first IGBT's projecting pole electric connection, the anodal one end electric connection still with inductance L2 of voltage input end, inductance L2 is kept away from the anodal one end of voltage input end and the projecting pole electric connection of second IGBT. The utility model discloses a based on parallelly connected equalizer circuit of two PWM ripples of DCDC, it can realize the current balance nature between the DCDC module.

Description

Based on two PWM ripples equalizer circuit that connect in parallel of DCDC

Technical Field

The utility model belongs to the technical field of the current balancing, concretely relates to based on parallelly connected equalizer circuit of two PWM ripples of DCDC.

Background

The disclosure number is CN201811563392, the subject name is a patent of invention of a battery voltage balancing device, and the technical scheme thereof discloses "N +1 switches, an isolation bidirectional DCDC converter and a battery management system, wherein the N +1 switches are respectively connected to the first sides of the 1 st to N th batteries and the second side of the nth battery, the isolation bidirectional DCDC converter has an energy storage unit, the isolation bidirectional DCDC converter is connected to the N +1 switches and the first side of the 1 st battery and the second side of the nth battery, the battery management system is respectively connected to the N batteries, the isolation bidirectional DCDC converter and the N +1 switches, and the input/output voltages of the isolation bidirectional DCDC converter are N × U and U, respectively.

Taking the above patent as an example, although the concept of current balancing DCDC (conversion from high voltage (low voltage) dc power to low voltage (high voltage) dc power) is disclosed, no adjustment is made by PWM (pulse width modulation), and therefore further improvement is needed. In addition, when the parameters of the devices are inconsistent in the parallel connection of the conventional DCDC, the currents of the DCDC modules are inconsistent, so that the load distribution among the modules is uneven, and even the overload damage of individual modules is caused.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a main aim at provides a based on parallelly connected equalizer circuit of two PWM ripples of DCDC, it can realize the current balance nature between the DCDC module.

Another object of the utility model is to provide a based on parallelly connected equalizer circuit of two PWM ripples of DCDC, it can realize that load distribution is even between the DCDC module.

In order to achieve the above object, the utility model discloses a based on parallelly connected equalizer circuit of two PWM ripples of DCDC, include:

the current detection circuit comprises a voltage input end, an inductor L1, an inductor L2, a first IGBT (insulated gate bipolar transistor) and a second IGBT, wherein the positive pole of the voltage input end is electrically connected with one end of an inductor L1, one end of the inductor L1, which is far away from the positive pole of the voltage input end, is electrically connected with the emitter of the first IGBT, the positive pole of the voltage input end is also electrically connected with one end of the inductor L2, and one end of the inductor L2, which is far away from the positive pole of the voltage input end, is electrically connected with the emitter of the second IGBT;

the current balancing circuit comprises a current I1, a current I2, a PI regulator (PI), a first PWM and a second PWM, wherein the difference value of the current I1 and the current I2 is electrically connected with the input end of the PI regulator, and the output end of the PI regulator respectively outputs the first PWM and the second PWM.

As a further preferable technical solution of the above technical solution, the current detection signal further includes a hall sensor CT1 and a hall sensor CT2, the hall sensor CT1 is located between the inductor L1 and the first IGBT, one end of the hall sensor CT1 is electrically connected to one end of the inductor L1 away from the positive electrode of the voltage input terminal, the other end of the hall sensor CT1 is electrically connected to the emitter of the first IGBT, the hall sensor CT2 is located between the inductor L2 and the second IGBT, one end of the hall sensor CT2 is electrically connected to one end of the inductor L2 away from the positive electrode of the voltage input terminal, the other end of the hall sensor CT2 is electrically connected to the emitter of the second IGBT, and the hall sensor CT1 and the hall sensor CT2 are used for detecting a current.

As a further preferable mode of the above-mentioned technical means, the current detection signal further includes a third IGBT, a fourth IGBT, and a voltage output terminal, wherein an emitter of the first IGBT is electrically connected to a collector of the third IGBT, an emitter of the third IGBT is electrically connected to a cathode of the voltage output terminal, a collector of the first IGBT is electrically connected to an anode of the voltage output terminal, an emitter of the second IGBT is electrically connected to a collector of the fourth IGBT, a collector of the second IGBT is electrically connected to an anode of the voltage output terminal, an emitter of the fourth IGBT is electrically connected to a cathode of the voltage output terminal, the first PWM is configured to drive a switch of the third IGBT, and the second PWM is configured to drive a switch of the fourth IGBT.

As a further preferable technical solution of the above technical solution, the current I1 is detected by the hall sensor CT1, and the current I2 is detected by the hall sensor CT 2.

As a further preferable embodiment of the above technical solution, the current balancing circuit further includes a zero current value, and the zero current value is located between the current I1 and the current I2 and the PI regulator.

As a further preferable aspect of the above aspect, the current balancing circuit further includes a PWM, and the PWM is electrically connected to the output terminal of the PI regulator.

Drawings

Fig. 1 is the utility model discloses a current detection circuit diagram based on two PWM ripples equalizer circuit that connect in parallel of DCDC.

Fig. 2 is the utility model discloses a current balance circuit diagram based on two PWM ripples equalizer circuit that connect in parallel of DCDC.

The reference numerals include: 1. a first IGBT; 2. a second IGBT; 3. a third IGBT; 4. a fourth IGBT; 5. a first PWM; 6. a second PWM; 7. and (7) PWM.

Detailed Description

The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents and other technical solutions without departing from the spirit and scope of the invention.

The utility model discloses a based on two PWM ripples equalizer circuit that connect in parallel of DCDC combines preferred embodiment below, further describes utility model's concrete embodiment.

Referring to fig. 1 of the drawings, fig. 1 is a current detection circuit diagram based on a DCDC double PWM wave parallel equalization circuit of the present invention, and fig. 2 is a current balance circuit diagram based on a DCDC double PWM wave parallel equalization circuit of the present invention.

In the embodiments of the present invention, those skilled in the art will note that the IGBT, DCDC, PWM, etc. of the present invention can be regarded as the prior art.

Preferred embodiments.

The utility model discloses a based on parallelly connected equalizer circuit of two PWM ripples of DCDC, a serial communication port, include:

the current detection circuit comprises a voltage input end Uin, an inductor L1, an inductor L2, a first IGBT1 and a second IGBT2, wherein the positive pole of the voltage input end Uin is electrically connected with one end of the inductor L1, one end, away from the positive pole of the voltage input end Uin, of the inductor L1 is electrically connected with the emitter of the first IGBT1, the positive pole of the voltage input end Uin is also electrically connected with one end of the inductor L2, and one end, away from the positive pole of the voltage input end Uin, of the inductor L2 is electrically connected with the emitter of the second IGBT 2;

the current balancing circuit comprises a current I1, a current I2, a PI regulator (PI), a first PWM5 and a second PWM6, wherein the difference value of the current I1 and the current I2 is electrically connected with the input end of the PI regulator, and the output end of the PI regulator respectively outputs a first PWM5 and a second PWM 6.

Specifically, the current detection signal further includes a hall sensor CT1 and a hall sensor CT2, the hall sensor CT1 is located between the inductor L1 and the first IGBT1, one end of the hall sensor CT1 is electrically connected to one end of the inductor L1 away from the positive electrode of the voltage input end Uin, the other end of the hall sensor CT1 is electrically connected to the emitter of the first IGBT1, the hall sensor CT2 is located between the inductor L2 and the second IGBT2, one end of the hall sensor CT2 is electrically connected to one end of the inductor L2 away from the positive electrode of the voltage input end Uin, the other end of the hall sensor CT2 is electrically connected to the emitter of the second IGBT CT2, and the hall sensor CT1 and the hall sensor CT2 are used for detecting a current.

More specifically, the current detection signal further includes a third IGBT3, a fourth IGBT4, and a voltage output terminal Uout, an emitter of the first IGBT1 is electrically connected to a collector of the third IGBT3, an emitter of the third IGBT3 is electrically connected to a cathode of the voltage output terminal Uout, a collector of the first IGBT1 is electrically connected to a positive electrode of the voltage output terminal Uout, an emitter of the second IGBT2 is electrically connected to a collector of the fourth IGBT4, a collector of the second IGBT2 is electrically connected to a positive electrode of the voltage output terminal Uout, an emitter of the fourth IGBT4 is electrically connected to a cathode of the voltage output terminal Uout, the first PWM5 is configured to drive a switch of the third IGBT3, and the second PWM6 is configured to drive a switch of the fourth IGBT 4.

Further, the hall sensor CT1 detects the current I1 (during operation of the DCDC module), and the hall sensor CT2 detects the current I2 (during operation of the DCDC module).

Still further, the current balancing circuit further includes a zero current value 0 (for comparing with the difference between the current I1 and the current I2, and then entering the PI regulator to obtain a compensation value), wherein the zero current value 0 is located between the current I1 and the current I2 and the PI regulator.

Preferably, the current balancing circuit further comprises a PWM7 (derived from an external voltage loop), the PWM7 being electrically connected to the output of the PI regulator.

Preferably, the difference between the PWM7 and the compensation value results in a first PWM5, and the sum of the PWM7 and the compensation value results in a second PWM 6.

Preferably, the inductor L1 and the inductor L2 are used as inductance elements of 2 DCDC modules.

It is worth mentioning that the technical features such as the IGBT, the DCDC, the PWM that the patent application of the present invention relates to should be regarded as the prior art, and the specific structure, the operating principle of these technical features and the control mode, the spatial arrangement mode that may involve adopt the conventional selection in this field can, should not be regarded as the invention point of the present invention is, the present invention does not further specifically expand the detailed description.

It will be apparent to those skilled in the art that modifications and variations can be made in the above-described embodiments, or some features of the invention may be substituted or omitted, and any modification, substitution, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims

1. A DCDC-based dual PWM wave parallel equalization circuit is characterized by comprising:

the current detection circuit comprises a voltage input end, an inductor L1, an inductor L2, a first IGBT and a second IGBT, wherein the positive pole of the voltage input end is electrically connected with one end of the inductor L1, one end of the inductor L1, which is far away from the positive pole of the voltage input end, is electrically connected with the emitter of the first IGBT, the positive pole of the voltage input end is also electrically connected with one end of the inductor L2, and one end of the inductor L2, which is far away from the positive pole of the voltage input end, is electrically connected with the emitter of the second IGBT;

the current balancing circuit comprises a current I1, a current I2, a PI regulator, a first PWM and a second PWM, wherein the difference value of the current I1 and the current I2 is electrically connected with the input end of the PI regulator, and the output end of the PI regulator respectively outputs the first PWM and the second PWM;

the current detection circuit further comprises a hall sensor CT1 and a hall sensor CT2, the hall sensor CT1 is located between the inductor L1 and the first IGBT, one end of the hall sensor CT1 is electrically connected with one end of the inductor L1, which is far away from the positive electrode of the voltage input end, the other end of the hall sensor CT1 is electrically connected with the emitter of the first IGBT, the hall sensor CT2 is located between the inductor L2 and the second IGBT, one end of the hall sensor CT2 is electrically connected with one end of the inductor L2, which is far away from the positive electrode of the voltage input end, the other end of the hall sensor CT2 is electrically connected with the emitter of the second IGBT, and the hall sensor CT1 and the hall sensor CT2 are used for detecting current;

the current detection circuit further comprises a third IGBT, a fourth IGBT and a voltage output end, wherein an emitting electrode of the first IGBT is electrically connected with a collecting electrode of the third IGBT, an emitting electrode of the third IGBT is electrically connected with a negative electrode of the voltage output end, a collecting electrode of the first IGBT is electrically connected with a positive electrode of the voltage output end, an emitting electrode of the second IGBT is electrically connected with a collecting electrode of the fourth IGBT, a collecting electrode of the second IGBT is electrically connected with a positive electrode of the voltage output end, an emitting electrode of the fourth IGBT is electrically connected with a negative electrode of the voltage output end, the first PWM is used for driving the third IGBT to be switched on and switched off, and the second PWM is used for driving the fourth IGBT to be switched on and switched off.

2. The DCDC-based double PWM wave parallel equalization circuit according to claim 1, wherein said current I1 is detected by said Hall sensor CT1, and said current I2 is detected by said Hall sensor CT 2.

3. The DCDC-based dual PWM wave parallel equalization circuit of claim 1, wherein said current balancing circuit further comprises a zero current value, said zero current value being located between said current I1 and current I2 and said PI regulators.

4. The DCDC-based dual-PWM wave parallel balancing circuit according to claim 1, wherein the current balancing circuit further comprises a PWM electrically connected to the output terminal of the PI regulator.