CN212009368U - Servo controller based on FPGA - Google Patents
Servo controller based on FPGA Download PDFInfo
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- CN212009368U CN212009368U CN201922240446.2U CN201922240446U CN212009368U CN 212009368 U CN212009368 U CN 212009368U CN 201922240446 U CN201922240446 U CN 201922240446U CN 212009368 U CN212009368 U CN 212009368U
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Abstract
A servo controller based on FPGA is composed of an FPGA chip, wherein the FPGA chip comprises a user interface, an encoder module, a current sampling module, a position loop control module, a speed loop control module and a current loop control module. The user interface is respectively and electrically connected with the position loop control module, the speed loop control module and the current loop control module. The encoder module is respectively and electrically connected with the position loop control module, the speed loop control module and the current loop control module. The current sampling module is electrically connected with the current loop control module. The position loop control module is electrically connected with the speed loop control module, and the speed loop control module is electrically connected with the current loop control module. The utility model discloses dynamic response is fast, and control reliability is high.
Description
Technical Field
The utility model relates to a motor control technique especially relates to servo control technique.
Background
The AC servo driving technology is one of the key technologies of modern electromechanical equipment. The servo control is usually a three-loop control system, which comprises a current loop, a speed loop and a position loop from inside to outside in sequence, wherein the current loop is an inner loop of the system, the speed loop and the position loop are outer loops of the system, and the performance of the outer loops depends on the performance of the inner loops. The current loop is the key for improving the control precision and the response speed in the servo control system, and in order to improve the dynamic and static performances of the servo system, the high-frequency response and high-precision current loop control are necessary.
The conventional servo drive control device is shown in fig. 1, and comprises a programmable logic device FPGA and an MCU (also can be an ARM, a DSP, etc.) chip, wherein the FPGA is responsible for current sampling, encoder signal processing, and pulse input/output processing; the MCU is responsible for three-loop control of a current loop, a speed loop and a position loop of the motor and user interface processing; and the FPGA and the MCU exchange data through a parallel port or a serial port bus, and the MCU configures the FPGA when the FPGA is electrified. In the MCU, a current loop control module performs PID calculation after making a difference between a current instruction output by a speed loop control module and a current sampling value output by a current sampling module, performs decoupling, compensation processing and coordinate transformation on the result of the PID calculation to obtain three paths of duty ratio signals, performs PWM modulation according to the duty ratio, and generates three-phase PWM signals for driving a three-phase inverter.
In the existing servo control technology, the current loop is generally implemented by the MCU in a pure software manner, wherein the execution process of the control algorithm adopts a serial execution mode based on the system clock. The method is limited by the running mode of serial code execution, so that the execution time of a current loop algorithm is long, and the time delay from current sampling to pulse width modulation duty ratio updating is long, so that the control precision of the whole servo control system is not high, the dynamic response is slow, and the system can be unstable in severe cases. In addition, because a parallel or serial bus is usually adopted between the FPGA and the MCU for data exchange, the FPGA and the MCU are connected and communicated through tens of signal lines, and any signal line with poor contact will cause data exchange error and cause failure, thereby affecting the reliability of the system.
Disclosure of Invention
The utility model aims to solve the technical problem that a servo controller that dynamic response is fast, the reliability is high is provided.
The embodiment of the utility model provides a servo controller based on FPGA, servo controller based on FPGA comprises the FPGA chip, and the FPGA chip includes user interface, encoder module, current sampling module, position ring control module, speed ring control module and electric current ring control module; the user interface is respectively electrically connected with the position loop control module, the speed loop control module and the current loop control module, and is used for receiving an external position instruction, an external speed instruction or an external current instruction from the upper computer, respectively sending the received external position instruction, external speed instruction and external current instruction to the position loop control module, the speed loop control module and the current loop control module, and feeding back the running states of the position loop control module, the speed loop control module and the current loop control module to the upper computer; the encoder module is respectively electrically connected with the position loop control module, the speed loop control module and the current loop control module and is used for receiving the motor rotor operation angle acquired by the encoder, carrying out differential calculation on the motor rotor operation angle to obtain a motor operation speed, respectively sending the motor rotor operation angle to the position loop control module and the current loop control module, and sending the motor operation speed to the speed loop control module; the current sampling module is electrically connected with the current loop control module and is used for receiving an externally input current sampling signal, conditioning the current sampling signal and sending the conditioned current sampling signal to the current loop control module; the position loop control module is electrically connected with the speed loop control module, the speed loop control module is electrically connected with the current loop control module, and the position loop control module, the speed loop control module and the current loop control module are respectively used for realizing position closed-loop control, speed closed-loop control and current closed-loop control of the motor.
The utility model discloses following advantage and characteristics have at least:
the FPGA-based servo controller of the embodiment adopts a parallel processing mode based on FPGA hardware logic to realize each control module required by servo control, shortens the execution time of a current loop algorithm, effectively improves the refresh frequency of a current loop, and expands the bandwidth of a servo system. In addition, the servo controller realizes speed control, position control and a user interface through the hardware logic of the FPGA, realizes the servo control of the motor by the single FPGA chip, avoids the use of the MCU chip and improves the reliability.
Drawings
Fig. 1 shows a schematic diagram of a conventional servo control device.
Fig. 2 shows a schematic circuit diagram of an FPGA-based servo controller according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Please refer to fig. 2. According to the utility model discloses a servo controller based on FPGA includes FPGA chip 100, and FPGA chip 100 includes user interface 11, encoder module 12, current sampling module 13, overcurrent protection module 14, position ring control module 15, speed ring control module 16 and current ring control module 17.
The user interface 11 is electrically connected to the position loop control module 15, the speed loop control module 16, and the current loop control module 17, and is configured to receive an external position instruction, an external speed instruction, or an external current instruction from the upper computer 2, send the received external position instruction to the position loop control module 15, send the received external speed instruction to the speed loop control module 16, send the received external current instruction to the current loop control module 17, and feed back the operating states of the position loop control module 15, the speed loop control module 16, and the current loop control module 17 to the external upper computer 2. The user interface 11 receives only one of the external position command, the external speed command, and the external current command at the same time. The above-mentioned operation states include, but are not limited to, an execution state of the position loop control module 15 on the received external position command (e.g., whether the servo motor has reached an externally given external position designation received by the position loop control module 15), an execution state of the speed loop control module 16 on the received external speed command, an execution state of the current loop control module 17 on the received external current command, and the like.
The encoder module 12 is electrically connected to the position loop control module 15, the speed loop control module 16 and the current loop control module 17, and is configured to receive the motor rotor operating angle acquired by the encoder 3, perform differential calculation on the motor rotor operating angle to obtain a motor operating speed, send the motor rotor operating angle to the position loop control module 15 and the current loop control module 17, and send the motor operating speed to the speed loop control module 16 for speed closed-loop control and current vector control.
Further, the encoder module 12 is electrically connected to the user interface 11, and is configured to monitor an operation state of the encoder in real time, and feed back error information to the upper computer 2 through the user interface 11 when a communication with the encoder 3 fails.
The current sampling module 13 is electrically connected to the current loop control module 17, and is configured to receive an externally input current sampling signal, condition the current sampling signal, and send the conditioned current sampling signal to the current loop control module 17. The signal conditioning includes, but is not limited to, filtering, signal scaling, and the like.
The overcurrent protection module 14 is electrically connected to the current sampling module 13 and the current loop control module 17, and is configured to determine whether a current sampling signal received by the current sampling module is greater than a preset current threshold, and if the current sampling signal is greater than the current threshold, send an overcurrent protection signal to the current loop control module 17, where the current loop control module 17 is configured to stop outputting a three-phase PWM signal for driving the three-phase inverter 5 when receiving the overcurrent protection signal.
In the present embodiment, the over-current protection module 14 is implemented by constructing a Sinc fast filter inside the FPGA 100. The overcurrent protection module 14 detects whether the current sampling value exceeds a preset current threshold value through a Sigma-Delta demodulator and a comparator implemented by hardware logic, and if the current sampling value exceeds the preset current threshold value, the current loop control module 17 is informed to turn off the output of the PWM signal, so that the motor and the driver are protected to prevent the motor and the driver from being damaged by overlarge current. Because the overcurrent protection module 14 is implemented by adopting a Sinc fast filter built in the FPGA, the extraction rate and the sampling time of the Sinc fast can be flexibly configured according to the characteristics of the external analog-to-digital converter 4, so that the balance between the sampling time and the sampling precision is achieved, and the threshold value of the comparator can be configured through parameters, so that the current threshold value of the overcurrent protection can be configured according to the power level as required, and the flexibility of the overcurrent protection is higher.
Further, the current sampling module 13 and the overcurrent protection module 14 are respectively electrically connected to the user interface 11, and the user interface 11 is configured to feed back the operating states of the current sampling module 13 and the overcurrent protection module 14 to an upper computer, such as an overcurrent state.
The position loop control module 15 is electrically connected with the speed loop control module 16, the speed loop control module 16 is electrically connected with the current loop control module 17, and the position loop control module 15, the speed loop control module 16 and the current loop control module 17 are respectively used for realizing position closed-loop control, speed closed-loop control and current closed-loop control of the motor.
In this embodiment, the position loop control module 15 is configured to perform PID calculation after a difference is made between the external position instruction and the motor rotor operating angle output by the encoder module 12, to obtain an internal speed instruction, and output the internal speed instruction to the speed loop control module 16. The speed loop control module 16 is configured to perform PID calculation after subtracting the external speed instruction or the internal speed instruction from the motor running speed output by the encoder module 12, to obtain an internal current instruction, and output the internal current instruction to the current loop control module 17. The current loop control module 17 is configured to perform PID calculation after a difference is made between the external current instruction or the internal current instruction and the current sampling value output by the current sampling module, perform decoupling, compensation processing, and coordinate conversion on a result of the PID calculation to obtain three duty ratio signals, perform PWM modulation according to the duty ratios, and generate three-phase PWM signals for driving the three-phase inverter.
Due to the parallel execution structure of FPGA hardware logic, the operation time of all modules can operate in dozens of FPGA clock cycles, the calculation time of the whole current loop is shortened to be within 1us, the delay caused by the calculation of the current loop is reduced, the current response speed is improved, and the bandwidth of a servo system is expanded. Furthermore, the utility model discloses a servo controller all realizes speed control, position control and user interface through FPGA's hardware logic, has realized the servo control of monolithic FPGA chip to the motor, has avoided walking the line to between MCU chip and the FPGA chip, has improved servo control's reliability.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. The FPGA-based servo controller is characterized by comprising an FPGA chip, wherein the FPGA chip comprises a user interface, an encoder module, a current sampling module, a position loop control module, a speed loop control module and a current loop control module;
the user interface is respectively electrically connected with the position loop control module, the speed loop control module and the current loop control module, and is used for receiving an external position instruction, an external speed instruction or an external current instruction from an upper computer, respectively sending the received external position instruction, external speed instruction and external current instruction to the position loop control module, the speed loop control module and the current loop control module, and feeding back the running states of the position loop control module, the speed loop control module and the current loop control module to the upper computer;
the encoder module is respectively electrically connected with the position loop control module, the speed loop control module and the current loop control module, and is used for receiving the motor rotor operation angle collected by the encoder, carrying out differential calculation on the motor rotor operation angle to obtain a motor operation speed, respectively sending the motor rotor operation angle to the position loop control module and the current loop control module, and sending the motor operation speed to the speed loop control module;
the current sampling module is electrically connected with the current loop control module and is used for receiving an externally input current sampling signal, conditioning the current sampling signal and sending the conditioned current sampling signal to the current loop control module;
the position loop control module is electrically connected with the speed loop control module, the speed loop control module is electrically connected with the current loop control module, and the position loop control module, the speed loop control module and the current loop control module are respectively used for realizing position closed-loop control, speed closed-loop control and current closed-loop control of the motor.
2. The FPGA-based servo controller of claim 1, wherein the encoder module is electrically connected to the user interface, and the encoder module is configured to monitor an operating status of the encoder in real time and feed back error information to the upper computer through the user interface when communication with the encoder fails.
3. The FPGA-based servo controller of claim 1, comprising an overcurrent protection module, wherein the overcurrent protection module is electrically connected to the current sampling module and the current loop control module, respectively, and configured to determine whether a current sampling signal received by the current sampling module is greater than a preset current threshold, and if so, send an overcurrent protection signal to the current loop control module;
and the current loop control module is used for stopping outputting a three-phase PWM signal for driving the three-phase inverter when receiving the overcurrent protection signal.
4. The FPGA-based servo controller of claim 3, wherein the over-current protection module is comprised of a Sinc fast filter.
5. The FPGA-based servo controller of claim 3, wherein the current sampling module and the over-current protection module are respectively electrically connected with a user interface, and the user interface is used for feeding back the operating states of the current sampling module and the over-current protection module to the upper computer.
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| CN201922240446.2U CN212009368U (en) | 2019-12-14 | 2019-12-14 | Servo controller based on FPGA |
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| CN201922240446.2U CN212009368U (en) | 2019-12-14 | 2019-12-14 | Servo controller based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114200872A (en) * | 2022-02-16 | 2022-03-18 | 广东科伺智能科技有限公司 | Band-type brake system of servo motor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114200872A (en) * | 2022-02-16 | 2022-03-18 | 广东科伺智能科技有限公司 | Band-type brake system of servo motor |
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