CN211930788U

CN211930788U - Master-slave configurable Hart interface circuit

Info

Publication number: CN211930788U
Application number: CN202021085302.0U
Authority: CN
Inventors: 周国顺; 李崧
Original assignee: Dalian Neusoft University of Information
Current assignee: Dalian Neusoft University of Information
Priority date: 2020-06-12
Filing date: 2020-06-12
Publication date: 2020-11-13
Anticipated expiration: 2030-06-12

Abstract

The embodiment of the utility model discloses Hart interface circuit that principal and subordinate are configurable, it includes: the Hart slave mode circuit, the Hart master mode circuit, the Hart signal filter circuit, the Hart modem, the master controller and the power circuit; one end of the Hart slave mode circuit is electrically connected with the terminal of the Hart slave terminal, and the other end of the Hart slave mode circuit is electrically connected with the Hart modem; one end of the Hart main mode circuit is electrically connected with a wiring terminal of the Hart main terminal, and the other end of the Hart main mode circuit is electrically connected with the Hart modem; the Hart signal filter circuit is electrically connected with the Hart modem; the Hart modem is electrically connected with the main controller. The utility model can flexibly configure the corresponding interface circuit according to the requirement, and realize the digital communication with the industrial field bus; meanwhile, the product design of engineering personnel can be simplified, and a master-slave configurable hart interface circuit is provided for users on the premise of not increasing the cost.

Description

Master-slave configurable Hart interface circuit

Technical Field

The utility model relates to a communication interface technical field especially relates to a Hart interface circuit that master slave is configurable.

Background

The original old analog transmitter gradually quits the historical stage, and is replaced by an intelligent transmitter taking a microcontroller as a data processing and control core. The intelligent transmitter expands the functions of the analog transmitter, improves the measurement precision and the working reliability, and can easily realize the functions of linear processing, temperature compensation, automatic zero point and range adjustment, digital communication and the like.

Because a large number of transmitters with 4-20mA standards are still available in industrial fields, the HART communication protocol is proposed by Rosemount, USA in consideration of compatibility with standard analog signals. Currently, the HART protocol has become one of the most widely used field communication protocols worldwide.

Currently, the existing HART-based modem circuit is quite complex in design, and basically, a slave mode intelligent transmitter is adopted more according to the application requirement. However, if the field actuator needs to be controlled by 4-20mA and the control parameters can be configured, the HART master mode interface circuit is additionally adopted.

Disclosure of Invention

Based on this, in order to solve the deficiency that exists in prior art, specially proposed a kind of principal and subordinate configurable hart interface circuit.

A master-slave configurable Hart interface circuit, comprising: the Hart slave mode circuit, the Hart master mode circuit, the Hart signal filter circuit, the Hart modem, the master controller and the power circuit; one end of the Hart slave mode circuit is electrically connected with the terminal of the Hart slave terminal, and the other end of the Hart slave mode circuit is electrically connected with the Hart modem; one end of the Hart main mode circuit is electrically connected with a wiring terminal of the Hart main terminal, and the other end of the Hart main mode circuit is electrically connected with the Hart modem; the Hart signal filter circuit is electrically connected with the Hart modem; the Hart modem is electrically connected with the main controller.

Optionally, in one embodiment, the Hart modem and the master controller are connected through a UART interface and an SPI interface.

Optionally, in one embodiment, the Hart signal filtering circuit employs a band-pass filter.

Optionally, in one embodiment, the Hart modem is an NCN5193 CMOS modem.

Optionally, in one embodiment, the Hart master mode circuit includes: a first resistor R16, a second resistor R17, a third resistor R18, a fourth resistor R19, a fifth resistor R20, a sixth resistor R21, a seventh resistor R22, a first PNP transistor Q2, a first analog switch U2, a first capacitor C8, a second capacitor C9 and a first operational amplifier AS 2A; one end of the first resistor R16 is connected with the RTS pin, and the other end is connected with the base of the first PNP transistor Q2; the emitter of the first PNP transistor Q2 is connected with a power supply, and the collector of the first PNP transistor Q2 is connected with the non-inverting input end of a first operational amplifier AS 2A; one end of the second resistor R17 is connected with the collector of the first PNP transistor Q2, and the other end is grounded; one end of the fifth resistor R20 is connected with an ARTF pin, and the other end is connected with the non-inverting input end of the first operational amplifier AS 2A; the inverting input end of the first operational amplifier AS2A is grounded, and the output end of the first operational amplifier AS2A is connected with the moving end of a first analog switch U2; one motionless end of the first analog switch U2 is connected with the LOOP + terminal of the Hart main terminal through a first capacitor C8, and the other motionless end is connected with the collector of a first PNP transistor Q2; one end of the third resistor R18 is connected with an ADC pin, and the other end of the third resistor R18 is connected with an LOOP + terminal of the Hart main terminal; one end of the fourth resistor R19 is connected with the third resistor R18, and the other end of the fourth resistor R19 is connected with a LOOP-terminal of the Hart main terminal; one end of the sixth resistor R21 is connected with a T × AM pin through a seventh resistor R22; one end of the second capacitor C9 is connected to the output end of the first operational amplifier AS2A, and the other end is connected to the inverting input end of the first operational amplifier AS 2A.

Optionally, in one embodiment, the Hart slave mode circuit includes an eighth resistor R9, a ninth resistor R10, a tenth resistor R11, an eleventh resistor R12, a twelfth resistor R13, a thirteenth resistor R14, a fourteenth resistor R15, a first NPN transistor Q1, a third capacitor C5, a fourth capacitor C6, a fifth capacitor C7, and a second operational amplifier AS 1A; one end of the eighth resistor R9 is connected to the txas pin through the third capacitor C5, and the other end is connected to the non-inverting input terminal of the second operational amplifier AS 1A; the output end of the second operational amplifier AS1A is connected with the base of a first NPN transistor Q1, the non-inverting input end of the second operational amplifier is connected with a power supply, and the inverting input end of the second operational amplifier AS1A is grounded; the collector of the first NPN transistor Q1 is connected with the LOOP + terminal of the Hart slave terminal, and the emitter of the first NPN transistor Q1 is connected with the LOOP-terminal of the Hart slave terminal through a tenth resistor R11 and an eleventh resistor R12; one end of the tenth resistor R11 is connected to the emitter of the first NPN transistor Q1, and the other end is connected to an eleventh resistor R12; one end of the eleventh resistor R12 is grounded, and the other end of the eleventh resistor R12 is connected with a LOOP-terminal of the Hart slave terminal; one end of the fourth capacitor C6 is connected to the inverting input terminal of the second operational amplifier AS1A, and the other end is connected to the output terminal of the second operational amplifier AS 1A; one end of the ninth resistor R10 is connected with the inverting input end of the second operational amplifier AS1A, and the other end is connected with the LOOP-terminal of the Hart slave terminal through a twelfth resistor R13; one end of the thirteenth resistor R14 is connected with the DAC pin, the other end of the thirteenth resistor R14 is connected with a fourteenth resistor R15, and the other end of the fourteenth resistor R15 is connected with a twelfth resistor R13; one end of the fifth capacitor C7 is connected to the thirteenth resistor R14 and the fourteenth resistor R15, respectively, and the other end is grounded.

Optionally, in one embodiment, the Hart interface circuit further includes a Hart master slave mode configuration circuit.

Implement the embodiment of the utility model provides a, will have following beneficial effect:

the utility model relates to a Hart interface circuit that master slave mode can switch configuration, it can send the required electric current ring of output under the slave mode, can accept the electric current signal that control system sent and be used for control under the master mode, and can also modulate and demodulate Hart carrier signal on the electric current ring and then enlarged the product range of application for the user; meanwhile, the clock, the analog quantity output and the working mode of the Hart modulation and demodulation chip can be set through the SPI interface of the MCU, and Hart communication with field equipment can be completed through the UART interface. In a word, the utility model can flexibly configure the corresponding interface circuit according to the requirement, and realize the digital communication with the industrial field bus; meanwhile, the product design of engineering personnel can be simplified, and a master-slave configurable hart interface circuit is provided for users on the premise of not increasing the cost.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Wherein:

FIG. 1 is a circuit schematic of the Hart interface circuit in one embodiment;

FIG. 2 is a circuit diagram of the Hart master mode circuit in one embodiment;

FIG. 3 is a circuit diagram of the Hart slave mode circuit in one embodiment;

FIG. 4 is a circuit diagram of the Hart signal filter circuit in one embodiment;

FIG. 5 is a circuit diagram of the Hart master slave mode configuration circuit in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. The first and second elements are both elements, but they are not the same element.

In order to solve the problems in the prior art, in this embodiment, a master-slave configurable Hart interface circuit is particularly proposed, which can implement configuration switching in a master-slave mode, for example, in a slave mode, a 4-20mA current loop can be output in a variable transmission manner, in a master mode, a 4-20mA current signal sent by a DCS control system can be received and used for control, and a Hart carrier signal on the current loop can be modulated and demodulated. Based on the design principle, as shown in fig. 1, the Hart interface circuit includes a Hart slave mode circuit, a Hart master mode circuit, a Hart signal filter circuit, a Hart modem, a master controller and a low power consumption power circuit (not shown in the figure); one end of the Hart slave mode circuit is electrically connected with the terminal of the Hart slave terminal, and the other end of the Hart slave mode circuit is electrically connected with the Hart modem; one end of the Hart main mode circuit is electrically connected with a wiring terminal of the Hart main terminal, and the other end of the Hart main mode circuit is electrically connected with the Hart modem; the Hart signal filter circuit is electrically connected with the Hart modem; the Hart modem is electrically connected with the main controller.

In some specific embodiments, the master employs an STM32L152RCT6 low power embedded microcontroller; STM32L152RCT6 is a low power embedded microcontroller capable of receiving and sending communication signals to a modem chip, i.e., the Hart modem, and transforming the acquired sensor signals into engineering dimensions; the Hart modem employs an NCN5193 CMOS modem. The corresponding working process is as follows: the low-power consumption power supply circuit provides power (3.0V) for the main controller and the Hart modem to use, specifically: in the slave mode, a sensor signal is converted into a 4-20mA current to be transmitted to a control room, a Hart signal of a main device (usually an upper computer or a control system) can be loaded, and the Hart signal is converted into a standard RS232 communication signal through an NCN5193 CMOS modem to be communicated with an STM32L152RCT6 embedded microcontroller with low power consumption; in the main mode, the Hart signal is loaded on a 4-20mA current loop output by a control room and used for control.

In some embodiments, the Hart signal filtering circuit uses a band-pass filter to separate the Hart digital signal from the 4-20mA signal. As shown in fig. 4, a typical Sallen-Key band-pass filter is used, which is placed inside the NCN5193 chip; the filter range of this filter is 620Hz to 2500Hz, while the Hart signal is 1200Hz and 2400Hz, which just covers the signal frequency.

In some specific embodiments, the Hart modem is connected to the master controller through a UART interface and an SPI interface.

In some specific embodiments, as shown in fig. 2, the design points of the main mode Hart interface circuit are as follows: the circuit can work under the low current of 3.5mA, so the low-power-consumption circuit design is needed; if on one hand, a 4-20mA signal needs to be acquired, the signal can be converted into a 0.5-2.5V voltage signal by a 125-ohm precision sampling resistor R19 so that the voltage signal can be converted into a digital quantity by a main controller for control output; on the other hand, the Hart command is continuously received, and corresponding information is sent when response is needed; here, the RTS request sending signal is used for starting a sending circuit through a 74LVC1G66 analog switch, so that the purpose of power saving is achieved; then, for the above design purpose, a specific Hart master mode circuit includes: a first resistor R16, a second resistor R17, a third resistor R18, a fourth resistor R19, a fifth resistor R20, a sixth resistor R21, a seventh resistor R22, a first PNP transistor Q2, a first analog switch U2, a first capacitor C8, a second capacitor C9 and a first operational amplifier AS 2A; one end of the first resistor R16 is connected with the RTS pin, and the other end is connected with the base of the first PNP transistor Q2; the emitter of the first PNP transistor Q2 is connected with a power supply, and the collector of the first PNP transistor Q2 is connected with the non-inverting input end of a first operational amplifier AS 2A; one end of the second resistor R17 is connected with the collector of the first PNP transistor Q2, and the other end is grounded; one end of the fifth resistor R20 is connected with an ARTF pin, and the other end is connected with the non-inverting input end of the first operational amplifier AS 2A; the inverting input end of the first operational amplifier AS2A is grounded, and the output end of the first operational amplifier AS2A is connected with the moving end of a first analog switch U2; one motionless end of the first analog switch U2 is connected with the LOOP + terminal of the Hart main terminal through a first capacitor C8, and the other motionless end is connected with the collector of a first PNP transistor Q2; one end of the third resistor R18 is connected with an ADC pin, and the other end of the third resistor R18 is connected with an LOOP + terminal of the Hart main terminal; one end of the fourth resistor R19 is connected with the third resistor R18, and the other end of the fourth resistor R19 is connected with a LOOP-terminal of the Hart main terminal; one end of the sixth resistor R21 is connected with a T × AM pin through a seventh resistor R22; one end of the second capacitor C9 is connected to the output end of the first operational amplifier AS2A, and the other end is connected to the inverting input end of the first operational amplifier AS 2A.

In some specific embodiments, AS shown in fig. 3, the Hart slave mode circuit includes an eighth resistor R9, a ninth resistor R10, a tenth resistor R11, an eleventh resistor R12, a twelfth resistor R13, a thirteenth resistor R14, a fourteenth resistor R15, a first NPN transistor Q1, a third capacitor C5, a fourth capacitor C6, a fifth capacitor C7, and a second operational amplifier AS 1A; one end of the eighth resistor R9 is connected to the txas pin through the third capacitor C5, and the other end is connected to the non-inverting input terminal of the second operational amplifier AS 1A; the output end of the second operational amplifier AS1A is connected with the base of a first NPN transistor Q1, the non-inverting input end of the second operational amplifier is connected with a power supply, and the inverting input end of the second operational amplifier AS1A is grounded; the collector of the first NPN transistor Q1 is connected with the LOOP + terminal of the Hart slave terminal, and the emitter of the first NPN transistor Q1 is connected with the LOOP-terminal of the Hart slave terminal through a tenth resistor R11 and an eleventh resistor R12; one end of the tenth resistor R11 is connected to the emitter of the first NPN transistor Q1, and the other end is connected to an eleventh resistor R12; one end of the eleventh resistor R12 is grounded, and the other end of the eleventh resistor R12 is connected with a LOOP-terminal of the Hart slave terminal; one end of the fourth capacitor C6 is connected to the inverting input terminal of the second operational amplifier AS1A, and the other end is connected to the output terminal of the second operational amplifier AS 1A; one end of the ninth resistor R10 is connected with the inverting input end of the second operational amplifier AS1A, and the other end is connected with the LOOP-terminal of the Hart slave terminal through a twelfth resistor R13; one end of the thirteenth resistor R14 is connected with the DAC pin, the other end of the thirteenth resistor R14 is connected with a fourteenth resistor R15, and the other end of the fourteenth resistor R15 is connected with a twelfth resistor R13; one end of the fifth capacitor C7 is connected to the thirteenth resistor R14 and the fourteenth resistor R15, respectively, and the other end is grounded. The circuit can well complete the superposition of digital-to-analog conversion and Hart signals and generate 4-20mA signals corresponding to sensing signals.

In some specific embodiments, the Hart interface circuit further comprises a Hart master slave mode configuration circuit, as shown in fig. 5, which completes the configuration of the master slave mode through two jumper caps. The single-pole double-throw analog switch chip 74LVC1G3157 selects a channel through the S end; when Jumper1 is connected, the S end is at low level, the A end is communicated with the B1 end, namely the TxAM connection TxA signal is in a main mode; conversely, when Jumper2 is connected, the S terminal is high, and the A terminal is connected to the B2 terminal, i.e., the TxAS connection TxA signal is in slave mode.

Therefore, the utility model can flexibly configure the corresponding interface circuit according to the requirement, and realize the digital communication with the industrial field bus; meanwhile, the product design of engineering personnel can be simplified, and a master-slave configurable hart interface circuit is provided for users on the premise of not increasing the cost.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A master-slave configurable Hart interface circuit, comprising: the Hart slave mode circuit, the Hart master mode circuit, the Hart signal filter circuit, the Hart modem, the master controller and the power circuit; one end of the Hart slave mode circuit is electrically connected with the terminal of the Hart slave terminal, and the other end of the Hart slave mode circuit is electrically connected with the Hart modem; one end of the Hart main mode circuit is electrically connected with a wiring terminal of the Hart main terminal, and the other end of the Hart main mode circuit is electrically connected with the Hart modem; the Hart signal filter circuit is electrically connected with the Hart modem; the Hart modem is electrically connected with the main controller.

2. The master-slave configurable Hart interface circuit of claim 1, wherein the Hart modem is connected to the master controller via a UART interface and an SPI interface.

3. The master-slave configurable Hart interface circuit of claim 1, wherein the Hart modem employs an NCN5193 CMOS modem.

4. The master-slave configurable Hart interface circuit of claim 3, wherein the Hart master mode circuit comprises: a first resistor R16, a second resistor R17, a third resistor R18, a fourth resistor R19, a fifth resistor R20, a sixth resistor R21, a seventh resistor R22, a first PNP transistor Q2, a first analog switch U2, a first capacitor C8, a second capacitor C9 and a first operational amplifier AS 2A; one end of the first resistor R16 is connected with the RTS pin, and the other end is connected with the base of the first PNP transistor Q2; the emitter of the first PNP transistor Q2 is connected with a power supply, and the collector of the first PNP transistor Q2 is connected with the non-inverting input end of a first operational amplifier AS 2A; one end of the second resistor R17 is connected with the collector of the first PNP transistor Q2, and the other end is grounded; one end of the fifth resistor R20 is connected with an ARTF pin, and the other end is connected with the non-inverting input end of the first operational amplifier AS 2A; the inverting input end of the first operational amplifier AS2A is grounded, and the output end of the first operational amplifier AS2A is connected with the moving end of a first analog switch U2; one motionless end of the first analog switch U2 is connected with the LOOP + terminal of the Hart main terminal through a first capacitor C8, and the other motionless end is connected with the collector of a first PNP transistor Q2; one end of the third resistor R18 is connected with an ADC pin, and the other end of the third resistor R18 is connected with an LOOP + terminal of the Hart main terminal; one end of the fourth resistor R19 is connected with the third resistor R18, and the other end of the fourth resistor R19 is connected with a LOOP-terminal of the Hart main terminal; one end of the sixth resistor R21 is connected with a T × AM pin through a seventh resistor R22; one end of the second capacitor C9 is connected to the output end of the first operational amplifier AS2A, and the other end is connected to the inverting input end of the first operational amplifier AS 2A.

5. The master-slave configurable Hart interface circuit of claim 4, wherein the Hart slave mode circuit comprises an eighth resistor R9, a ninth resistor R10, a tenth resistor R11, an eleventh resistor R12, a twelfth resistor R13, a thirteenth resistor R14, a fourteenth resistor R15, a first NPN transistor Q1, a third capacitor C5, a fourth capacitor C6, a fifth capacitor C7 and a second operational amplifier AS 1A; one end of the eighth resistor R9 is connected to the txas pin through the third capacitor C5, and the other end is connected to the non-inverting input terminal of the second operational amplifier AS 1A; the output end of the second operational amplifier AS1A is connected with the base of a first NPN transistor Q1, the non-inverting input end of the second operational amplifier is connected with a power supply, and the inverting input end of the second operational amplifier AS1A is grounded; the collector of the first NPN transistor Q1 is connected with the LOOP + terminal of the Hart slave terminal, and the emitter of the first NPN transistor Q1 is connected with the LOOP-terminal of the Hart slave terminal through a tenth resistor R11 and an eleventh resistor R12; one end of the tenth resistor R11 is connected to the emitter of the first NPN transistor Q1, and the other end is connected to an eleventh resistor R12; one end of the eleventh resistor R12 is grounded, and the other end of the eleventh resistor R12 is connected with a LOOP-terminal of the Hart slave terminal; one end of the fourth capacitor C6 is connected to the inverting input terminal of the second operational amplifier AS1A, and the other end is connected to the output terminal of the second operational amplifier AS 1A; one end of the ninth resistor R10 is connected with the inverting input end of the second operational amplifier AS1A, and the other end is connected with the LOOP-terminal of the Hart slave terminal through a twelfth resistor R13; one end of the thirteenth resistor R14 is connected with the DAC pin, the other end of the thirteenth resistor R14 is connected with a fourteenth resistor R15, and the other end of the fourteenth resistor R15 is connected with a twelfth resistor R13; one end of the fifth capacitor C7 is connected to the thirteenth resistor R14 and the fourteenth resistor R15, respectively, and the other end is grounded.

6. The master-slave configurable Hart interface circuit of claim 5, wherein the Hart interface circuit further comprises a Hart master-slave mode configuration circuit.

7. The master-slave configurable Hart interface circuit of claim 1, wherein the Hart signal filtering circuit employs a band pass filter.