CN211930499U

CN211930499U - Power supply starting circuit

Info

Publication number: CN211930499U
Application number: CN202020474273.0U
Authority: CN
Inventors: 成家强; 王海波; 张波; 郭颂
Original assignee: Shenzhen Urovo Technology Corp ltd
Current assignee: Shenzhen Urovo Technology Corp ltd
Priority date: 2020-04-02
Filing date: 2020-04-02
Publication date: 2020-11-13
Anticipated expiration: 2030-04-02

Abstract

The utility model relates to a power supply starting circuit, include: the device comprises a power supply input end for an external power supply, a D trigger, a processor, a key switch, a first isolation circuit, a second isolation circuit and a power supply processing circuit connected with the processor; the first end of the first isolation circuit is connected with the key switch, and the second end of the first isolation circuit is connected with the power supply processing circuit; the direct position end and the power supply end of the D trigger are connected with the power supply input end, the direct reset end and the clock input end of the D trigger are respectively connected with the processor, the reverse phase output end of the D trigger is connected with the data input end of the D trigger, and the in-phase output end of the D trigger is connected with the processor through the second isolating circuit. Implement the utility model discloses can realize not going down the electricity when the system resets and restart.

Description

Power supply starting circuit

Technical Field

The utility model relates to the field of electronic technology, more specifically say, relate to a power starting circuit.

Background

In an electronic circuit with a processor system, the POWER supply POWER-on and POWER-off control is basically implemented as shown in fig. 2, a key K1 is pressed, a control signal POWER _ EN of the POWER supply is at a high level, the whole circuit system is powered on and powered on, and the processor operates and controls an IO pin POWER _ KEEP to output a high level. POWER _ EN can continue to remain high when key K1 is released so that the circuitry can remain in constant POWER operation. When the POWER-off is needed, the processor controls the IO pin POWER _ KEEP to output a low level, and then the POWER-off is performed.

Such circuitry is sometimes required to have a reset restart function. When the processor enters a reset state, the IO pin of the processor is released to enter an initial state, and the output high level of PWR _ KEEP cannot be guaranteed, so the entire system is powered off, and the system can be powered on again only by manually pressing the key K1. Automatic reset restart cannot be realized.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in, to the above-mentioned prior art defect of prior art, a power starting circuit is provided.

The utility model provides a technical scheme that its technical problem adopted is: a power supply startup circuit is constructed comprising: the device comprises a power supply input end for an external power supply, a D trigger, a processor, a key switch, a first isolation circuit, a second isolation circuit and a power supply processing circuit connected with the processor;

the first end of the first isolation circuit is connected with the key switch, and the second end of the first isolation circuit is connected with the power supply processing circuit;

the direct position end and the power supply end of the D trigger are connected with the power supply input end, the direct reset end and the clock input end of the D trigger are respectively connected with the processor, the reverse phase output end of the D trigger is connected with the data input end of the D trigger, and the in-phase output end of the D trigger is connected with the processor through the second isolating circuit.

Preferably, the first isolation circuit comprises a first diode, an anode of the first diode is connected with the key switch, and a cathode of the first diode is connected with the power processing circuit.

Preferably, the second isolation circuit includes a second diode, an anode of the second diode is connected to the non-inverting output terminal of the D flip-flop, and a cathode of the second diode is connected to the power processing circuit.

Preferably, the utility model discloses a power starting circuit still includes filter circuit, filter circuit's one end is connected the clock input end of D flip-flop, filter circuit's the other end is connected the treater.

Preferably, the filter circuit includes a filter capacitor, a first end of the filter capacitor is connected to the processor through a resistor R3, the first end of the filter capacitor is further connected to the clock input end of the D flip-flop, and a second end of the filter capacitor is grounded.

Implement the utility model discloses a power supply starting circuit has following beneficial effect: the system can be restarted without powering down when being reset.

Drawings

The invention will be further explained with reference to the drawings and examples, wherein:

fig. 1 is a schematic circuit diagram of a power supply start circuit according to the present invention;

fig. 2 is a schematic circuit diagram of a conventional power supply start-up circuit.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, in a first embodiment of the power supply start circuit of the present invention, the power supply start circuit includes: a power input end for an external power supply, a D trigger 150, a processor 160, a key switch 120, a first isolation circuit 130, a second isolation circuit 140 and a power processing circuit 110 connected with the processor 160;

a first end of the first isolation circuit 130 is connected to the key switch 120, and a second end of the first isolation circuit 130 is connected to the power processing circuit 110;

the direct set end and the power supply end of the D flip-flop 150 are connected to the power supply input end, the direct reset end and the clock input end of the D flip-flop 150 are respectively connected to the processor 160, the inverted output end of the D flip-flop 150 is connected to the data input end of the D flip-flop 150, and the in-phase output end of the D flip-flop 150 is connected to the processor 160 through the second isolation circuit 140.

Specifically, when an external POWER input is provided at the POWER input end, the external POWER input at the POWER input end can be input to the POWER processing circuit 110 through the first isolation circuit 130 by triggering the key K1, that is, the POWER signal POWER _ EN is at a high level, the POWER processing circuit 110 POWERs on the whole circuit system inside the device, the processor 160 starts to operate, when the processor 160 operates, RESET initialization is performed first, the processor outputs the RESET signal initialization through the RESET signal output end to control the output of the D flip-flop 150, at this time, the output of the in-phase output end Q is low, and the output of the inverted output end Qn is high. The processor 160 starts to operate after being initialized, the IO pin of the processor 160 connected to the clock input terminal of the D flip-flop 150 outputs LATCH pulse, and the D flip-flop 150 outputs the inverted signal under the trigger of the pulse signal, that is, the in-phase output terminal Q outputs high, and the inverted output terminal Qn outputs low. Since the non-inverting output Q remains high, the input POWER _ EN of the POWER processing circuit 110 can remain high after the key K1 is released, so that the circuitry can remain powered. When the system needs to be powered off, the IO pin connected between the processor 160 and the clock input end of the D flip-flop 150 outputs LATCH pulse, and the output of the D flip-flop 150 is inverted again under the trigger of the pulse signal, that is, the output of the in-phase output end Q is low, and the output of the inverted output end Qn is high, at this time, because the output of the in-phase output end Q is low, the input POWER _ EN of the POWER processing circuit 110 is also low, and the POWER off of the circuit system is performed. When the reset is restarted, the processor 160 triggers the reset, although the LATCH pulse output by the IO pin connected between the clock input terminals of the processor 160 and the D flip-flop 150 is released to become the initial state, because the D flip-flop 150 has no trigger signal, the output state is kept unchanged, that is, the output of the in-phase output terminal Q is high, the output of the inverted output terminal Qn is low, the input POWER _ EN of the POWER processing circuit 110 can continue to keep the high level, and the circuit system can realize that the POWER off is not performed when the processor 160 of the system is reset. Wherein the first isolation circuit 130 and the second isolation circuit 140 are used to prevent the output of the D flip-flop 150 and the power supply output from sinking into each other when the key K1 is pressed.

In an embodiment, the first isolation circuit 130 includes a first diode, an anode of the first diode is connected to the key switch 120, and a cathode of the first diode is connected to the power processing circuit 110. Specifically, the first isolation circuit 130 may be isolated using a first diode D2.

In one embodiment, the second isolation circuit 140 includes a second diode, an anode of the second diode is connected to the non-inverting output terminal of the D flip-flop 150, and a cathode of the second diode is connected to the power processing circuit 110. Specifically, the second isolation circuit 140 may be isolated using a second diode D1.

Optionally, the power supply start circuit of the present invention further includes a filter circuit 170, one end of the filter circuit 170 is connected to the clock input terminal of the D flip-flop 150, and the other end of the filter circuit 170 is connected to the processor 160. Specifically, the output end of the IO pin of the processor 160 connected to the clock input end of the D flip-flop 150 may be connected to the filter circuit 170, and the output LATCH pulse may be filtered by the filter circuit 170.

Optionally, the filter circuit 170 includes a filter capacitor, a first end of the filter capacitor is connected to the processor 160 through a resistor R3, the first end of the filter capacitor is further connected to the clock input end of the D flip-flop 150, and a second end of the filter capacitor is grounded. Specifically, the filter circuit 170 may employ a filter capacitor C1, and the filter capacitor C1 is isolated from the output terminal of the IO pin of the processor 160 by a resistor R3.

It is to be understood that the foregoing examples merely represent preferred embodiments of the present invention, and that the description thereof is more specific and detailed, but not intended to limit the scope of the invention; it should be noted that, for those skilled in the art, the above technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

1. A power supply startup circuit, comprising: the device comprises a power supply input end for an external power supply, a D trigger, a processor, a key switch, a first isolation circuit, a second isolation circuit and a power supply processing circuit connected with the processor;

2. The power supply startup circuit of claim 1, wherein the first isolation circuit comprises a first diode, an anode of the first diode is connected to the key switch, and a cathode of the first diode is connected to the power supply processing circuit.

3. The power supply startup circuit of claim 1, wherein the second isolation circuit comprises a second diode, an anode of the second diode is connected to the non-inverting output terminal of the D flip-flop, and a cathode of the second diode is connected to the power supply processing circuit.

4. The power supply startup circuit of claim 1, further comprising a filter circuit, wherein one end of the filter circuit is connected to the clock input terminal of the D flip-flop, and the other end of the filter circuit is connected to the processor.

5. The power supply startup circuit of claim 4, wherein the filter circuit comprises a filter capacitor, a first terminal of the filter capacitor is connected to the processor through a resistor R3, the first terminal of the filter capacitor is further connected to the clock input terminal of the D flip-flop, and a second terminal of the filter capacitor is connected to ground.