CN211909012U - Mosaic image processing apparatus - Google Patents
Mosaic image processing apparatus Download PDFInfo
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- CN211909012U CN211909012U CN202020526847.4U CN202020526847U CN211909012U CN 211909012 U CN211909012 U CN 211909012U CN 202020526847 U CN202020526847 U CN 202020526847U CN 211909012 U CN211909012 U CN 211909012U
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Abstract
The utility model provides a concatenation image processing equipment, be connected with the concatenation screen that is used for showing the image, concatenation image processing equipment includes video processing server and image concatenation processing box, 4-10 image concatenation processing boxes are connected to the video processing server, image concatenation processing box connects the concatenation screen, the video processing server is used for cutting apart into 4-10 little resolution ratio signal sources with outside or local big resolution ratio signal source, and send little resolution ratio signal source to image concatenation processing box, the video processing server sends synchro command to image concatenation processing box, image concatenation processing box decodes and caches little resolution ratio signal source that the video processing server sent, accept server synchro command signal and carry out synchronous output, drive the concatenation screen according to concatenation screen parameter and show; the utility model discloses a concatenation image processing equipment can realize the point-to-point nondestructive display of image signal, can realize point-to-point concatenation.
Description
Technical Field
The utility model relates to an image processing equipment field, in particular to concatenation image processing equipment.
Background
At present, a large-screen splicing system is widely applied to various engineering fields. Generally, a full high definition 1080P or ultra high definition 4K signal source is distributed to each video splicing card or splicing box and other splicing processing ends through a central switching hub, and the splicing processing ends are compressed or amplified and displayed on a splicing screen by using an image video processing technology and an image Scaler algorithm. If a larger resolution signal needs to be acquired, the path of large resolution signal needs to be compressed into a signal resolution format which can be processed by a 1080P or 4K splicing processing end, and then the signal resolution format is distributed to each splicing processing end through an exchange hub, the splicing processing end can cut out part of video pixel information according to splicing requirements, and the content of a spliced image is amplified and displayed on a splicing screen through a video image Scaler algorithm, so that a video image seen by a user can be amplified and stretched, and the phenomenon of image blurring and unsharpness easily occurs in the conventional spliced image processing equipment.
It is therefore desirable to provide a stitched image processing apparatus that solves the above technical problems.
SUMMERY OF THE UTILITY MODEL
The utility model provides a concatenation image processing equipment, it cuts apart the processing to the high resolution ratio signal source through using the video processing server, handles the box and the point-to-point concatenation of concatenation screen is synthetic by the image concatenation again to there is the image to take place to weaken unclear and the not reasonable problem inadequately of distribution of each part in the concatenation image processing equipment among the solution prior art more.
In order to solve the technical problem, the utility model adopts the technical scheme that:
a spliced image processing device is used for image splicing processing and is connected with a spliced screen for displaying images, and comprises a video processing server and an image splicing processing box, wherein the video processing server is connected with 4-10 image splicing processing boxes, the image splicing processing boxes are connected with the spliced screen, the video processing server is used for dividing an external or local large-resolution signal source into 4-10 small-resolution signal sources and sending the small-resolution signal sources to the image splicing processing boxes, the video processing server sends a synchronization command to the image splicing processing boxes, the image splicing processing boxes decode and cache the small-resolution signal sources sent by the video processing server, receive server synchronization command signals and execute synchronization output, and the spliced screen is driven to display according to parameters of the spliced screen;
the resolution range of the large-resolution signal source is 4096X2160-5760X3840, and the resolution range of the small-resolution signal source is 1440X900-2560X 1440.
Concatenation image processing equipment in, the video processing server includes video capture card, CPU central processing unit and network data coding chip, CPU central processing unit connects respectively video capture card with network data coding chip, video capture card are used for gathering outside big signal source, CPU central processing unit is used for cutting apart the signal and sends synchronous command, network data coding chip is used for with the signal source code of small resolution ratio.
Concatenation image processing equipment in, the video processing server is provided with the hard disk, the hard disk is connected CPU, hard disk are used for saving the big resolution ratio signal source.
Concatenation image processing equipment in, the video processing server is provided with touch display screen, touch display screen connects CPU central processing unit, touch display screen are used for the demonstration and the control of server processing signal.
Concatenation image processing equipment in, the image concatenation is handled the box and is provided with the network data chip of decoding, the network data chip of decoding connects the video processing server for the small resolution ratio signal source is decoded.
Concatenation image processing equipment in, the image concatenation is handled the box and is provided with programmable logic chip, programmable logic chip connects the network data chip of decoding for logic processing.
Concatenation image processing equipment in, the image concatenation is handled the box and is provided with the code display chip, the code display chip is connected programmable logic chip with the concatenation screen for transmission signal is to the concatenation screen.
Concatenation image processing equipment in, the image concatenation is handled the box and is provided with the buffer memory chip, the buffer memory chip is connected the programmable logic chip for the quick access of data.
Concatenation image processing equipment in, the image concatenation is handled the box and is provided with synchronous clock chip, synchronous clock chip connects programmable logic chip for the timing.
Concatenation image processing equipment in, the image concatenation is handled the box and is provided with memory chip, memory chip connects programmable logic chip for the storage of data.
The utility model discloses compare in prior art, its beneficial effect is: the utility model discloses a concatenation image processing equipment, it is cut apart the processing to the large resolution ratio signal source through using the video processing server, handles the box again by the image concatenation with the point-to-point concatenation of concatenation screen is synthetic, and whole flow does not have any image amplification during, reduces the operation, and image information does not have any loss, can realize the point-to-point harmless demonstration of image signal, can realize point-to-point concatenation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments are briefly introduced below, and the drawings in the following description are only corresponding drawings of some embodiments of the present invention.
Fig. 1 is a block diagram of the spliced image processing apparatus of the present invention.
Fig. 2 is a block diagram of the spliced image processing apparatus of the present invention.
Fig. 3 is the utility model discloses a concatenation image processing equipment gathers outside large-resolution ratio signal mosaic display's flowchart.
Fig. 4 is the utility model discloses a spliced image processing equipment is to the flow chart of local big resolution ratio signal concatenation demonstration.
10, an external signal source, 20, a video processing server, 21, a video acquisition card, 22, a CPU (central processing unit), 23, a network data coding chip, 24, a hard disk, 25, a touch display screen, 30, an image splicing processing box, 31, a network data decoding chip, 32, a programmable logic chip, 33, a coding display chip, 34, a synchronous clock chip, 35, a cache chip, 36, a storage chip, 40 and a splicing screen.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.
In the present invention, the directional terms, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", "top" and "bottom", refer to the orientation of the drawings, and the directional terms are used for illustration and understanding, but not for limiting the present invention.
The terms "first," "second," and the like in the terms of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor should they be construed as limiting in any way.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
The existing spliced image processing equipment has the defects of image blurring and unclear definition.
The present invention provides a preferred embodiment of a mosaic image processing device capable of solving the above technical problems.
Please refer to fig. 1, fig. 2, fig. 3 and fig. 4, fig. 1 is the structure block diagram of the splicing image processing device, fig. 2 is the structure block diagram of the splicing image processing device of the present invention, fig. 3 is the flow chart of the splicing image processing device collecting the splicing display of the external large resolution signal, fig. 4 is the flow chart of the splicing image processing device splicing display of the local large resolution signal.
In the drawings, elements having similar structures are denoted by the same reference numerals.
The utility model provides a spliced image processing device, which is used for image splicing processing and is connected with a spliced screen 40 for displaying images, and comprises a video processing server 20 and an image splicing processing box 30, wherein the video processing server 20 is connected with 4-10 image splicing processing boxes 30, each image splicing processing box 30 is connected with a spliced screen 40, the video processing server 20 is used for dividing an external or local large-resolution signal source into 4-10 small-resolution signal sources and sending the small-resolution signal sources to the image splicing processing box 30, the video processing server 20 sends a synchronous command to the image splicing processing box 30, the image splicing processing box 30 decodes and caches the small-resolution signal sources sent by the video processing server, receives server synchronous command signals and executes synchronous output, the spliced screen 40 is driven to display according to parameters of the spliced screen, the resolution range of the large-resolution signal source is 4096X2160-5760X3840, and the resolution range of the small-resolution signal source is 1440X900-2560X 1440.
The video processing server 20 comprises a video acquisition card 21, a CPU 22, a network data coding chip 23, a hard disk 24 and a touch display screen 25, wherein the CPU 22 is respectively connected with the video acquisition card 21, the network data coding chip 23, the hard disk 24 and the touch display screen 25, the video acquisition card 21 is used for acquiring an external large signal source, the CPU 22 is used for dividing signals and sending synchronous commands, the network data coding chip 23 is used for coding a small-resolution signal source, the hard disk 24 is used for storing the large-resolution signal source, and the touch display screen 25 is used for displaying and controlling signals processed by the server.
The image splicing processing box 30 is internally provided with a network data decoding chip 31, a programmable logic chip 32, an encoding display chip 33, a synchronous clock chip 34, a cache chip 35 and a storage chip 36, wherein the programmable logic chip 32 is respectively connected with the network data decoding chip 31, the encoding display chip 33, the synchronous clock chip 34, the cache chip 35 and the storage chip 36, the network data decoding chip 31 is connected with the video processing server 20 and used for decoding a low-resolution signal source, the programmable logic chip 32 is mainly of an FPGA model and used for logic processing, the encoding display chip 33 is mainly of an HDMI model and used for transmitting signals to the splicing screen 40, the cache chip 35 is of a DDR3 model and used for fast access of data, the synchronous clock chip 34 is used for timing, and the storage chip 36 is a Flash storage chip and used for storing data.
The utility model discloses a theory of operation:
the first embodiment is as follows: referring to fig. 2 and 3, the flow of processing the external 5760X2160 high-resolution signal by the stitching image processing device of the present invention is divided into the following steps:
the method comprises the following steps: the video processing server 20 collects a path of 5760X2160 high-resolution video signal data by using a video capture card 21.
Step two: the video processing server 20 processes the path 5760X2160 of high-resolution video data into 6 pieces of 1920X1080 small-resolution data a, B, C, D, E, F by the CPU 22 according to the splicing size requirement of 2X 3.
Step three: the video processing server 20 encodes video image information a, B, C, D, E, and F by the network data encoding chip 23, and transmits the encoded video image information to the 6 image stitching processing boxes 30 through the network cable, that is, the image information data a is transmitted to the image stitching processing box No. 1 30, the image information data B is transmitted to the image stitching processing box No. 2 30, the image information data C is transmitted to the image stitching processing box No. 3 30, the image information data D is transmitted to the image stitching processing box No. 4 30, the image information data E is transmitted to the image stitching processing box No. 5 30, and the image information data F is transmitted to the image stitching processing box No. 6, so that the video image information a, B.
Step four: each image stitching processing box 30 receives the respective image information data, starts decoding and stores the decoded 3-frame image data into the cache chip 35 of the DDR3 model, and waits for the timestamp synchronization pulse signal sent by the video processing server 20.
Step five: when each image splicing processing box 30 receives the first timestamp synchronization pulse, it starts to fetch the 1 st frame of image data from the DDR3 cache chip 35, sets the output timing sequence of the FPGA programmable logic chip 32 according to the parameters of the upper computer of the video processing server 20, and drives the HDMI encoded display chip 33 to output an HDMI image data stream, which is displayed on the corresponding splicing screen 40. Meanwhile, the image stitching processing box 30 starts to decode the 4 th frame of image data and store the data into the DDR3 cache chip 35. In turn, when the image stitching processing boxes 30 receive the nth time stamp synchronizing signal, they take the nth frame image information from the DDR3 buffer chip 35 for display, decode the (N + 3) th frame image and store it in the DDR3 buffer chip 35.
Step six: and if the image splicing processing boxes 30 do not receive the time stamp synchronization pulse signals, performing the fourth waiting action until receiving the synchronization signals.
Example two: referring to fig. 2 and 4, the flow of processing the large-resolution signal of the internal 5760X2160 by the stitching image processing device of the present invention is divided into the following steps:
the method comprises the following steps: the video processing server 20 uses the system to splice the upper computer software to load a local 5760X2160 high-resolution video film source signal to be spliced and displayed.
Step two: the same as the second step in the first embodiment.
Step three: the same as the third step in the first embodiment.
Step four: all the image information data received by each image splicing processing box 30 are stored in the local storage medium Flash memory chip 36 of the image splicing processing box 30, and when the local video film source signal is needed to be used again, the image information data are directly extracted from the Flash memory chip 36 without complicated steps such as signal segmentation, coding transmission and the like.
Step five: the 3 frames of image data decoded from the video information in the Flash memory chip 36 are stored in the DDR3 cache chip 35 and wait for the timestamp synchronization pulse signal from the video processing server 20.
Step six: the same as step five in the first embodiment.
Step seven: if the image splicing processing boxes 30 do not receive the time stamp synchronization pulse signal, the waiting action of step five is performed until the synchronization signal is received.
This completes the operation of the stitched image processing apparatus of the present preferred embodiment.
The stitched image processing apparatus of the present preferred embodiment passes.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so that the scope of the present invention shall be determined by the scope of the appended claims.
Claims (10)
1. A spliced image processing device is used for image splicing processing and is connected with a spliced screen for displaying images, and is characterized by comprising a video processing server and an image splicing processing box, wherein the video processing server is connected with 4-10 image splicing processing boxes, the image splicing processing boxes are connected with the spliced screen, the video processing server is used for dividing an external or local large-resolution signal source into 4-10 small-resolution signal sources and sending the small-resolution signal sources to the image splicing processing boxes, the video processing server sends a synchronization command to the image splicing processing boxes, the image splicing processing boxes decode and cache the small-resolution signal sources sent by the video processing server, receive server synchronization command signals and execute synchronization output, and the spliced screen is driven to display according to parameters of the spliced screen;
the resolution range of the large-resolution signal source is 4096X2160-5760X3840, and the resolution range of the small-resolution signal source is 1440X900-2560X 1440.
2. The stitched image processing device of claim 1, wherein the video processing server comprises a video capture card, a CPU central processing unit and a network data coding chip, the CPU central processing unit is connected to the video capture card and the network data coding chip, respectively, the video capture card is configured to capture an external large signal source, the CPU central processing unit is configured to segment signals and send synchronization commands, and the network data coding chip is configured to code a low-resolution signal source.
3. The stitched image processing device of claim 2, wherein the video processing server is provided with a hard disk, the hard disk is connected to the CPU, and the hard disk is used for storing the high-resolution signal source.
4. The stitched image processing device of claim 2, wherein the video processing server is provided with a touch display screen, the touch display screen is connected to the CPU, and the touch display screen is used for displaying and controlling the server processing signals.
5. The spliced image processing device according to claim 1, wherein the image splicing processing box is provided with a network data decoding chip, and the network data decoding chip is connected with the video processing server and used for decoding a small-resolution signal source.
6. The spliced image processing device according to claim 5, wherein the image splicing processing box is provided with a programmable logic chip, and the programmable logic chip is connected with the network data decoding chip for logic processing.
7. The spliced image processing device according to claim 6, wherein the image splicing processing box is provided with a coding display chip, and the coding display chip is connected with the programmable logic chip and the spliced screen and used for transmitting signals to the spliced screen.
8. The spliced image processing device according to claim 6, wherein the image splicing processing box is provided with a cache chip, and the cache chip is connected with the programmable logic chip and used for fast data access.
9. The spliced image processing device according to claim 6, wherein the image splicing processing box is provided with a synchronous clock chip, and the synchronous clock chip is connected with the programmable logic chip for timing.
10. The spliced image processing device according to claim 6, wherein the image splicing processing box is provided with a memory chip, and the memory chip is connected with the programmable logic chip and used for storing data.
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| CN202020526847.4U CN211909012U (en) | 2020-04-10 | 2020-04-10 | Mosaic image processing apparatus |
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| CN202020526847.4U CN211909012U (en) | 2020-04-10 | 2020-04-10 | Mosaic image processing apparatus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112561929A (en) * | 2020-12-09 | 2021-03-26 | 威创集团股份有限公司 | Splicing screen cutting and zooming method and device, electronic device and storage medium thereof |
| CN114945100A (en) * | 2022-05-13 | 2022-08-26 | 广州市保伦电子有限公司 | Remote transmission method of high-resolution video image and background server |
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2020
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112561929A (en) * | 2020-12-09 | 2021-03-26 | 威创集团股份有限公司 | Splicing screen cutting and zooming method and device, electronic device and storage medium thereof |
| CN112561929B (en) * | 2020-12-09 | 2022-10-25 | 威创集团股份有限公司 | Splicing screen cutting and zooming method and device, electronic device and storage medium thereof |
| CN114945100A (en) * | 2022-05-13 | 2022-08-26 | 广州市保伦电子有限公司 | Remote transmission method of high-resolution video image and background server |
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