CN211855373U - Dynamic measuring circuit of array type capacitive sensor - Google Patents
Dynamic measuring circuit of array type capacitive sensor Download PDFInfo
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- CN211855373U CN211855373U CN202020507088.7U CN202020507088U CN211855373U CN 211855373 U CN211855373 U CN 211855373U CN 202020507088 U CN202020507088 U CN 202020507088U CN 211855373 U CN211855373 U CN 211855373U
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Abstract
The dynamic measurement circuit of the array type capacitive sensor comprises a single chip microcomputer, a cross gating switch array, a sine wave signal generator, a CA conversion circuit, a balance circuit, an amplitude demodulation circuit, a first multi-path selection switch, a low-pass filter circuit 2, a level shift circuit and a sampling feedback circuit. The CA conversion circuit converts the capacitance value of the capacitive unit gated by the cross gating switch array into a sine wave signal, the balance circuit counteracts the effect of the static capacitance of the capacitive unit and outputs a weak unbalanced signal which only reflects the relative change rate of the capacitance value of the capacitive unit; the amplitude demodulation circuit demodulates the amplitude of the weak unbalanced signal, and then the low-pass filter circuit 2 filters the alternating current signal and finally outputs a useful direct current signal. The utility model discloses according to different static capacitance value automatic adjustment circuit parameter, the relative variation of weak electric capacity is measured to the accuracy. The sensitivity is high, the response speed is high, the anti-interference capability is strong, and the dynamic measurement of the capacitor array with the scale reaching hundreds of channels can be realized.
Description
Technical Field
The utility model relates to a sensor measurement field, in particular to array capacitive sensor's dynamic measurement circuit.
Background
The basic principle of a capacitive sensor is to convert some physical quantity, such as displacement, area, dielectric, etc., into a capacitance and then indirectly measure the physical quantity sought by measuring the capacitance. Capacitive sensors have a very wide range of applications. Especially in the field of high-precision detection, the capacitive sensor has no alternative position. The capacitance sensor has the advantages of high sensitivity and quick response, but the measuring circuit is complex. In most cases, the capacitance of the capacitive sensor is weak, and the circuit is easily affected by parasitic parameters and environmental changes, which makes the problem more complicated.
Common weak capacitance measurement techniques include a direct current charge-discharge method, an alternating current bridge method, a V/T conversion method and a negative feedback alternating current excitation method based on an operational amplifier. The direct current charging and discharging method adopts direct current excitation, and the measurement precision is easily influenced by offset voltage drift of the amplifier. In addition, the method needs to rapidly charge and discharge the capacitor, needs an electronic switch, and is easy to influence the circuit precision by the charge injection effect of the electronic switch. The zero setting of the ac bridge method is complicated, and is easily affected by the parasitic capacitance of the circuit, and a complicated shielding measure is required in the actual implementation process. The method is difficult to measure the weak change of the small capacitance. The V/T conversion method is used for measuring capacitance values by measuring the charge-discharge time of capacitors, and the measurement precision is easily influenced by the direct-current voltage drift of a circuit and the injection charge of an electronic switch like a direct-current charge-discharge method; from part of published documents, the circuit with the highest measurement accuracy in the actual application of weak capacitance detection is a negative feedback alternating current excitation method based on an operational amplifier. The method has high resolution and strong parasitic capacitance resistance. In addition, a high-voltage bilateral excitation detection method needs high-frequency high-voltage excitation signals, is only used for specific objects and occasions, and has more limiting conditions.
In the capacitance detection method described above, it is mostly used for static measurement of capacitance, however, in many applications it is necessary to measure the dynamic change of capacitance with time. This has the requirement of response speed in addition to the requirement of precision for the circuit; for array capacitive sensors, the circuit is also required to have multi-channel measurement capability.
The electronic palpation technology is a technology for diagnosing hardness information of internal tissues of the mammary gland by utilizing pressure feedback and plane distribution thereof, and can replace the traditional manual palpation to a certain extent. The sensor used in this technique is a capacitive array probe, the structure of which is shown in fig. 1. Narrow metal sheets are distributed in parallel in the horizontal and vertical directions of the sensitive plane of the probe, and a very thin elastic insulating medium is filled between the two groups of metal sheet planes. A small parallel plate capacitor can be formed at the intersection of two parallel planes, each of which is chosen to be a metal foil, as shown in figure 2.
The force applied to the sensitive surface of the probe can compress the insulating medium, so that the capacitance value is changed. The pressure at the intersection can be measured by measuring the amount of change in the capacitance. Under the assumption that the insulating material is fully elastic and ideal parallel plate capacitance, it can be deduced that the pressure at the crossover point is proportional to the relative rate of change of capacitance of the crossover capacitance:
C0is the initial capacitance (also called bulk capacitance or static capacitance value) at the crossover point, Δ C is the capacitance change under pressure, E is the young's modulus of the insulating medium, and p is the pressure at the crossover point. Requiring circuit output proportional to the relative rate of change of capacitance
Rather than static capacitance value C0。
In practical application, the static capacitance value C is small because the area at the intersection point is small0Also relatively small, on the order of pF, this capacitance value is much smaller than the parasitic capacitance of the cable. In addition, due to material and other factors, the strain of the insulating medium is also very small, which results in a very small change in capacitance Δ C, on the order of magnitude below fF.
Because of the defects of the probe manufacturing process, the consistency among the capacitance units is difficult to ensure, and the basic capacitance distribution among probe batches has certain difference. In order to obtain more consistent measurement performance, the circuit is required to have stronger self-adaptability to the sensor capacitance.
To achieve higher spatial resolution, it is desirable to have the capacitor arrays be as dense as possible. This requires the circuit to be able to have the capability of fast switching of multiple channels. In the actual diagnosis process, the pressure distribution image is required to be presented in a dynamic form, so that the circuit is required to have higher response speed. Conventional capacitive sensing techniques are far from meeting the requirements of the above applications.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model aims at disclosing a dynamic measurement circuit of array capacitive sensor.
The utility model aims at realizing through the following technical scheme:
the dynamic measurement circuit of the array type capacitive sensor comprises a single chip microcomputer, a cross gating switch array, a sine wave signal generator, a CA conversion circuit, a balance circuit, an amplitude demodulation circuit, a first multi-path selection switch, a second low-pass filter circuit, a level shift circuit and a sampling feedback circuit; the cross gating switch array gates a capacitor unit of the array capacitor sensor to be tested, and the output end of the cross gating switch array is connected with the first input end of the CA conversion circuit; the four input ends of the sine wave signal generator are respectively input with a first square wave signal DS0, a second square wave signal DS1, a first analog signal AS0 and a second analog signal AS1 which are output by the singlechip, the first output end of the sine wave signal generator is connected with the second input end of the CA conversion circuit, and the second output end of the sine wave signal generator is connected with the second input end of the balancing circuit; the first input end of the balancing circuit is connected with the output end of the CA conversion circuit, and the output end of the balancing circuit is connected with the first input end of the amplitude demodulation circuit; the second input end of the amplitude demodulation circuit is connected with the square wave signal output port of the single chip microcomputer; the output end of the amplitude demodulation circuit is connected to the first input end of the second low-pass filter circuit through a first multi-path selection switch; the level shift circuit outputs a direct current shift voltage signal to a second input end of the second low-pass filter circuit, and the second low-pass filter circuit finally outputs a useful direct current signal to an on-chip analog-to-digital converter of the single chip microcomputer; the sampling feedback circuit respectively gates sine wave signals output by a first output end of the sine wave signal generator, an output end of the CA conversion circuit, the balancing circuit and the amplitude demodulation circuit, then the sine wave signals sequentially pass through the first multi-path selection switch and the second low-pass filter circuit to obtain sine wave amplitude signals, and the sine wave amplitude signals are output to an on-chip analog-to-digital converter of the single chip microcomputer.
Furthermore, the balancing circuit comprises a second fixed gain device and an adding circuit, wherein the input end of the second fixed gain device is used as the second input end of the balancing circuit, the first input end of the adding circuit is used as the first input end of the balancing circuit, the output end of the second fixed gain device is connected with the second input end of the adding circuit, and the output end of the adding circuit is used as the output end of the balancing circuit.
Further, the amplitude demodulation circuit comprises a first fixed gain device, a first low-pass filter circuit and a synchronous demodulation circuit; the input end of the first fixed gain device is used as the first input end of the amplitude demodulation circuit, the output end of the first fixed gain device is connected to the first input end of the synchronous demodulation circuit after passing through the first low-pass filter circuit, the second input end of the synchronous demodulation circuit is used as the second input end of the amplitude demodulation circuit, and the output end of the synchronous demodulation circuit is used as the output end of the amplitude demodulation circuit.
Furthermore, the sampling feedback circuit comprises a second multi-path selection switch and a root-mean-square circuit, wherein the input end of the second multi-path selection switch is used as the input end of the sampling feedback circuit, the output end of the second multi-path selection switch is connected with the input end of the root-mean-square circuit, and the output end of the root-mean-square circuit is used as the output end of the sampling feedback circuit.
Furthermore, the cross gating switch array comprises two groups of switch arrays, m + n input ends and two output ends; the first group of switch arrays comprises m groups of switches, each group of switches comprises two single-pole single-throw switches, one end of a first single-pole single-throw switch of the ith group of switches is connected with one end of a second single-pole single-throw switch of the ith group of switches and serves as one of m + n input ends of the cross gating switch array, the other end of the first single-pole single-throw switch of the ith group of switches is connected to one output end of the cross gating switch array, and the other end of the second single-pole single-throw switch of the ith group of switches is grounded; the second group of switch arrays comprises n groups of switches, each group of switches comprises two single-pole single-throw switches, one end of a first single-pole single-throw switch of the jth group of switches is connected with one end of a second single-pole single-throw switch of the jth group of switches and serves as the other one of m + n input ends of the cross gate switch array, the other end of the first single-pole single-throw switch of the jth group of switches is connected to the other output end of the cross gate switch array, and the other end of the second single-pole single-throw switch of the jth group of switches is grounded; wherein m is more than or equal to 1, n is more than or equal to 1, i is more than or equal to 1 and less than or equal to m, and j is more than or equal to 1 and less than or equal to n.
Furthermore, the cross gating switch array comprises two groups of switch arrays, m + n input ends and two output ends; the first group of switch arrays comprises m single-pole double-throw switches, the common end of the ith single-pole double-throw switch is used as one of m + n input ends of the cross gating switch array, the first end of the ith single-pole double-throw switch is connected to one output end of the cross gating switch array, and the second end of the ith single-pole double-throw switch is grounded; the second group of switch array comprises n single-pole double-throw switches, the common end of the jth single-pole double-throw switch is used as the other of the m + n input ends of the cross gate switch array, the first end of the jth single-pole double-throw switch is connected to the other output end of the cross gate switch array, and the second end of the jth single-pole double-throw switch is grounded; wherein m is more than or equal to 1, n is more than or equal to 1, i is more than or equal to 1 and less than or equal to m, and j is more than or equal to 1 and less than or equal to n.
Furthermore, the sine wave signal generator comprises two sine wave generating circuits; the sine wave generating circuit comprises an amplitude control circuit, a single-pole double-throw electronic switch circuit and a filter; the input end of the amplitude control circuit inputs an analog signal output by an on-chip DAC of the singlechip, the output end of the amplitude control circuit is connected with one input end of the single-pole double-throw electronic switch circuit, the other input end of the single-pole double-throw electronic switch circuit is grounded, the common end of the single-pole double-throw electronic switch circuit is connected with the input end of the filter, and the output end of the filter outputs a sine wave.
Further, the CA conversion circuit comprises a first Capacitor (CR), a second capacitor (C59), a first operational amplifier (U7-A) and a first resistor (R32); one end of the first Capacitor (CR) is used as a second input end of the CA conversion circuit, and the other end of the first Capacitor (CR) is respectively connected with one end of the second capacitor (C59), one end of the first resistor (R32) and the inverting input end of the first operational amplifier (U7-A); the other end of the second capacitor (C59) and the non-inverting input end of the first operational amplifier (U7-A) are grounded; the output end of the first operational amplifier (U7-A) is connected with the other end of the first resistor (R32) and then used as the output end of the CA conversion circuit; both ends of the first resistor (R32) serve as first input terminals of the CA conversion circuit.
Further, the synchronous demodulation circuit comprises a second resistor (R49), a third resistor (R50), a fourth resistor (R51), a fifth resistor (R52), a sixth resistor (R53), a seventh resistor (R66), an eighth resistor (R67), a ninth resistor (R68), a third capacitor (C82), a fourth capacitor (C119), a second single-pole double-position switch (U11-B), a second operational amplifier (U10-A) and a third operational amplifier (U10-B); one end of a second resistor (R49) is connected with the first end of a second single-pole double-position switch (U11-B) and is used as the first input end of the synchronous demodulation circuit; the second end of the second single-pole double-position switch (U11-B) is grounded, and the common end of the second single-pole double-position switch (U11-B) is connected with one end of a fourth resistor (R51); the other end of the second resistor (R49) is respectively connected with one end of a sixth resistor (R53) and the inverting input end of the second work operational amplifier (U10-A), and the other end of the sixth resistor (R53) is grounded; the other end of the fourth resistor (R51) is connected with the non-inverting input end of the second operational amplifier (U10-A), and the output end of the second work operational amplifier (U10-A) is connected with the inverting input end of the third operational amplifier (U10-B) through a seventh resistor (R66); the third capacitor (C82) and the third resistor (R50) are connected in parallel and then are connected between the inverting input end and the output end of the second operational amplifier (U10-A); a ninth resistor (R68) is connected between the non-inverting input of the third operational amplifier (U10-B) and ground; the fourth capacitor (C119) and the eighth resistor (R67) are connected in parallel and then connected between the inverting input end and the output end of the third operational amplifier (U10-B); the output end of the third operational amplifier (U10-B) is used as the output end of the synchronous demodulation circuit after passing through a fifth resistor (R52).
Further, the RMS circuit includes a first voltage follower (U15-A), a tenth resistor (R69), an eleventh resistor (R70), a twelfth resistor (R71), a thirteenth resistor (R72), a fifth capacitor (C148), a fourth operational amplifier (U15-B), a first diode (D9) and a second diode (D10); the sine wave signal gated by the second multi-way selection switch is input to one end of a tenth resistor (R69) after passing through a first voltage follower (U15-A), and the other end of the tenth resistor (R69) is connected with the inverting input end of a fourth operational amplifier (U15-B); an eleventh resistor (R70) is connected between the non-inverting input of the fourth operational amplifier (U15-B) and ground; the output end of the fourth operational amplifier (U15-B) is connected with the anode of the second diode (D10); the fifth capacitor (C148) and the twelfth resistor (R71) are connected in parallel and then connected between the inverting input end and the output end of the fourth operational amplifier (U15-B); the anode of the first diode (D9) is connected with the inverting input end of the fourth operational amplifier (U15-B), and the cathode of the first diode (D9) is connected with the output end of the fourth operational amplifier (U15-B); the cathode of the second diode (D10) is connected with one end of a thirteenth resistor (R72), and the other end of the thirteenth resistor (R72) is used as the output end of the root mean square circuit.
The utility model discloses an array capacitive sensor's dynamic measurement circuit has the automatic zero setting function, can make circuit parameter reach the optimal configuration according to the different initial capacitance value automatic adjustment circuit parameters of sensor unit, accurately measures the variable quantity of weak electric capacity. The utility model provides a detection problem under the weak sensor capacitor array, sensitivity is high, and response speed is fast, can realize dynamic measurement.
Drawings
FIG. 1 is a schematic diagram of an array capacitive sensor;
FIG. 2 is a schematic diagram of a plate capacitor formed by two crossed foil electrodes in the array type capacitive sensor;
fig. 3 is a block diagram of a dynamic measurement circuit of the array type capacitive sensor of the present invention;
fig. 4 is a circuit schematic of a first embodiment of a cross-gated switch array of the present invention;
fig. 5 is a circuit schematic of a second embodiment of a cross-gate switch array according to the present invention;
fig. 6 is a circuit block diagram of the sine wave signal generator of the present invention;
fig. 7 is a schematic circuit diagram of the sine wave signal generator of the present invention;
fig. 8 is a schematic circuit diagram of a CA conversion circuit according to the present invention;
fig. 9 is a schematic circuit diagram of the synchronous demodulation circuit of the present invention;
fig. 10 is a schematic circuit diagram of a root-mean-square circuit according to the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
The connection of the utility model refers to the electrical connection, which can be the direct electrical connection or the indirect electrical connection through a certain device.
The utility model discloses an used electric capacity-voltage conversion method is based on the electric capacity measurement's alternating current negative feedback method to carry out a large amount of improvements on this basis, make the direct output of circuit be directly proportional to the direct current voltage signal of the relative rate of change of electric capacity. Firstly, a gated capacitor unit in the array type capacitor sensor is accessed to a dynamic measurement circuit through a cross gating switch array, and weak capacitance variation of the gated capacitor unit is modulated into amplitude of an excitation sine wave signal. In order to remove the effect of the static capacitance of the sensor unit, another sine wave with adjustable amplitude and phase is generated, and the waveform of the sine wave just offsets the effect caused by the static capacitance of the gated capacitor unit. This process is called "zeroing", the circuit is called "balancing circuit", and the sine wave with adjustable amplitude and phase is called "balancing signal". After the zeroing process is completed, the control quantity of the balance signal is stored by the MCU. During measurement, when the capacitance value of the gated capacitor unit of the array capacitor sensor changes, the balance circuit outputs a sine wave with the amplitude proportional to the capacitance change rate of the gated capacitor unit. The amplitude of the sine wave is solved by the synchronous demodulation circuit, and the sine wave is output as a direct current voltage signal which is in direct proportion to the relative change rate of the capacitance of the switched-on capacitance unit after low-pass filtering.
The block diagram of the dynamic measurement circuit of the array type capacitive sensor of the utility model is shown in fig. 3, and comprises a single chip microcomputer MCU, a cross gating switch array, a sine wave signal generator, a CA conversion circuit, a balance circuit, an amplitude demodulation circuit, a 2:1 multi-way selection switch, a low-pass filter circuit 2, a level shift circuit and a sampling feedback circuit.
The MCU has an on-chip analog-to-digital converter ADC0, a control BUS interface BUS0/BUS1/BUS2, an IO output port CH0/CH1/CH2, and an on-chip digital-to-analog converter DAC0/DAC 1. The MCU outputs a control BUS signal DS3 through a control BUS interface BUS0, a control BUS signal DS4 through a control BUS interface BUS1, and a control BUS signal DS5 through a control BUS interface BUS 2. The MCU outputs a square wave signal DS2 through the square wave signal output port CH 2. The MCU outputs a square wave signal DS0 through an IO port CH0, outputs a square wave signal DS1 through an IO port CH1, outputs an analog signal AS0 through an on-chip DAC0 and outputs an analog signal AS1 through an on-chip DAC1, and the MCU controls the sine wave signal generator through DS0/DS1/AS0/AS 1. The sine wave signal generator is provided with a first input end, a second input end, a third input end, a fourth input end, a first output end and a second output end. The CA conversion circuit has a first input terminal, a second input terminal, and an output terminal. The balancing circuit has a first input terminal, a second input terminal, and an output terminal. The amplitude demodulation circuit has a first input terminal, a second input terminal, and an output terminal. The sampling feedback circuit has an input and an output.
The cross gating switch array gates the capacitor unit of the array capacitor sensor to be tested, and the output end of the cross gating switch array is connected with the first input end of the CA conversion circuit. The four input ends of the sine wave signal generator are respectively input with a first square wave signal DS0, a second square wave signal DS1, a first analog signal AS0 and a second analog signal AS1 which are output by the MCU, the first output end of the sine wave signal generator is connected with the second input end of the CA conversion circuit, and the second output end of the sine wave signal generator is connected with the second input end of the balancing circuit. The first input end of the balancing circuit is connected with the output end of the CA conversion circuit, and the output end of the balancing circuit is connected with the first input end of the amplitude demodulation circuit. The second input end of the amplitude demodulation circuit inputs the third-party wave signal DS2 output by the MCU. The output of the amplitude demodulation circuit is connected to a first input of the low-pass filter circuit 2 via a 2:1 multiplexer switch. The level shift circuit outputs a dc offset voltage signal to the second input terminal of the low pass filter circuit 2, and the low pass filter circuit 2 finally outputs a useful dc signal to the on-chip ADC0 of the MCU. The sampling feedback circuit respectively gates sine wave signals output by the first output end of the sine wave signal generator, the output end of the sampling CA conversion circuit, the balancing circuit and the amplitude demodulation circuit, then the sine wave signals sequentially pass through the 2:1 multi-way selection switch and the low-pass filter circuit 2 to obtain sine wave amplitude signals, and the sine wave amplitude signals are output to an on-chip analog-to-digital converter ADC0 of the MCU.
The balance circuit comprises a fixed gain device K2 and an adding circuit, wherein the input end of the fixed gain device K2 is used as the second input end of the balance circuit, the first input end of the adding circuit is used as the first input end of the balance circuit, the output end of the fixed gain device K2 is connected with the second input end of the adding circuit, and the output end of the adding circuit is used as the output end of the balance circuit.
The amplitude demodulation circuit comprises a fixed gain device K1, a low-pass filter circuit 1 and a synchronous demodulation circuit. The input end of the fixed gain device K1 is used as the first input end of the amplitude demodulation circuit, the output end of the fixed gain device K1 is connected to the first input end of the synchronous demodulation circuit after passing through the low-pass filter circuit 1, the second input end of the synchronous demodulation circuit is used as the second input end of the amplitude demodulation circuit, and the output end of the synchronous demodulation circuit is used as the output end of the amplitude demodulation circuit.
The sampling feedback circuit comprises a 4:1 multi-path selection switch and a root-mean-square circuit, wherein the input end of the 4:1 multi-path selection switch is respectively connected with the first output end of the sine wave signal generator, the output end of the CA conversion circuit, the output end of the fixed gain device K2 and the output end of the low-pass filter circuit 1, and the sine wave signals of the output ends are collected. The output end of the multi-path selection switch of 4:1 is connected with the input end of the root-mean-square circuit, and the output end of the root-mean-square circuit is used as the output end of the sampling feedback circuit.
One capacitor unit in the cross gating switch array gating array type capacitor sensor comprises m + n input ends which are respectively connected to a first group of metal sheets and a second group of metal sheets in the array type capacitor sensor; including two outputs (X and Y). m + n represents the sum of the number of the first group of metal sheets and the second group of metal sheets in the array type capacitive sensor, m is larger than or equal to 1, and n is larger than or equal to 1. The metal sheets in each group are on the same horizontal plane and are parallel to each other, and the metal sheets between the two groups are vertically distributed in space. And a capacitor unit is formed at the position where any one metal sheet in each group is vertically intersected with any one metal sheet in the other group in space. The circuit structure of the cross gate switch array has two embodiments.
A first embodiment of a cross-gated switch array is shown in fig. 4 and includes two sets of switch arrays. The first group of switch arrays comprises m groups of switches, each group of switches comprises two single-pole single-throw switches, one end of a first single-pole single-throw switch of the ith group of switches and one end of a second single-pole single-throw switch of the ith group of switches are connected to one metal sheet of the first group of metal sheets, the other end of the first single-pole single-throw switch of the ith group of switches is connected to one output end of the cross gate switch array, and the other end of the second single-pole single-throw switch of the ith group of switches is grounded; wherein i is more than or equal to 1 and less than or equal to m. The second group of switch array comprises n groups of switches, each group of switches comprises two single-pole single-throw switches, one end of a first single-pole single-throw switch of the jth group of switches and one end of a second single-pole single-throw switch of the jth group of switches are connected to one metal sheet of the second group of metal sheets, the other end of the first single-pole single-throw switch of the jth group of switches is connected to the other output end of the cross gate switch array, and the other end of the second single-pole single-throw switch of the jth group of switches is grounded; wherein j is more than or equal to 1 and less than or equal to n. Under the control of a control bus signal DS5 of the MCU, the cross gate switch array closes a first single-pole single-throw switch of the ith group of switches and opens a second single-pole single-throw switch of the ith group of switches. The first single-pole single-throw switch of the other groups of switches except the ith group of switches in the first group of switch arrays is opened, and the second single-pole single-throw switch of the other groups of switches except the ith group of switches is closed. I.e. gating the ith foil in the first set of foils is achieved. Similarly, gating the jth metal plate in the second set of metal plates may also be implemented. Therefore, the gating of the capacitance unit formed at the vertical intersection of the ith metal sheet and the jth metal sheet is realized.
A second embodiment of a cross-gated switch array is shown in fig. 5, and includes two sets of switch arrays. The first group of switch arrays comprises m single-pole double-throw switches, the common terminal of the ith single-pole double-throw switch is connected to one metal sheet in the first group of metal sheets, the first terminal of the ith single-pole double-throw switch is connected to one output terminal of the cross-gate switch array, and the second terminal of the ith single-pole double-throw switch is grounded; wherein i is more than or equal to 1 and less than or equal to m. The second group of switch array comprises n single-pole double-throw switches, the common terminal of the jth single-pole double-throw switch is connected to one metal sheet of the second group of metal sheets, the first terminal of the jth single-pole double-throw switch is connected to the other output terminal of the cross gate switch array, and the second terminal of the jth single-pole double-throw switch is grounded; wherein j is more than or equal to 1 and less than or equal to n. Under the control of a control bus signal DS5 of the MCU, the cross gate switch array closes the first end and the common end of the ith single-pole double-throw switch, and closes the second ends and the common end of the other single-pole double-throw switches in the first group of switch arrays. I.e. gating the ith foil in the first set of foils is achieved. Similarly, gating the jth metal plate in the second set of metal plates may also be implemented. Therefore, the gating of the capacitance unit formed at the vertical intersection of the ith metal sheet and the jth metal sheet is realized.
The sine wave signal generator is used for generating two paths of sine wave signals AS2 and AS9 under the control of DS0/DS1/AS0/AS1 output by the MCU. The circuit block diagram of the sine wave signal generator is shown in fig. 6, and comprises two sine wave generating circuits, wherein each sine wave generating circuit comprises an amplitude control circuit, a single-pole double-throw electronic switch circuit and a filter; the input end of the amplitude control circuit inputs an analog signal output by an on-chip DAC of the MCU, the output end of the amplitude control circuit is connected with one input end of the single-pole double-throw electronic switch circuit, the other input end of the single-pole double-throw electronic switch circuit is grounded, the common end of the single-pole double-throw electronic switch circuit is connected with the input end of the filter, and the output end of the filter outputs a sine wave. The control end of the single-pole double-throw electronic switch circuit is controlled by a square wave signal output by the single chip microcomputer.
The principle is illustrated by taking fig. 6 as an example: the analog signal AS0 or AS1 output by the MCU controls the amplitude control circuit to generate a controlled DC voltage source which is periodically cut off by a square wave signal DS0 or DS1 with 50% duty ratio output by the MCU, so AS to generate an amplitude controlled square wave, and the phase of the square wave determines the phase of the sine wave. After the controlled square wave enters the filter, 3-order and more than 3-order harmonics are filtered out, and only fundamental frequency sine wave signals are reserved. The amplitude and phase of the sine wave signal are controlled by the MCU. The filter may be an active or passive low pass filter circuit or a band pass filter with a center frequency at the fundamental frequency.
The sine wave signal generator is illustrated in fig. 7, which is a circuit for generating a sine wave. The amplitude control circuit comprises voltage followers U1-A and U1-B, a resistor R1, a capacitor C1 and a capacitor C3. The single-pole double-throw electronic switch circuit comprises a resistor R11, a triode Q1, a resistor R2 and a capacitor C2. An analog signal DAC0 output by the MCU is connected to one end of a resistor R3 after passing through a voltage follower U1-A, and the other end of the resistor R3 is connected to the filter after passing through a voltage follower U1-B. The single chip microcomputer MCU outputs a square wave signal CH0 to one end of a resistor R11, and the other end of R11 is connected with one end of a capacitor C2, one end of a resistor R2 and a base electrode of a triode Q1; the other end of the capacitor C2, the other end of the resistor R2 and an emitter of the triode Q1 are grounded; the collector of the triode Q1 is connected to the other end of the resistor R3 through the resistor R1; the capacitors C1 and C3 are connected in parallel, one end of each capacitor is connected to the other end of R3, and the capacitors C1 and C3 are connected in parallel, and the other end of each capacitor is grounded.
The working principle of fig. 7 is: the on-chip DAC of the MCU outputs a controlled direct-current voltage source (namely an analog signal AS0) through a DAC0 port, the direct-current voltage source outputs to the resistor 3 after passing through a voltage follower U1-A, meanwhile, a square wave signal DS0 with the duty ratio of 50% is output from a CH0 port of the single chip microcomputer, and the on and off of the triode Q1 are periodically controlled. When Q1 is turned on, the controlled DC voltage source output by MCU is connected to ground through Q1, and when Q1 is turned off, the controlled DC voltage source output by MCU is connected to filter through voltage follower U1-B.
The circuit schematic diagram of the CA conversion circuit is shown in FIG. 8, and comprises a capacitor CR, a capacitor C59, an operational amplifier U7-A and a resistor R32. One end of the CR is connected with a sine wave signal AS2 output by the signal generator AS a second input end of the CA conversion circuit, and the other end of the CR is respectively connected with one end of a capacitor C59, one end of a resistor R32 and an inverting input end of an operational amplifier U7-A. The other end of the capacitor C59 and the non-inverting input of the operational amplifier U7-A are grounded. The output end of the operational amplifier U7-A is connected with the other end of the resistor R32 and then used AS the output end of the CA conversion circuit to output a sine wave signal AS 3. Two ends of the resistor R32 are connected to the output end of the cross gate switch array as the first input end of the CA conversion circuit. Where CX is the equivalent capacitance of the sensor cell gated by the cross-gated switch array and CR is the reference capacitance.
The circuit schematic diagram of the synchronous demodulation circuit is shown in fig. 9 and comprises a resistor R49, a resistor R50, a resistor R51, a resistor R52, a resistor R53, a resistor R66, a resistor R67, a resistor R68, a capacitor C82, a capacitor C119, a single-pole double-position switch U11-B and operational amplifiers U10-A and U10-B. One end of the resistor R49 is connected with the first end of the single-pole double-position switch U11-B and is used AS the first input end of the synchronous demodulation circuit to input the sine wave signal AS 5. The second end of the U11-B is grounded, and the common end of the U11-B is connected with one end of the resistor R51. U11-B is controlled by square wave signal DS2 output by the MCU and is switched between the first end and the second end. The other end of the resistor R49 is connected with one end of the resistor R53 and the inverting input end of the operational amplifier U10-A respectively, and the other end of the resistor R53 is grounded. The other end of the resistor R51 is connected with the non-inverting input end of the operational amplifier U10-A. The output of the operational amplifier U10-A is connected to the inverting input of the operational amplifier U10-B through a resistor R66. The capacitor C82 and the resistor R50 are connected in parallel and then connected between the inverting input end and the output end of the operational amplifier U10-A. The resistor R68 is connected between the non-inverting input of the operational amplifier U10-B and ground. The capacitor C119 and the resistor R67 are connected in parallel and then connected between the inverting input terminal and the output terminal of the operational amplifier U10-B. The output end of the operational amplifier U10-B is used AS the output end of the synchronous demodulation circuit to output a sine wave signal AS6 after passing through a resistor R52.
The RMS circuit does not include a low-pass filter function, and the output of the RMS circuit and the output of the synchronous demodulation circuit multiplex the same low-pass filter circuit in a time-sharing manner, so that the cost of the circuit is reduced. The schematic diagram of the RMS circuit is shown in FIG. 10 and includes a voltage follower U15-A, a resistor R69, a resistor R70, a resistor R71, a resistor R72, a capacitor C148, an operational amplifier U15-B, a diode D9, and a diode D10. The sine wave signal gated by the multi-way selection switch of 4:1 is input to one end of a resistor R69 after passing through a voltage follower U15-A, and the other end of the resistor R69 is connected with the inverting input end of an operational amplifier U15-B. Resistor R70 is connected between the non-inverting input of operational amplifier U15-B and ground. The output terminal of the operational amplifier U15-B is connected to the anode of the diode D10. The capacitor C148 and the resistor R71 are connected in parallel and then connected between the inverting input terminal and the output terminal of the operational amplifier U15-B. The anode of the diode D9 is connected to the inverting input terminal of the operational amplifier U15-B, and the cathode of the diode D9 is connected to the output terminal of the operational amplifier U15-B. The cathode of the diode D10 is connected to one end of the resistor R72, and the other end of the resistor R72 outputs a sine wave signal AS13 AS the output end of the rms circuit.
With reference to fig. 3 to 10, the operation principle of the dynamic measurement circuit of the present invention is described in detail as follows:
the cross gating switch array gates one capacitor unit in the array capacitor sensor under the control of the DS5 bus of the MCU, and the gated capacitor unit is connected to the first input end of the CA conversion circuit. As shown in fig. 4 and 5, in the circuit, X0, X1, X2, X3 are.. times.xn-1, Y0, Y1, Y2, Y3 are.. times.yn-1 are sensor array electrodes (probe cable access signals), and X, Y is an access point of the CA conversion circuit.
The MCU outputs DS0/DS1/AS0/AS1 to the sine wave signal generator, and the sine wave signal generator generates two sine wave signals AS2 and AS9 by two sine wave generating circuits under the control of DS0/DS1/AS0/AS 1. The operation principle of the sine wave generating circuit has been described above and will not be described in detail here. The sine wave signal AS2 is input to the CA conversion circuit, and the sine wave signal AS9 is input to the fixed booster K2.
The sine wave signal AS2 may be functionally represented AS:
fAS2＝A0sin (ω t) equation (2)
A0Is the amplitude of the sine wave, ω is the angular frequency and the phase is defined as 0.
The sine wave signal AS10 is controlled in amplitude and phase (relative to the phase of signal AS 2) by the MCU.
The CA conversion circuit modulates the variation in the capacity of the capacitive cells gated by the cross-gated switch array to the amplitude variation of the sine wave signal AS 3. The circuit is based on a classical ac method capacitance measuring circuit, with the difference that the equivalent capacitance of the gated capacitive cell is arranged on the feedback loop. As shown in fig. 8, CX is an equivalent capacitance of the sensor capacitance unit turned on, and CR is a reference capacitance.
Under certain approximate conditions, the sine wave signal AS3 output by the CA conversion circuit is expressed AS:
C0is the initial capacitance (also called bulk capacitance or static capacitance) of the gated capacitive unit, Δ C is the capacitance variation, and Cr is the reference capacitance. When Δ C is 0, fAS3Is the sine wave output caused by the static capacitance of the selected capacitive cell.
After passing through the fixed booster K2, the sine wave signal AS9 outputs a sine wave signal AS10, the sine wave signal AS10 is equal in amplitude and opposite in phase to the sine wave signal generated by the static capacitor of the turned-on capacitor unit, and therefore the process of generating the sine wave signal AS10 is AS follows:
when the array type capacitive sensor is in a completely static state, the amplitude and the phase of the AS9 output by the signal generator are controlled according to the control signal of the MCU continuously adjusted by a certain algorithm, so that the amplitude of the sine wave signal AS5 approaches to 0.
This time is:
this process may be referred to as a zeroing process. After zeroing is complete, the MCU will store the controlled circuit parameters. This parameter is then loaded before each measurement is taken, leaving the circuit in a zeroing completed state.
When the capacitance value of the gated capacitor cell changes (relative to the static value) after the zero-setting parameter is applied, the amplitude of the signal AS3 slightly changes relative to the static value. At this time, the AS3 signal is influenced by two contributions, the capacitance change amount of the on-capacitance cell and the static capacitance. The contribution of the static capacitance is cancelled by the sinusoidal new AS10 by way of addition (via the addition circuit). Therefore, the purpose of the adder circuit is to remove the output of the static capacitance of the turned-on capacitance unit so that only the capacitance change amount is included in the output. The addition circuit may be implemented by an inverting proportional adder.
The adder output passes through a fixed gain K1 and then through a low pass filter circuit 1. The low-pass filter circuit 1 filters part of noise carried in the weak signal. After passing through the low-pass filter circuit 1, a sine wave AS5 related to the capacitance variation is obtained, and the expression of the sine wave signal AS5 is:
wherein K1A fixed gain value set for the fixed gain circuit K1.
The two input ends of the synchronous demodulation circuit respectively input a sine wave signal AS5 and a square wave signal DS 2. DS2 controls the connection of single-pole double-throw electronic switch U11-B, changes the gain of the circuit. The electronic switches are periodically switched so that the circuit has two stable states, which result in the same value of the circuit gain but opposite sign. The amplifier U10-B amplifies and filters the output as appropriate. This effect is equivalent to multiplying the sine wave signal AS5 with a symmetrical square wave signal AS 2. After an output AS6 of the synchronous demodulation circuit passes through a low-pass filter circuit 2 to filter an alternating current signal, a direct current voltage signal proportional to the relative change rate of the capacitance of the sensor unit is obtained, and the voltage value is:
vzero is the zero set residual error. Half of the on-chip ADCs can only detect positive voltages. In order to ensure that the useful signal U can be detected effectively, a small dc signal AS12 is superimposed artificially on the level shift circuit at the second input of the low-pass filter circuit 2, and finally the output AS8 of the low-pass filter circuit 2 is represented AS:
voffset is the smaller dc signal AS12 output by the level shifting circuit.
A4: 1 multi-way selection switch and a root-mean-square circuit are used for zeroing the circuit. During zeroing, the amplitudes of AS1, AS2, AS6, and AS7 are time-shared by the rms circuit. The operating principle of the root-mean-square circuit is as follows: the operational amplifier U15-B constitutes an in-phase precision half-wave rectifier circuit such that the output signal contains only the positive half cycle of the input sinusoidal signal, while the negative half cycle is forced to 0. The half-wave signal is low-pass filtered to obtain a direct current signal, and the voltage value of the direct current signal is in direct proportion to the amplitude of the sine wave input by the root-mean-square circuit, so that the amplitude (or root-mean-square, which are in direct proportion) of the input signal can be acquired.
The above description is for illustrative purposes only and is not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. that do not depart from the spirit and principles of the present invention should be construed as within the scope of the present invention.
Claims (10)
1. The dynamic measurement circuit of the array type capacitive sensor is characterized by comprising a single chip microcomputer, a cross gating switch array, a sine wave signal generator, a CA conversion circuit, a balance circuit, an amplitude demodulation circuit, a first multi-path selection switch, a second low-pass filter circuit, a level shift circuit and a sampling feedback circuit; the cross gating switch array gates a capacitor unit of the array capacitor sensor to be tested, and the output end of the cross gating switch array is connected with the first input end of the CA conversion circuit; the four input ends of the sine wave signal generator are respectively input with a first square wave signal DS0, a second square wave signal DS1, a first analog signal AS0 and a second analog signal AS1 which are output by the singlechip, the first output end of the sine wave signal generator is connected with the second input end of the CA conversion circuit, and the second output end of the sine wave signal generator is connected with the second input end of the balancing circuit; the first input end of the balancing circuit is connected with the output end of the CA conversion circuit, and the output end of the balancing circuit is connected with the first input end of the amplitude demodulation circuit; the second input end of the amplitude demodulation circuit is connected with the square wave signal output port of the single chip microcomputer; the output end of the amplitude demodulation circuit is connected to the first input end of the second low-pass filter circuit through a first multi-path selection switch; the level shift circuit outputs a direct current shift voltage signal to a second input end of the second low-pass filter circuit, and the second low-pass filter circuit finally outputs a useful direct current signal to an on-chip analog-to-digital converter of the single chip microcomputer; the sampling feedback circuit respectively gates sine wave signals output by a first output end of the sine wave signal generator, an output end of the CA conversion circuit, the balancing circuit and the amplitude demodulation circuit, then the sine wave signals sequentially pass through the first multi-path selection switch and the second low-pass filter circuit to obtain sine wave amplitude signals, and the sine wave amplitude signals are output to an on-chip analog-to-digital converter of the single chip microcomputer.
2. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 1, wherein the balancing circuit comprises a second fixed gain device and an adder circuit, wherein an input terminal of the second fixed gain device is used as a second input terminal of the balancing circuit, a first input terminal of the adder circuit is used as a first input terminal of the balancing circuit, an output terminal of the second fixed gain device is connected to a second input terminal of the adder circuit, and an output terminal of the adder circuit is used as an output terminal of the balancing circuit.
3. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 1, wherein the amplitude demodulation circuit comprises a first fixed gain device, a first low pass filter circuit and a synchronous demodulation circuit; the input end of the first fixed gain device is used as the first input end of the amplitude demodulation circuit, the output end of the first fixed gain device is connected to the first input end of the synchronous demodulation circuit after passing through the first low-pass filter circuit, the second input end of the synchronous demodulation circuit is used as the second input end of the amplitude demodulation circuit, and the output end of the synchronous demodulation circuit is used as the output end of the amplitude demodulation circuit.
4. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 1, wherein the sampling feedback circuit comprises a second multi-way selector switch and a root-mean-square circuit, an input terminal of the second multi-way selector switch is used as an input terminal of the sampling feedback circuit, an output terminal of the second multi-way selector switch is connected to an input terminal of the root-mean-square circuit, and an output terminal of the root-mean-square circuit is used as an output terminal of the sampling feedback circuit.
5. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 1, wherein the cross-gated switch array comprises two sets of switch arrays, m + n inputs, two outputs; the first group of switch arrays comprises m groups of switches, each group of switches comprises two single-pole single-throw switches, one end of a first single-pole single-throw switch of the ith group of switches is connected with one end of a second single-pole single-throw switch of the ith group of switches and serves as one of m + n input ends of the cross gating switch array, the other end of the first single-pole single-throw switch of the ith group of switches is connected to one output end of the cross gating switch array, and the other end of the second single-pole single-throw switch of the ith group of switches is grounded; the second group of switch arrays comprises n groups of switches, each group of switches comprises two single-pole single-throw switches, one end of a first single-pole single-throw switch of the jth group of switches is connected with one end of a second single-pole single-throw switch of the jth group of switches and serves as the other one of m + n input ends of the cross gate switch array, the other end of the first single-pole single-throw switch of the jth group of switches is connected to the other output end of the cross gate switch array, and the other end of the second single-pole single-throw switch of the jth group of switches is grounded; wherein m is more than or equal to 1, n is more than or equal to 1, i is more than or equal to 1 and less than or equal to m, and j is more than or equal to 1 and less than or equal to n.
6. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 1, wherein the cross-gated switch array comprises two sets of switch arrays, m + n inputs, two outputs; the first group of switch arrays comprises m single-pole double-throw switches, the common end of the ith single-pole double-throw switch is used as one of m + n input ends of the cross gating switch array, the first end of the ith single-pole double-throw switch is connected to one output end of the cross gating switch array, and the second end of the ith single-pole double-throw switch is grounded; the second group of switch array comprises n single-pole double-throw switches, the common end of the jth single-pole double-throw switch is used as the other of the m + n input ends of the cross gate switch array, the first end of the jth single-pole double-throw switch is connected to the other output end of the cross gate switch array, and the second end of the jth single-pole double-throw switch is grounded; wherein m is more than or equal to 1, n is more than or equal to 1, i is more than or equal to 1 and less than or equal to m, and j is more than or equal to 1 and less than or equal to n.
7. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 1, wherein the sine wave signal generator comprises two sine wave generating circuits; the sine wave generating circuit comprises an amplitude control circuit, a single-pole double-throw electronic switch circuit and a filter; the input end of the amplitude control circuit inputs an analog signal output by an on-chip DAC of the singlechip, the output end of the amplitude control circuit is connected with one input end of the single-pole double-throw electronic switch circuit, the other input end of the single-pole double-throw electronic switch circuit is grounded, the common end of the single-pole double-throw electronic switch circuit is connected with the input end of the filter, and the output end of the filter outputs a sine wave.
8. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 1, wherein the CA switch circuit comprises a first Capacitor (CR), a second capacitor (C59), a first operational amplifier (U7-a), a first resistor (R32); one end of the first Capacitor (CR) is used as a second input end of the CA conversion circuit, and the other end of the first Capacitor (CR) is respectively connected with one end of the second capacitor (C59), one end of the first resistor (R32) and the inverting input end of the first operational amplifier (U7-A); the other end of the second capacitor (C59) and the non-inverting input end of the first operational amplifier (U7-A) are grounded; the output end of the first operational amplifier (U7-A) is connected with the other end of the first resistor (R32) and then used as the output end of the CA conversion circuit; both ends of the first resistor (R32) serve as first input terminals of the CA conversion circuit.
9. The dynamic measurement circuit of the array type capacitive sensor as claimed in claim 3, wherein the synchronous demodulation circuit comprises a second resistor (R49), a third resistor (R50), a fourth resistor (R51), a fifth resistor (R52), a sixth resistor (R53), a seventh resistor (R66), an eighth resistor (R67), a ninth resistor (R68), a third capacitor (C82), a fourth capacitor (C119), a second single-pole double-position switch (U11-B), a second operational amplifier (U10-A), and a third operational amplifier (U10-B); one end of a second resistor (R49) is connected with the first end of a second single-pole double-position switch (U11-B) and is used as the first input end of the synchronous demodulation circuit; the second end of the second single-pole double-position switch (U11-B) is grounded, and the common end of the second single-pole double-position switch (U11-B) is connected with one end of a fourth resistor (R51); the other end of the second resistor (R49) is respectively connected with one end of a sixth resistor (R53) and the inverting input end of the second work operational amplifier (U10-A), and the other end of the sixth resistor (R53) is grounded; the other end of the fourth resistor (R51) is connected with the non-inverting input end of the second operational amplifier (U10-A), and the output end of the second work operational amplifier (U10-A) is connected with the inverting input end of the third operational amplifier (U10-B) through a seventh resistor (R66); the third capacitor (C82) and the third resistor (R50) are connected in parallel and then are connected between the inverting input end and the output end of the second operational amplifier (U10-A); a ninth resistor (R68) is connected between the non-inverting input of the third operational amplifier (U10-B) and ground; the fourth capacitor (C119) and the eighth resistor (R67) are connected in parallel and then connected between the inverting input end and the output end of the third operational amplifier (U10-B); the output end of the third operational amplifier (U10-B) is used as the output end of the synchronous demodulation circuit after passing through a fifth resistor (R52).
10. The dynamic measurement circuit of the array capacitive sensor as claimed in claim 4, wherein the RMS circuit comprises a first voltage follower (U15-A), a tenth resistor (R69), an eleventh resistor (R70), a twelfth resistor (R71), a thirteenth resistor (R72), a fifth capacitor (C148), a fourth operational amplifier (U15-B), a first diode (D9) and a second diode (D10); the sine wave signal gated by the second multi-way selection switch is input to one end of a tenth resistor (R69) after passing through a first voltage follower (U15-A), and the other end of the tenth resistor (R69) is connected with the inverting input end of a fourth operational amplifier (U15-B); an eleventh resistor (R70) is connected between the non-inverting input of the fourth operational amplifier (U15-B) and ground; the output end of the fourth operational amplifier (U15-B) is connected with the anode of the second diode (D10); the fifth capacitor (C148) and the twelfth resistor (R71) are connected in parallel and then connected between the inverting input end and the output end of the fourth operational amplifier (U15-B); the anode of the first diode (D9) is connected with the inverting input end of the fourth operational amplifier (U15-B), and the cathode of the first diode (D9) is connected with the output end of the fourth operational amplifier (U15-B); the cathode of the second diode (D10) is connected with one end of a thirteenth resistor (R72), and the other end of the thirteenth resistor (R72) is used as the output end of the root mean square circuit.
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| CN111307183A (en) * | 2020-04-09 | 2020-06-19 | 北京先通康桥医药科技有限公司 | Dynamic measuring circuit of array type capacitive sensor |
| CN115112213A (en) * | 2022-07-12 | 2022-09-27 | 武汉科技大学 | Piezoelectric sensor, system and method for dynamically measuring automobile weight based on vehicle |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111307183A (en) * | 2020-04-09 | 2020-06-19 | 北京先通康桥医药科技有限公司 | Dynamic measuring circuit of array type capacitive sensor |
| CN115112213A (en) * | 2022-07-12 | 2022-09-27 | 武汉科技大学 | Piezoelectric sensor, system and method for dynamically measuring automobile weight based on vehicle |
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