CN211830786U

CN211830786U - Clock synchronization equipment based on Beidou

Info

Publication number: CN211830786U
Application number: CN201922460865.7U
Authority: CN
Inventors: 罗东海; 王云峰
Original assignee: Nanjing Ticom Tech Co ltd
Current assignee: Nanjing Ticom Tech Co ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-10-30
Anticipated expiration: 2029-12-31

Abstract

The utility model provides a clock synchronization device based on Beidou, which comprises a Beidou receiving module and an FPGA module, wherein the Beidou receiving module is used for receiving Beidou signals, demodulating the same time and 1PPS signals according to the Beidou signals and inputting the signals into the FPGA module; the FPGA module is synchronized with a 1PPS signal received by the Beidou; the FPGA module comprises a constant-temperature crystal oscillator and a DAC module, the Beidou receiving module is respectively connected with the frequency divider and the DAC module through an exclusive-OR gate, and the constant-temperature crystal oscillator is connected between the frequency divider and the DAC module. The time synchronization equipment based on the Beidou is dispersedly arranged on the periphery of equipment along the railway, the time synchronization of the control equipment can be well kept after the single clock equipment fails, meanwhile, in order to avoid Beidou signal loss, the time synchronization equipment is provided with a clock tracking and maintaining function, and can keep 24h synchronous tracking under the Beidou signal loss condition and give an alarm signal to facilitate maintenance and repair of maintenance personnel.

Description

Clock synchronization equipment based on Beidou

Technical Field

The utility model relates to a railway control system field specifically is a based on big dipper clock synchronization equipment.

Background

Railway communication networks mainly impose requirements on time synchronization in three aspects:

1. need for network optimization

At present, the network scale and the number of users of the Chinese railway communication network are in a relatively stable development period, and currently, the important work is to optimize the network, improve the network efficiency and guarantee the network safety. The strengthening of the network management system and the establishment of the seventh signaling monitoring system are important work contents of network optimization, and the network management system and the seventh signaling monitoring system both need time synchronization, and particularly, the smooth operation of the seventh signaling monitoring system needs high-precision time synchronization signals for marking the sequence of the monitored signaling flows.

2. Need for improved quality of service

The dependence of high-speed railways on communication is increasing, and the quality of service is one of the core problems that railway communication departments are concerned with. The problem of the right-to-front point of the high-speed railway is one of the problems which are very concerned by passengers, and one of the main reasons for causing disputes is time asynchronization, so that various operation synchronization problems need to be solved urgently.

3. The need for high speed railway transportation service

With the establishment of the GSM-R system adopted by the railway wireless communication technology, in the development process of the railway digital communication in east, particularly the continuous development and application of the CTCS train control technology, new services need to be continuously introduced to meet the requirements of high-speed railways, such as the transmission of train control speed limit commands, the transmission of wireless blocking signals, the positioning of train positions of motor train units, the monitoring of vehicle-mounted equipment and the like, and the smooth development of the new services all need to ensure the time synchronization with certain precision.

The railway control system adopts a clock server to carry out clock synchronization, all equipment on the whole line communicates with a clock service through a railway special network to keep clock synchronization, the running safety of the railway is ensured, and if the equipment clock along the line cannot keep synchronization due to the fault of the communication system, the control system fails to work, and the safe running of the railway is influenced.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a solve prior art's problem, provide a based on big dipper clock synchronization equipment, to deploy the time synchronization equipment dispersion based on big dipper at railway equipment periphery along the line, can fine keep controlgear's time synchronization after single clock equipment trouble, simultaneously in order to avoid big dipper signal to lose, time synchronization equipment has designed the clock tracking and has kept the function, can lose the condition at big dipper signal and keep 24h synchronous tracking to give alarm signal simultaneously and conveniently maintain maintainer's maintenance.

The utility model comprises a big dipper receiving module and an FPGA module, wherein the big dipper receiving module is used for receiving big dipper signals, demodulating north synchronous time and 1PPS signals according to the big dipper signals, and inputting the signals into the FPGA module; the FPGA module is synchronized with a 1PPS signal received by the Beidou; the FPGA module comprises a constant-temperature crystal oscillator and a DAC module, the Beidou receiving module is respectively connected with the frequency divider and the DAC module through an exclusive-OR gate, and the constant-temperature crystal oscillator is connected between the frequency divider and the DAC module.

The FPGA module constant-temperature crystal oscillator is further improved, the frequency of the FPGA module constant-temperature crystal oscillator is 10MHZ, and after the frequency is divided to 1hz, the frequency is synchronized with a 1PPS signal received by the Beidou.

When the clock is asynchronous with the Beidou receiving 1PPS after the constant temperature crystal oscillator frequency division, or the gate generates output back to control the DAC module to adjust the output of the constant temperature crystal oscillator, and when the output is adjusted to be synchronous, the XOR gate does not output and records the adjustment parameters in the EEROM.

After the circuit is adjusted, the local clock of the clock synchronization equipment is synchronized with the Beidou system, and when the Beidou signal is lost, the output of the constant-temperature crystal oscillator can be automatically adjusted according to EEROM parameters, and meanwhile, an alarm signal is given;

when the Beidou signal is lost, the FPGA provides a time signal holding function according to the local clock, and the time is ensured to be consistent with that of the Beidou system. The time of all clock synchronization equipment is synchronized with the Beidou time, so that the time and the clock of the control equipment along the railway line can be kept synchronous, and the tracking and keeping for a period of time can be ensured under the condition that the Beidou signal is lost, so that the time is strived for maintenance.

The utility model has the advantages that:

1. the optimized time synchronization of the railway control system is adjusted from a centralized CS architecture to a distributed architecture, and meanwhile, a special communication network is removed, so that compared with the existing time synchronization system, the time synchronization system greatly saves the construction cost, increases the stability and maintainability of the system, and has the advantages that the clock failure of a single node does not affect all control equipment along the line, the failure range is reduced, and the technical support is provided for improving the railway driving efficiency and safe driving.

2. The clock synchronization device is used for field test application on a railway control system of the department of China, is used for recording the fault time of the device, completely meets the requirement of the field on the fault recording time through test operation, solves the problem that the device along the line is actually inconsistent with a server, can meet the field practical application, and has wide market prospect.

Drawings

Fig. 1 is a schematic diagram of a clock synchronization apparatus.

FIG. 2 is a schematic diagram of a synchronization circuit.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings.

The structure of the utility model is as shown in figure 1, and comprises a big dipper receiving module and an FPGA module, wherein the big dipper receiving module is used for receiving big dipper signals, demodulating north synchronous time and 1PPS signals according to the big dipper signals, and inputting the big dipper signals into the FPGA module; the FPGA module is synchronous with the 1PPS signal received by the big dipper, the synchronizing circuit is shown in figure 2, the FPGA module comprises a constant temperature crystal oscillator and a DAC module, the big dipper receiving module is respectively connected with a frequency divider and the DAC module through an exclusive-OR gate, and the constant temperature crystal oscillator is connected between the frequency divider and the DAC module.

The functional requirements are as follows:

the Beidou clock-based synchronous tracking and keeping function is realized.

The main technical indexes are as follows:

the big dipper receiver: a channel: 6; reception sensitivity: 157.6 dBW; cold start first catch time: less than or equal to 2 seconds; lock losing recapture time: less than or equal to 1 second; 1PPS accuracy: is better than 100 nS.

The length of the time service antenna is matched with 30 meters, and can be selected from 40, 50, 60, 80, 100, 120, 150, 200 and 300 meters or more.

NTP/SNTP throughput: 20000 time requests per second are fulfilled.

The network port support protocol: NTP/SNTP, ARP, UDP/Time, Telnet, TFTP, SNMP, ICMP, DHCP, MD 5.

The external dimension is as follows: standard rack mount chassis, 1U, 19 inches.

And (3) time setting precision: pulse, B code: 0.1 μ S, serial port: 10 μ S, NTP/SNTP: 1-10ms, PTP:70 ns.

Power and environmental requirements:

1. working temperature: -20 ℃ to +70 ℃, storage temperature: -40 ℃ to +85 ℃, humidity: < 95%.

2. Input DC24V + 20%.

3. The power consumption of the whole machine is less than 30 w.

The electromagnetic compatibility requirement is as follows:

the electromagnetic compatibility requirement should comply with the relevant regulation of GB/T24338.5.

The safety requirement is as follows:

1 is grounded.

2, electric strength:

a power interface: the insulation withstand voltage is more than or equal to 1500V.

3, anti-electromagnetic interference:

a power interface: the circuit has the protection of anti-surge, anti-peak voltage and anti-lightning circuit.

4, safety protection:

a power interface: input overvoltage protection, output overcurrent protection, communication, detection interface: isolation protection is required.

The utility model discloses the concrete application way is many, and the above-mentioned only is the preferred embodiment of the utility model, should point out, to ordinary skilled person in this technical field, under the prerequisite that does not deviate from the utility model discloses the principle, can also make a plurality of improvements, and these improvements also should be regarded as the utility model discloses a scope of protection.

Claims

1. The utility model provides a clock synchronization equipment based on big dipper which characterized in that: the Beidou receiver comprises a Beidou receiving module and an FPGA module, wherein the Beidou receiving module is used for receiving a Beidou signal, demodulating a same north time and a 1PPS signal according to the Beidou signal, and inputting the same north time and the 1PPS signal into the FPGA module; the FPGA module is synchronized with a 1PPS signal received by the Beidou; the FPGA module comprises a constant-temperature crystal oscillator and a DAC module, the Beidou receiving module is respectively connected with the frequency divider and the DAC module through an exclusive-OR gate, and the constant-temperature crystal oscillator is connected between the frequency divider and the DAC module.

2. The Beidou clock synchronization device based on claim 1, characterized in that: the frequency of the constant-temperature crystal oscillator of the FPGA module is 10MHZ, and after the frequency is divided to 1hz, the constant-temperature crystal oscillator is synchronized with a 1PPS signal received by the Beidou.