CN211830602U

CN211830602U - Synchronous rectification control circuit and isolated voltage conversion circuit

Info

Publication number: CN211830602U
Application number: CN202020106182.1U
Authority: CN
Inventors: 张波; 文鹏
Original assignee: Hangzhou Biyi Microelectronics Co ltd
Current assignee: Hangzhou Biyi Microelectronics Co ltd
Priority date: 2020-01-17
Filing date: 2020-01-17
Publication date: 2020-10-30
Anticipated expiration: 2030-01-17

Abstract

The application relates to a synchronous rectification control circuit and an isolated voltage conversion circuit, wherein when a detection circuit detects that a drain-source voltage is in a plateau period and the drain-source voltage is continuously greater than a first threshold value within a preset time, an effective primary side conduction signal is output; and after receiving the effective primary side conduction signal, the conduction control circuit controls the synchronous rectification switch to be conducted if the drain-source voltage is smaller than a second threshold value. The effective primary side conduction signal can represent that the primary side switch is in a conduction state, and the drain-source voltage is smaller than the second threshold value and can represent that the body diode of the synchronous rectification switch is in the conduction state, so that the conduction control circuit can accurately judge the conduction time of the synchronous rectification switch and control the conduction of the synchronous rectification switch in the conduction time.

Description

Synchronous rectification control circuit and isolated voltage conversion circuit

Technical Field

The present disclosure relates to synchronous rectification technologies, and particularly to a synchronous rectification control circuit and an isolated voltage converting circuit.

Background

With the development of electronic technology, synchronous rectification circuits are widely used in situations where high conversion efficiency is required due to their high conversion efficiency. A synchronous rectification circuit generally refers to a circuit that receives an input voltage on the primary side of a transformer and converts the input voltage to a desired output voltage on the secondary side of the transformer using a synchronous rectification switch.

In the secondary side synchronous rectification scheme, the on and off of the synchronous rectification switch are usually controlled directly according to the drain-source voltage of the synchronous rectification switch. However, in this control method, if the power supply operates in a DCM Mode (discontinuous conduction Mode), when the synchronous rectification switch is turned off, the circuit may oscillate, and parasitic oscillation of the circuit may also cause the body diode of the synchronous rectification switch to be turned on, which may cause the synchronous rectification switch to be turned on erroneously. If the parasitic oscillation time is directly blanked, the blanking time (Blank time) may hinder the normal turn-on of the synchronous rectification switch in the QR (quasi-resonant Mode) and CCM (Continuous Conduction Mode) operation modes, thereby reducing the efficiency of the power supply. Therefore, the existing synchronous rectification circuit cannot accurately control the conduction of the synchronous rectification switch, and the power supply efficiency is low.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a synchronous rectification control circuit and an isolated voltage conversion circuit, which can accurately control the conduction time of a synchronous rectification switch and improve the power efficiency.

A synchronous rectification control circuit connected with a secondary side synchronous rectification switch comprises:

the first comparison circuit is used for comparing the drain-source voltage of the synchronous rectification switch with a first threshold value;

the detection circuit is connected with the first comparison circuit and used for outputting an effective primary side conduction signal when the drain-source voltage is detected to be in a plateau period and the drain-source voltage is continuously greater than the first threshold value within a preset time, wherein the effective primary side conduction signal is used for representing that a primary side switch is in a conduction state;

a second comparison circuit for comparing the drain-source voltage with a second threshold; the second threshold is less than the first threshold;

and the conduction control circuit is respectively connected with the detection circuit and the second comparison circuit and is used for controlling the conduction of the synchronous rectification switch if the drain-source voltage is smaller than the second threshold value after the conduction of the primary side switch is detected.

In one embodiment, the detection circuit is further configured to determine that the drain-source voltage is in the plateau period when it is detected that a rising slope of the drain-source voltage is smaller than a rising slope threshold and a falling slope of the drain-source voltage is smaller than a falling slope threshold within the preset time.

In one embodiment, the detection circuit is further configured to determine that the drain-source voltage is in a plateau period when it is detected within the preset time that the rising amplitude of the drain-source voltage does not exceed a rising threshold and the falling amplitude of the drain-source voltage does not exceed a falling threshold.

In one embodiment, the synchronous rectification control circuit is coupled to a resistor or a capacitor, and the preset time is set through the resistor or the capacitor.

In one embodiment, the detection circuit comprises:

the integration module is used for carrying out integration operation on time to obtain an integration signal;

the signal comparison module is connected with the integration module and used for outputting the primary side conduction signal according to the integration signal and a reference signal;

and the integration control module is connected with the integration module and used for outputting a pulse signal to control the integration module to clear the integration signal when the rising amplitude of the drain-source voltage exceeds a rising threshold value or the falling amplitude exceeds a falling threshold value.

In one embodiment, the first comparison circuit is connected to the integration module or the signal comparison module, and is further configured to control the integration module to clear the integration signal or control the signal comparison module to stop working when the drain-source voltage is smaller than the first threshold.

In one embodiment, the integration control module comprises:

a voltage holding unit which samples the drain-source voltage to provide a drain-source voltage holding signal when receiving the pulse signal;

the rising detection unit is connected with the voltage holding unit and outputs a first pulse trigger signal when the difference value of the drain-source voltage and the drain-source voltage holding signal is greater than the rising threshold value;

the voltage holding unit is connected with the input end of the first pulse trigger signal, and the voltage holding unit is used for holding the drain-source voltage of the first pulse trigger signal;

and the pulse output unit is respectively connected with the rising detection unit and the falling detection unit and is used for outputting the pulse signal when receiving the first pulse trigger signal or the second pulse trigger signal.

In one embodiment, the integration module comprises:

the current source is used for providing an integration power supply for the integration unit;

the integration unit is coupled with the current source and the signal comparison module and is used for integrating the integration power supply with time;

the zero clearing switch is connected with the current source and the integration unit in a sharing mode and is used for controlling the integration unit to integrate the integration power source with time when the integration unit is switched off and controlling the integration unit to clear the integration when the integration unit is switched on;

and the switch control unit is respectively connected with the signal comparison module, the integral control module and the zero clearing switch and is used for controlling the zero clearing switch to be switched on when the pulse signal or an effective primary side switching-on signal is received.

In one embodiment, the method further comprises the following steps:

the turn-off control circuit is connected with the synchronous rectifier switch and used for outputting a turn-off control signal according to the drain-source voltage;

the reset end of the first trigger circuit is connected with the output end of the turn-off control circuit, the position end of the first trigger circuit is connected with the output end of the turn-on control circuit, and the output end of the first trigger circuit is coupled with the grid of the synchronous rectification switch.

In one embodiment, the method further comprises the following steps:

and the reset end of the second trigger circuit is coupled with the output end of the first trigger circuit, the position end of the second trigger circuit is connected with the output end of the detection circuit, and the output end of the second trigger circuit is connected with the input end of the conduction control circuit.

In one embodiment, the method further comprises the following steps:

and the sampling circuit is respectively connected with the first comparison circuit, the detection circuit, the second comparison circuit and the synchronous rectification switch, and is used for collecting the drain-source voltage and respectively outputting the drain-source voltage to the detection circuit, the first comparison circuit and the second comparison circuit.

An isolated voltage conversion circuit comprising:

the energy storage element comprises a primary winding and a secondary winding;

the primary side switch is coupled with the primary side winding of the energy storage element;

the synchronous rectification switch is coupled with the secondary winding of the energy storage element; and

a circuit as described above.

The synchronous rectification control circuit and the isolated voltage conversion circuit output effective primary side conduction signals when the detection circuit detects that the drain-source voltage is in a plateau period and the drain-source voltage is continuously greater than a first threshold value within a preset time; and after receiving the effective primary side conduction signal, the conduction control circuit controls the synchronous rectification switch to be conducted if detecting that the drain-source voltage is smaller than a second threshold value. The effective primary side conduction signal can represent that the primary side switch is in a conduction state, and the drain-source voltage is smaller than the second threshold value and can represent that the body diode of the synchronous rectification switch is in the conduction state, so that the conduction control circuit can accurately judge the conduction time of the synchronous rectification switch and control the conduction of the synchronous rectification switch in the conduction time.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of a synchronous rectification control circuit of an embodiment;

FIG. 2 is a block diagram of a detection circuit in one embodiment;

FIG. 3 is a block diagram of an integral control module in one embodiment;

FIG. 4 is a block diagram of an integral control module in one embodiment;

FIG. 5 is a block diagram of a synchronous rectification control circuit in another embodiment;

FIG. 6 is a schematic diagram of an embodiment of a circuit corresponding to the circuit of FIG. 5;

FIG. 7 is a timing diagram illustration of a synchronous rectification control circuit in one embodiment;

FIG. 8 is a timing diagram representation of a synchronous rectification control circuit in one embodiment;

FIG. 9 is a block diagram of an isolated voltage translation circuit in one embodiment;

FIG. 10 is a circuit diagram of the circuit of FIG. 9 according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. The term "couple" or "connect" as used herein includes both direct and indirect connections, such as through an electrically conductive medium such as a metal or through some other known active or passive device that performs the same function.

Fig. 1 is a block diagram of a synchronous rectification control circuit of an embodiment.

As shown in fig. 1, the synchronous rectification control circuit 20 is connected to the secondary side synchronous rectification switch 10, and the synchronous rectification control circuit 20 includes a first comparison circuit 200, a detection circuit 201, a second comparison circuit 202, and a conduction control circuit 203. The synchronous rectification control circuit 20 is connected to the drain and the gate of the synchronous rectification switch 10, and is connected to the drain-source voltage of the synchronous rectification switch 10 to control the on/off of the synchronous rectification switch 10 through the gate.

The first comparison circuit 200 is used for comparing the drain-source voltage of the synchronous rectification switch with a first threshold value.

The detection circuit 201 is configured to output an effective primary side conduction signal when it is detected that the drain-source voltage of the synchronous rectifier switch 10 is in a plateau period and the drain-source voltage is greater than a first threshold within a preset time, where the effective primary side conduction signal is used to represent that the primary side switch is in a conduction state. For example, when the primary side conduction signal is at an effective value, such as a high level, it indicates that the primary side switch of the flyback voltage conversion circuit is detected to be conductive.

And a second comparing circuit 202 for comparing the drain-source voltage with a second threshold value, wherein the second threshold value is smaller than the first threshold value.

And the conduction control circuit 203 is respectively connected with the detection circuit 201 and the second comparison circuit 202, and is used for controlling the conduction of the synchronous rectification switch 10 if the drain-source voltage is smaller than the second threshold value after the conduction of the primary side switch is detected.

In this embodiment, the first comparison circuit 200 is connected to the synchronous rectification switch 10, and is connected to the drain-source voltage of the synchronous rectification switch 10 to compare the drain-source voltage of the synchronous rectification switch 10 with the first threshold. In one embodiment, the first comparison circuit 200 may be a comparator that outputs an active first comparison signal when the drain-source voltage is greater than a first threshold. The active state of the first comparison signal may be a high state or a low state, and is determined by specific devices inside the first comparison circuit 200 and specific setting conditions of the first threshold.

In this embodiment, the detection circuit 201 is connected to the synchronous rectification switch 10, and is connected to the drain-source voltage of the synchronous rectification switch 10, and when it is detected that the drain-source voltage is in the plateau period and the drain-source voltage is greater than the first threshold within a preset time, an effective primary side conduction signal is output, and the effective primary side conduction signal is used to represent that the primary side switch is in a conduction state.

Wherein, the plateau refers to a region with relatively gentle change in the window time. The drain-source voltage is in the plateau period, which means that the voltage value of the drain-source voltage is basically constant or the variation value of the drain-source voltage is in an acceptable range within the window time corresponding to the plateau period. Further, the drain-source voltage is in the plateau period, which means that the variation amplitude or the slope of the drain-source voltage is smaller than a preset variation threshold. The preset variation threshold includes an ascending threshold and a descending threshold. Both the rising threshold and the falling threshold can be set according to actual requirements.

In an embodiment, the detection circuit is configured to determine that the drain-source voltage is in the plateau period when it is detected within a preset time that a rising slope of the drain-source voltage is smaller than a rising slope threshold and a falling slope of the drain-source voltage is smaller than a falling slope threshold.

In an embodiment, the detection circuit is configured to determine that the drain-source voltage is in a plateau period when it is detected within a preset time that the rising amplitude of the drain-source voltage does not exceed the rising threshold and the falling amplitude of the drain-source voltage does not exceed the falling threshold.

The preset time is set according to the window time of the platform period, and in one embodiment, the preset time is equal to the window time. In one embodiment, the synchronous rectification control circuit 20 is coupled to a resistor or a capacitor, and the preset time is set by the resistor or the capacitor.

The first threshold may be set according to a predetermined drain-source voltage value of the secondary synchronous rectification switch corresponding to the primary switch in the on state or set according to experience, and is used to distinguish a level plateau under other conditions, for example, to distinguish a plateau of a maximum control waveform for suppressing secondary voltage oscillation, so that the first threshold is greater than the threshold of the plateau, and thus, false triggering of the secondary synchronous rectification switch in the oscillation period can be effectively avoided.

Wherein the valid primary side conduction signal is indicative of the detection of the primary side switch conduction. The effective state of the primary side conduction signal may be a high level state or a low level state, and the effective state of the primary side conduction signal may be set according to the setting conditions of the internal specific devices of the detection circuit 201 and the conduction control circuit 203. Upon detecting that the primary switch is on, the detection circuit 201 outputs an active primary on signal to instruct the on control circuit 203 to perform the related synchronous rectification operation next.

In this embodiment, the second comparing circuit 202 is connected to the synchronous rectification switch 10, inputs the drain-source voltage, compares the drain-source voltage with the second threshold, and when the drain-source voltage is smaller than the second threshold, for example, smaller than-50 mv, it indicates that the body diode of the synchronous rectification switch 10 is currently in the conducting state, and since the current state is after the primary side switch is conducted, it can be determined that the conducting state of the body diode is not caused by the parasitic oscillation of the circuit.

Wherein the second threshold is less than the first threshold. When the drain-source voltage is smaller than the second threshold, the second comparing circuit 202 outputs an effective second comparing signal, the effective state of the second comparing signal may be a high level state or a low level state, and the effective state of the second comparing signal is determined by specific devices inside the second comparing circuit 202 and specific setting conditions of the second threshold.

In this embodiment, the conduction control circuit 203 is respectively connected to the detection circuit 201 and the second comparison circuit 202, and is configured to control the synchronous rectification switch 10 to be turned on if the drain-source voltage is smaller than the second threshold after the primary side switch is detected to be turned on.

The primary side conduction signal is represented by invalid to valid, and the primary side switch is detected to be turned on, the next sudden change of the drain-source voltage corresponds to the turn-off of the primary side switch, and at the moment, the conduction control circuit 203 controls the synchronous rectification switch 10 to be turned on according to the primary side conduction control signal and the second comparison signal. After the synchronous rectification switch 10 is turned on, once the drain-source voltage changes abruptly in a reverse direction, indicating that the secondary side current is close to zero, the synchronous rectification switch 10 can be turned off. In one embodiment, a turn-off control circuit may be provided, which controls the synchronous rectification switch 10 to turn off by detecting the variation of the drain-source voltage until the next cycle. To this end, synchronous control of the synchronous rectification switch 10 is realized.

In the synchronous rectification control circuit provided by this embodiment, when the detection circuit 201 detects that the drain-source voltage is in the plateau period and the drain-source voltage is continuously greater than the first threshold value within the preset time, an effective primary side conduction signal is output; after receiving the valid primary side conduction signal, the conduction control circuit 203 controls the synchronous rectification switch 10 to be conducted if the drain-source voltage is smaller than the second threshold. The effective primary side conduction signal can represent that the primary side switch is in a conduction state, and the drain-source voltage is smaller than the second threshold value and can represent that the body diode of the synchronous rectification switch 10 is in the conduction state, so that the conduction control circuit 203 can accurately judge the conduction time of the synchronous rectification switch 10 and control the conduction of the synchronous rectification switch 10 at the conduction time.

Referring to fig. 2, fig. 2 is a block diagram of a detection circuit 201 according to an embodiment.

As shown in fig. 2, the detection circuit 201 includes an integration module 301, a signal comparison module 302, and an integration control module 303.

An integrating module 301, configured to perform an integrating operation on time to obtain an integrated signal.

And the signal comparison module 302 is connected to the integration module 301, and is configured to output a primary side conduction signal according to the integration signal and the reference signal.

And the integration control module 303 is connected with the integration module 301, and is configured to output a pulse signal to control the integration module 301 to clear the integration signal when the rising amplitude of the drain-source voltage exceeds a rising threshold or the falling amplitude exceeds a falling threshold.

In the embodiment shown in fig. 2, the integration module 301 is connected to the integration control module 303 and the signal comparison module 302, respectively, and the integration module 301 performs integration operation on time to obtain an integration signal and outputs the integration signal to the signal comparison module 302; when the pulse signal of the integration control module 303 is received, the integration signal is cleared and re-integrated, so that the subsequent signal comparison module 302 re-compares the integration signal with the reference signal. The integration module 301 integrates time, specifically, the integration module 301 converts the integration of a current source over time into a voltage stored on an integration capacitor to obtain an integrated signal.

In an embodiment, the integration module 301 is further connected to the output end of the signal comparison module 302, and when receiving the valid primary side conduction signal output by the signal comparison module 302, clears the integration signal to zero and re-integrates.

In this embodiment, the signal comparison module 302 is connected to the integration module 301, and the signal comparison module 302 compares the received integration signal with the time reference signal, and outputs an effective primary side conduction signal when the integration signal is greater than the time reference signal.

The time reference signal can be empirically set to an integral value less than a constant (determined by parameters such as current source and capacitance) over the primary switch on-time.

The voltage of the integrated signal increases with time, and when the voltage of the integrated signal is greater than the time reference signal, it indicates that the integrated signal is currently in the primary side switch conduction period, and at this time, the signal comparison module 302 outputs a primary side conduction signal with an effective value to the conduction control circuit 203. The integral voltage caused by parasitic oscillation is not greater than the time reference signal due to short platform period, so that an effective primary side conduction signal is not generated.

In one embodiment, the signal comparison module 302 provides the time reference signal by setting the duration configuration unit. Specifically, the duration configuration unit may obtain the time reference signals of different voltage values by coupling the resistors and adjusting the resistance values of the resistors.

In an embodiment, the integrating module 301 and the signal comparing module 302 are further connected to the first comparing circuit 200 respectively. The first comparison circuit 200 is configured to enable the integration module 301 or the signal comparison module 302 when the drain-source voltage is greater than a first threshold within a preset time, so that the integration module 301 or the signal comparison module 302 operates normally; when the drain-source voltage is smaller than the first threshold value within the preset time, the integration module 301 is controlled to stop working, or the integration module 301 is controlled to clear the integration, or the signal comparison module 302 is controlled to stop working. Therefore, once the drain-source voltage is detected to be smaller than the first threshold value within the preset time, an effective primary side conducting signal cannot be generated.

In this embodiment, the integration control module 303 is connected to the integration module 301, and outputs a pulse signal to control the integration module 301 to clear the integration signal when the rising amplitude of the drain-source voltage exceeds a rising threshold or the falling amplitude exceeds a falling threshold.

Specifically, when the rising amplitude of the drain-source voltage does not exceed the rising threshold and the falling amplitude does not exceed the falling threshold, the integration control module 303 outputs no effective pulse signal, so that the integration of the integration module 301 with respect to time is not affected; if no effective pulse signal is output after the preset time, the drain-source voltage is in a plateau period, and the signal comparison module 302 outputs an effective primary side conduction signal; when the rising amplitude of the drain-source voltage exceeds the rising threshold or the falling amplitude exceeds the falling threshold within the preset time, that is, the drain-source voltage is judged not to be in the plateau period, an effective pulse signal is output to control the integration module 301 to zero the integration signal and restart the integration, and the judgment process is repeated.

Referring to fig. 3, fig. 3 is a structural diagram of the integration control module 303 according to an embodiment.

As shown in fig. 3, the integration control module 303 includes a voltage holding unit 401, a rise detection unit 402, a fall detection unit 403, and a pulse output unit 404.

And a voltage holding unit 401 for inputting a drain-source voltage, sampling the drain-source voltage when receiving the pulse signal, and providing a drain-source voltage holding signal.

And a rising detection unit 402 connected to the voltage holding unit 401, for outputting a first pulse trigger signal when a difference between the drain-source voltage and the drain-source voltage holding signal is greater than the rising threshold.

And a drop detection unit 403 connected to the voltage holding unit 401, and configured to output a second pulse trigger signal when a difference between the drain-source voltage holding signal and the drain-source voltage is greater than a drop threshold.

And a pulse output unit 404, connected to the rising detection unit 402 and the falling detection unit 403, respectively, for outputting a pulse signal when receiving the first pulse trigger signal or the second pulse trigger signal.

The voltage holding unit 401 has an input terminal for receiving a drain-source voltage, an output terminal for providing a drain-source voltage holding signal, and an enable terminal for receiving a pulse signal. The rise detection unit 402 may have a first terminal for receiving a drain-source voltage and a second terminal for receiving a drain-source voltage hold signal. The droop detecting unit 403 may have a first terminal for receiving a drain-source voltage and a second terminal for receiving a drain-source voltage holding signal. The pulse output unit 404 has a first input terminal coupled to the output terminal of the rising detection unit 402, a second input terminal coupled to the output terminal of the falling detection unit 403, and an output terminal providing a pulse signal.

Specifically, when the voltage holding unit 401 does not receive the pulse signal, the voltage output by the voltage holding unit 401 is held, and the rising detection unit 402 outputs the first pulse trigger signal when detecting that the rising amplitude of the drain-source voltage with respect to the drain-source voltage holding signal is greater than the rising threshold, or the falling detection unit 403 outputs the second pulse trigger signal when detecting that the falling amplitude of the drain-source voltage with respect to the drain-source voltage holding signal is greater than the falling threshold. The pulse output unit 404 outputs a pulse signal when receiving the first pulse trigger signal or the second pulse trigger signal, so as to trigger the voltage holding unit 401 to update the voltage holding signal to be the current drain-source voltage.

Referring to fig. 4, fig. 4 is a block diagram of an integration module 301 according to an embodiment.

As shown in fig. 4, the integration module 301 includes a current source 501, an integration unit 502, a clear switch 503, and a switch control unit 504.

A current source 501 for providing integration power to the integration unit 502.

The integrating unit 502 and the current source 501 are connected to the signal comparing module 302, and are configured to integrate the integrated power with respect to time.

A clear switch 503 is used to cause the integration unit 502 to integrate the integration power supply with time when it is turned off, and to control the integration unit 502 to clear the integration when it is turned on.

And the switch control unit 504 is respectively connected with the signal comparison module 302, the integration control module 303 and the clear switch 503, and is configured to control the clear switch 503 to be turned on when a pulse signal or an effective primary side conduction signal is received.

The input end of the switch control unit 504 is connected with the signal comparison module 302 and the integration control module 303 respectively, the output end of the switch control unit 504 is connected with the control end of the zero clearing switch 503, the output end of the current source 501, the normally closed contact of the zero clearing switch 503 and the first end of the integration unit 502 are connected to the input end of the signal comparison module 302 in a shared manner, and the normally open contact of the zero clearing switch 503 and the second end of the integration unit 502 are connected to the ground in a shared manner.

Specifically, the current source 501 charges the integration unit 502, and the voltage on the integration unit 502 represents the integrated voltage of the current source over time. When the switch control unit 504 does not receive the pulse signal or does not receive the effective primary side conducting signal, the zero clearing switch 503 is in a disconnected state, and the integration unit 502 integrates the time; when the switch control unit 504 receives the pulse signal or the effective primary side conduction signal, the switch control unit 504 controls the conduction of the zero clearing switch 503, and the integration unit 502 clears the accumulated voltage to detect whether the plateau period is performed again.

In other embodiments, the switch control unit 504 may further be connected to the first comparison circuit 200, and when the first comparison circuit 200 detects that the drain-source voltage is smaller than the first threshold, the zero clearing switch 503 is controlled to be turned on, so that the integration unit 502 performs integration zero clearing, and interference in the oscillation period voltage limiting plateau period is prevented.

Referring to fig. 5, fig. 5 is a block diagram of a synchronous rectification control circuit 20 according to another embodiment.

On the basis of the above embodiment, the synchronous rectification control circuit 20 further includes a shutdown control circuit 204 and a first flip-flop circuit 205.

And the turn-off control circuit 204 is connected with the synchronous rectification switch 10 and used for outputting a turn-off control signal according to the drain-source voltage.

And a reset end of the first trigger circuit 205 is connected with the output end of the turn-off control circuit 204, a set end of the first trigger circuit 205 is connected with the output end of the turn-on control circuit 203, and an output end of the first trigger circuit 205 is connected with the gate of the synchronous rectification switch 10.

The turn-off control circuit 204 generates an active turn-off control signal when the drain-source voltage reaches a preset turn-off voltage threshold, and turns off the secondary synchronous rectification switch 10 when the turn-off control signal changes from an inactive state to an active state. The threshold of the turn-off voltage can be set according to actual conditions.

The reset terminal of the first flip-flop 205 is connected to the output terminal of the turn-off control circuit 204, and the set terminal of the first flip-flop 205 is connected to the output terminal of the turn-on control circuit 203, so that the state of the first flip-flop 205 is controlled by the turn-off control signal and the output signal of the turn-on control circuit 203. When the reset terminal input signal is inactive, such as low level, and the set terminal input signal is active, such as high level, the trigger state of the first trigger circuit 205 is determined by the signal at the set terminal, i.e. the first trigger circuit 205 is controlled by the conduction control circuit 203 for conducting the secondary side synchronous rectification switch 10. When the reset terminal input signal is active, such as high level, and the set terminal input signal is inactive, such as low level, the trigger state of the first trigger circuit 205 is determined by the reset terminal signal, that is, the first trigger circuit 205 is controlled by the turn-off control circuit 204, and is used to turn off the secondary side synchronous rectification switch 10. Thus, a satisfactory trigger pulse is supplied through the first trigger circuit 205 to turn on or off the synchronous rectification switch 10.

On the basis of the above embodiment, the synchronous rectification control circuit 20 may further include a second flip-flop circuit 206.

The reset terminal of the second flip-flop circuit 206 is coupled to the output terminal of the first flip-flop circuit 203, the set terminal of the second flip-flop circuit 206 is connected to the output terminal of the detection circuit 201, and the output terminal of the second flip-flop circuit 206 is connected to the input terminal of the conduction control circuit 203.

When the reset input signal of the second flip-flop circuit 206 is active, such as high, and the set input signal is inactive, such as low, the trigger state of the second flip-flop circuit 206 is determined by the reset signal, i.e. the second flip-flop circuit 206 is controlled by the first flip-flop circuit 205, and the output is set to zero. When the reset terminal input signal is in an inactive state, such as a low level, and the set terminal input signal is in an active state, such as a high level, the trigger state of the second trigger circuit 206 is determined by the signal at the set terminal, that is, the second trigger circuit 206 is controlled by the detection circuit 201, and outputs an active primary side conduction signal. Thus, a satisfactory trigger pulse is provided by the second trigger circuit 206 to trigger the turn-on control circuit 203.

On the basis of the above embodiment, the synchronous rectification control circuit 20 further includes the sampling circuit 207.

And the sampling circuit 207 is respectively connected with the first comparison circuit 200, the detection circuit 201, the second comparison circuit 202 and the synchronous rectification switch 10, and is used for collecting drain-source voltage and respectively outputting the drain-source voltage to the detection circuit 201 and the second comparison circuit 202.

Specifically, the sampling circuit 207 may include a resistance voltage divider circuit, and the drain-source voltage of the synchronous rectification switch 10 is sampled by the resistance voltage divider circuit, and the magnitude of the voltage value obtained by sampling is specifically determined by the drain-source voltage and the setting condition of the internal devices of the sampling circuit 207.

By the sampling circuit 207, different resistance values can be set according to actual needs to obtain different sampling ratios. According to different sampling ratios, the first threshold value and the second threshold value can be set to be reference values of corresponding ratios respectively.

Referring to fig. 6, fig. 6 is a specific circuit diagram corresponding to the circuit of fig. 5 in an embodiment.

In this embodiment, the detection circuit 201 includes an integration module 301, a signal comparison module 302, and an integration control module 303.

Specifically, the specific structure of each block in the first comparison circuit 200 and the detection circuit 201 is as follows: in this embodiment, the first comparing circuit 200 includes a comparator a1, and a non-inverting input terminal of the comparator a1 is connected to the sampling circuit 207The output terminal of (1) inputs the sampling voltage of the drain-source voltage; the inverting input terminal of the comparator a1 inputs the first threshold reference voltage, and the output terminal of the comparator a1 is connected 302 to the integrating module 301 or the signal comparing module. When the drain-source voltage (characterized by Vds _ s) is greater than the first threshold (characterized by Ref 1), the first comparator A1 outputs the comparison signal A1out of high level, and the detection circuit 201 operates normally. When the drain-source voltage is less than the first threshold, the first comparator a1 outputs a low level, which prevents the detection circuit 201 from outputting a valid primary side conduction signal. In the illustrated embodiment, the inverted value of the output signal of comparator A1

And the input terminal of the OR gate OR2 in the integration module 301 is coupled, and when the drain-source voltage is smaller than the first threshold, the integration signal Vc2 in the integration circuit 301 is cleared, and the primary side conduction signal PWM on keeps a low level.

In this embodiment, the integration control module 303 includes a voltage holding unit 401, a rise detection unit 402, a fall detection unit 403, and a pulse output unit 404.

The voltage holding unit 401 includes a normally open switch S1 and a capacitor C1, a normally closed contact of the normally open switch S1 is an input end of the voltage holding unit 401, the normally open contact of the normally open switch S1 and a first end of the capacitor C1 are connected together to be an output end of the voltage holding unit 401, and a control end of the normally open switch S1 is connected to an output end of the pulse output unit 404.

The rising detection unit 402 includes a voltage source V1, a comparator A3, and a rising edge detector O1. An input terminal of the voltage source V1 is connected to the output terminal of the sampling circuit 207 to input the drain-source voltage, an output terminal of the voltage source V1 is connected to a non-inverting input terminal of the comparator A3, an inverting input terminal of the comparator A3 is connected to the output terminal of the voltage holding unit 401, an output terminal of the comparator A3 is connected to an input terminal of the rising edge detector O1, and an output terminal of the rising edge detector O1 is connected to a first input terminal of the pulse output unit 404. Voltage source V1 is a rising threshold reference signal.

The falling detection unit 403 includes a voltage source V2, a comparator a4, and a rising edge detector O2. An input terminal of the voltage source V2 is connected to the output terminal of the sampling circuit 207 to input the drain-source voltage, an output terminal of the voltage source V2 is connected to an inverting input terminal of the comparator a4, a non-inverting input terminal of the comparator a4 is connected to the output terminal of the voltage holding unit 401, an output terminal of the comparator a4 is connected to an input terminal of the rising edge detector O2, and an output terminal of the rising edge detector O2 is connected to a second input terminal of the pulse output unit 404. Voltage source V2 is a falling threshold reference signal.

The pulse output unit 404 includes an OR gate OR1, a first input terminal of the OR gate OR1 is a first input terminal of the pulse output unit 404, a second input terminal of the OR gate OR1 is a second input terminal of the pulse output unit 404, and an output terminal of the OR gate OR1 is an output terminal of the pulse output unit 404.

Wherein the pulse output unit 404 outputs a pulse of a fixed time length when the input jumps from a low level to a high level by the rising edge detector O1, and the pulse output unit 404 outputs a pulse of a fixed time length when the input jumps from a low level to a high level by the rising edge detector O2.

In this embodiment, the integration module 301 includes a current source 501, a switch control unit 504, a clear switch 503, and an integration unit 502.

The switch control unit 504 comprises an OR gate OR2, the clear switch 503 comprises a normally open switch S2, the integrating unit 502 comprises an integrating capacitor C2, a first input end of the OR gate OR2 is a first input end of the switch control unit 504 and is used for receiving a Pulse signal Pulse a, a second input end of the OR gate OR2 is a second input end of the switch control unit 504 and is used for receiving a primary side conduction signal PWM on, an output end of the OR gate OR2 is connected with a control end of the clear switch 503, a normally closed contact of the clear switch 503, a first end of the integrating capacitor and an output end of the current source 501 are connected to the signal comparing module 302 in common, and a normally open contact of the clear switch 503 and a second end of the integrating capacitor C2 are connected to the ground in common.

In this embodiment, the signal comparing module 302 includes a comparator a5 and a duration configuration unit P, and the duration configuration unit P may be coupled to the resistor R1 for setting the window time length, i.e. the preset duration.

When the drain-source voltage is above the drain-source voltage (characterized by Vds _ s) within the window time (characterized by the time reference signal Ref 3)When the rising amplitude exceeds a rising threshold (represented by V1) OR the falling amplitude exceeds a falling threshold (represented by V2), the integration control module 303 outputs a Pulse signal Pulse a at a high level, and the OR gate OR2 outputs a high level to turn on the clear switch S2, and the integrated signal Vc2 is cleared. If the rising amplitude of the drain-source voltage does not exceed the rising threshold or the falling amplitude does not exceed the falling threshold within the window time, the integration control module 303 does not output the pulse signal, the integrated signal Vc2 rises to be higher than the time reference signal, and the comparator 5 outputs the primary side conducting signal PWM on of high level. While the OR2 outputs a high level for clearing the integrated signal Vc 2. In the illustrated embodiment, the OR2 is further coupled to a comparator circuit a1, which signals when the drain-source voltage is less than a first threshold

And controlling the integral signal to be cleared.

A non-inverting input terminal of the comparator a5 is connected to the output terminal of the integration module 301, an inverting input terminal of the comparator a5 is connected to the first terminal of the duration configuration unit P for inputting the time reference signal, an output terminal of the comparator a5 is the output terminal of the signal comparison module 302, a second terminal of the duration configuration unit P is coupled to the first terminal of the resistor Rcf, and a second terminal of the resistor Rcf is grounded.

Specifically, the specific structure of the second comparison circuit 202 is as follows:

the second comparing circuit 202 includes a comparator a2, a non-inverting input terminal of the comparator a2 inputs the second threshold reference signal Ref2, an inverting input terminal of the comparator a2 is connected to the sampling circuit 207 for inputting the drain-source voltage, and an output terminal of the comparator a2 is connected to a second input terminal of the turn-on control circuit 203.

Specifically, the specific structure of the on-control circuit 203 is as follows:

the conduction control circuit 203 comprises an AND gate AND1 AND a second flip-flop 206, wherein a first input terminal of the AND gate AND1 is coupled to an output terminal of the second flip-flop 206, a second input terminal of the AND gate AND1 is a second input terminal of the conduction control circuit 203, AND an output terminal of the AND gate AND1 is an output terminal of the conduction control circuit 203.

Specifically, the sampling circuit 207, the shutdown control circuit 204, the first flip-flop circuit 205, and the second flip-flop circuit 206 have the following specific structures:

the sampling circuit 207 includes a resistor R1 and a resistor R2, the turn-OFF control circuit 204 includes a turn-OFF control OFF, the first flip-flop circuit 205 includes a flip-flop T1, and the second flip-flop circuit 206 includes a flip-flop T2.

The first end of the resistor R1 is grounded, the second end of the resistor R1 AND the first end of the resistor R2 are connected in common as the output end of the sampling circuit 207, the second end of the resistor R2 AND the drain of the synchronous rectification switch 10 can be connected in common with the secondary winding, the first end of the OFF controller OFF is connected with the output end of the sampling circuit 207 to input sampling voltage, the second end of the OFF controller OFF is connected with the reset end R of the trigger T1, the set end S of the trigger T1 is connected with the output end of the AND gate AND1, AND the output end Q of the trigger T1 is connected with the gate of the synchronous rectification switch 10. The reset terminal R of the flip-flop T2 is connected to the output terminal of the flip-flop T1, the set terminal S of the flip-flop T2 is connected to the output terminal of the comparator a5, and the output terminal Q of the flip-flop T2 is connected to the first input terminal of the conduction control circuit 203.

The following describes the main operation of the synchronous rectification control circuit 20 based on the above specific device structure:

in the case that the voltage Vds _ S output by the sampling circuit 207 is constant, referring to fig. 7, initially, the initial value of Vds _ hold is 0, and as the drain-source voltage rises rapidly, Vds _ S-V1 > Vds _ hold, the comparator A3 outputs a high voltage OR gate OR1 to generate a Pulse signal Pulse a, and the voltage holding unit 401 composed of the normally-open switch S1 and the capacitor C1 performs sampling, so that Vds _ hold is equal to Vds _ S. After that, the drain-source voltage is kept constant or changes little, neither comparator A3 nor comparator a4 will act, and the Pulse signal Pulse a will remain low. Current source 501I1 charges integrating capacitor C2, and after a period of time (t ═ Ref3 × C2/I1), the voltage at C2 will be higher than Ref3, comparator a5 outputs a high voltage, and comparator a5 outputs an active high level pulse PWM on.

In the case that Vds _ s output by the sampling circuit 207 is continuously changed, referring to fig. 8, when Vds _ s increases by V1, the comparator A3 is triggered to output a high level, so that the OR gate OR1 generates a Pulse signal Pulse a; when Vds _ s is reduced by V2, comparator A4 is triggered to output high level, so that OR gate OR1 generates Pulse signal Pulse A. The Pulse signal Pulse a is continuously generated, so that the integrated voltage on the integrating capacitor C2 cannot continuously increase, and therefore the comparator a5 cannot output an active high-level Pulse PWM-on.

When the comparator a5 outputs an active high level pulse PWM-on, the flip-flop T2 is used to maintain the high level, AND if the comparator a2 detects that the drain-source voltage is less than the second threshold value AND outputs a high level, the AND gate AND1 controls the flip-flop T1 to output a high level switch control signal PWM to control the synchronous rectification switch 10 to be turned on. The high level of the switch control signal PWM is used to reset the flip-flop T2 until a valid primary side conduction signal is again received.

It should be noted that the division of each circuit in the synchronous rectification control circuit is only used for illustration, and in other embodiments, the synchronous rectification control circuit may be divided into different circuits as needed to complete all or part of the functions of the synchronous rectification control circuit.

Referring to fig. 9, fig. 9 is a structural diagram of an isolated voltage converting circuit according to an embodiment.

As shown in fig. 9, the voltage converting circuit includes a synchronous rectification switch 10, a synchronous rectification control circuit 20 according to the above embodiment, an energy storage element 30, and a primary side switch 40.

The energy storage element 30 includes a primary winding and a secondary winding; the primary side switch 40 is electrically coupled to the primary side winding of the energy storage element 30; the synchronous rectification switch 10 is coupled to the secondary winding of the energy storage element 30. Wherein the energy storage element 30 may be a transformer.

In an embodiment, referring to fig. 10, a first output terminal of the secondary winding is connected to the first terminal of the output capacitor Cout and the Load, a second output terminal of the secondary winding and the drain of the synchronous rectification switch 10 are commonly connected to the input terminal of the control circuit, a source of the synchronous rectification switch 10 and the second terminal of the output capacitor Cout are commonly connected to the ground, and a gate of the synchronous rectification switch 10 is connected to the control terminal of the control circuit according to the above embodiment.

In the voltage conversion circuit provided by this embodiment, the synchronous rectification control circuit 20 can accurately determine the on-time of the synchronous rectification switch 10 according to the state of the primary side switch 40 and the magnitude of the drain-source voltage of the synchronous rectification switch 10, so that when it is detected that the primary side switch 40 is in the on-state and the drain-source voltage of the synchronous rectification switch 10 is smaller than the second threshold, the synchronous rectification switch 10 is accurately controlled to be turned on and off, and the power efficiency is improved.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A synchronous rectification control circuit is connected with a secondary side synchronous rectification switch, and is characterized by comprising:

2. The circuit of claim 1, wherein the detection circuit is further configured to determine that the drain-source voltage is in the plateau period when it is detected that a rising slope of the drain-source voltage is smaller than a rising slope threshold and a falling slope of the drain-source voltage is smaller than a falling slope threshold within the preset time.

3. The circuit of claim 1, wherein the detection circuit is further configured to determine that the drain-source voltage is in a plateau period when it is detected within the preset time that the rising amplitude of the drain-source voltage does not exceed a rising threshold and the falling amplitude of the drain-source voltage does not exceed a falling threshold.

4. The circuit of claim 1, wherein the synchronous rectification control circuit is coupled to a resistor or a capacitor, and the preset time is set by the resistor or the capacitor.

5. The circuit of claim 1, wherein the detection circuit comprises:

6. The circuit of claim 5, wherein the first comparison circuit is connected to the integration module or the signal comparison module, and further configured to control the integration module to clear the integration signal or control the signal comparison module to stop operating when the drain-source voltage is smaller than the first threshold.

7. The circuit of claim 5, wherein the integral control module comprises:

8. The circuit of claim 5, wherein the integration module comprises:

9. The circuit of any one of claims 1-8, further comprising:

10. The circuit of claim 9, further comprising:

11. The circuit of any one of claims 1-8, further comprising:

12. An isolated voltage conversion circuit, comprising:

the energy storage element comprises a primary winding and a secondary winding;

a circuit as claimed in any one of claims 1 to 8.