CN211792040U - Optimizing earphone in-place detection circuit - Google Patents

Optimizing earphone in-place detection circuit Download PDF

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Publication number
CN211792040U
CN211792040U CN201922499266.6U CN201922499266U CN211792040U CN 211792040 U CN211792040 U CN 211792040U CN 201922499266 U CN201922499266 U CN 201922499266U CN 211792040 U CN211792040 U CN 211792040U
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earphone
circuit
level
level shift
detection circuit
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CN201922499266.6U
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杨维国
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Shanghai Shuguo Technology Co ltd
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Shanghai Shuguo Technology Co ltd
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Abstract

The utility model discloses an optimize earphone detection circuitry on throne, connect detection circuitry including the earphone, it still includes level shift circuit, DET pin in level shift circuit and the earphone connection detection circuitry, level shift circuit connects the earphone identification system on throne. The utility model provides an earphone is detection circuitry on throne through increasing level shift circuit in "DET" signal path, improves the high level of signal voltage amplitude, and more accurate can make the judgement that the earphone extracted.

Description

Optimizing earphone in-place detection circuit
Technical Field
The utility model relates to a detection circuitry technical field, concretely relates to optimize earphone detection circuitry on throne.
Background
Along with the continuous development of the public network intercom industry, the requirement on the function of the public network intercom is higher and higher, from the traditional handheld conversation to the earphone conversation, more and more scenes need earphone conversation modes to be carried out, and the earphone sound volume in the earphone conversation of a specific scene has higher requirements, such as restaurants, KTV and other application scenes, the intercom must be carried out by using the earphone, the restaurant and the KTV scenes are noisy, and the requirement on the volume of the intercom earphone must be high.
In public network talkback, the earphone call is started after the earphone is identified to insert through the earphone detection circuit, and the in-place detection of the earphone is identified according to the terminal pin.
As shown in fig. 1, it shows a detection schematic diagram of a conventional earphone detection circuit.
As can be seen from the figure, after the earphone is inserted, the pin DET is connected with the pin L, the pin L is the left channel of the earphone, and the left channel is connected with the earphone speaker and GND to form a loop.
The level domain of a conventional DET pin is DC1.8V, after the earphone is inserted, the DET is pulled down from a high level, the system recognizes that the low level is converted into an earphone mode, an L pin can pass through an audio signal, the amplitude of the L pin signal can be increased to obtain higher volume, the amplitude of the signal can exceed DC1.4V at certain audio frequency points, the 1.4V system can be considered as the high level for GPIO, when the DET pin is the high level, the system can recognize that the earphone is pulled out and is converted into a handheld mode, and the earphone can not be normally used under the condition.
Therefore, how to improve the reliability of the earphone in-place detection scheme is an urgent problem to be solved in the field.
SUMMERY OF THE UTILITY MODEL
In view of the reliability problem of the existing earphone in-place detection scheme, a new earphone in-place detection scheme is needed.
Therefore, the utility model aims to provide an optimize earphone detection circuit on throne to improve the earphone reliability of detection on throne.
In order to achieve the above object, the utility model provides an optimize earphone detection circuitry on throne, including earphone connection detection circuitry, it still includes level shift circuit, DET pin connection in level shift circuit and the earphone connection detection circuitry, level shift circuit connects the earphone identification system on throne.
Further, the level conversion circuit is composed of a level conversion IC.
The utility model provides an earphone detection circuitry on throne through increasing a level shift circuit in "DET" signal circuit, can improve the high level of signal voltage amplitude, raises the threshold value of the high voltage of discernment, can be accurate make the judgement that the earphone extracted to improve the earphone reliability of detection on throne.
Drawings
The invention will be further explained with reference to the drawings and the detailed description
Fig. 1 is a schematic diagram of a conventional earphone in-place detection circuit;
fig. 2 is a schematic diagram of an in-place detection circuit of the earphone according to an embodiment of the present invention;
fig. 3 is a diagram illustrating an exemplary configuration of a level shift circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical means, creation features, achievement purposes and functions of the present invention easy to understand and understand, the present invention is further explained by combining with the specific drawings.
In the embodiment, the DET signal is detected in the earphone, the earphone detection signal is designed for realizing the on-position detection of the earphone, the system acquires the confirmation of the on-position state of the earphone through the level monitoring of the signal, the earphone is in no-position or pulled out at high level, and the earphone is in the on-position state at low level. A level conversion circuit is added in the path to raise the high level of the signal voltage amplitude, so that the reliability of the earphone on-site detection is improved.
Referring to fig. 2, a schematic diagram of the earphone presence detection circuit in this example is shown. As can be seen from the figure, the earphone presence detection circuit in the present embodiment mainly includes a level shift circuit 100 and an earphone connection detection circuit 200.
The earphone connection detection circuit 200 provides a connection point with the earphone, and provides an MC + pin, a GND pin, an R pin, a DET pin, and an L pin to form a corresponding connection point for connecting and detecting the earphone 300.
The earphone connection detection circuit 200 is constructed by conventional techniques, and will not be described herein.
The present example further provides the level shift circuit 100 in the "DET" signal path of the DET pin in the headset connection detection circuit 200, and the headset presence identification system 400 is connected by the level shift circuit 100.
The level shift circuit 100 takes a level shift IC as a core, and signal communication under different voltages is realized by adding different dc voltages to the input and output terminals.
The specific structure of the level conversion IC can be determined according to actual requirements, the output end of the level conversion IC supplies the same voltage as the system IO domain, the input end of the level conversion IC adopts 2.8VDC power supply, and signals below 2.3V can be guaranteed, so that the DET signal is identified as '0' by the system.
Therefore, in specific application, the level conversion circuit 100 formed by the level conversion IC converts a 1.8V DC power domain in a common circuit into a 2.8V DC power domain, and the signal amplitude is increased from 1.3V to a high level triggered by about 2.4V, so as to optimize earphone detection.
The following illustrates the application process of the present earphone presence detection circuit.
The earphone is identified by the earphone in-place identification system through the high-low level of the 'DET' GPIO signal, the conventional 'DET' GPIO pin of the system is a digital circuit, the conventional high level is 1, the low level is 0, the conventional power domain of the 'DET' GPIO is DC1.8V, and the lower limit voltage of the high level is DC1.4V.
Accordingly, in this example, by adding the level shift circuit in the "DET", the left side of the level shift circuit is the system side, the high level threshold is identified as DC1.4V, and the right side is the connection point between the level shift IC and the headphone, and by adding DC2.8V to the input terminal of the level shift IC, the threshold for identifying the high voltage on the right side is raised, e.g., the VCC power supply is DC2.8V, and the identified high voltage threshold is DC2.4V, i.e., when the VCC power supply is 2.8V, the high level can be detected by the system only when the "L" channel signal reaches 2.4V, and the headphone pull-out determination is made (as shown in fig. 3).
In addition, a safety protection circuit can be added on the level conversion IC according to the requirement, so that the safety of the whole scheme is further improved.
In addition, an alarm circuit can be additionally arranged on the level conversion IC according to needs, and an alarm is given out when the circuit fails, so that the reliability of the whole circuit is improved.
The configuration of the safety protection circuit and the alarm circuit and the arrangement of the safety protection circuit and the alarm circuit in cooperation with the level shift IC are determined according to actual requirements, and are not limited herein. For example, existing robust solutions may be used, which are well known to those skilled in the art and will not be described in detail here.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (2)

1. An optimized earphone in-place detection circuit comprises an earphone connection detection circuit and is characterized by further comprising a level conversion circuit, wherein the level conversion circuit is connected with a DET pin in the earphone connection detection circuit, and the level conversion circuit is connected with an earphone in-place recognition system.
2. The optimized headset on-bit detection circuit of claim 1, wherein the level shifting circuit is comprised of a level shifting IC.
CN201922499266.6U 2019-12-31 2019-12-31 Optimizing earphone in-place detection circuit Active CN211792040U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201922499266.6U CN211792040U (en) 2019-12-31 2019-12-31 Optimizing earphone in-place detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201922499266.6U CN211792040U (en) 2019-12-31 2019-12-31 Optimizing earphone in-place detection circuit

Publications (1)

Publication Number Publication Date
CN211792040U true CN211792040U (en) 2020-10-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201922499266.6U Active CN211792040U (en) 2019-12-31 2019-12-31 Optimizing earphone in-place detection circuit

Country Status (1)

Country Link
CN (1) CN211792040U (en)

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GR01 Patent grant
GR01 Patent grant
PE01 Entry into force of the registration of the contract for pledge of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of utility model: An optimized earphone in place detection circuit

Effective date of registration: 20211217

Granted publication date: 20201027

Pledgee: Societe Generale Bank Co.,Ltd. Qingpu Branch of Shanghai

Pledgor: SHANGHAI SHUGUO TECHNOLOGY Co.,Ltd.

Registration number: Y2021310000141

PC01 Cancellation of the registration of the contract for pledge of patent right
PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20221207

Granted publication date: 20201027

Pledgee: Societe Generale Bank Co.,Ltd. Qingpu Branch of Shanghai

Pledgor: SHANGHAI SHUGUO TECHNOLOGY Co.,Ltd.

Registration number: Y2021310000141