CN211790738U - CVBS input/output protection circuit, CVBS interface, reversing image system and vehicle - Google Patents
CVBS input/output protection circuit, CVBS interface, reversing image system and vehicle Download PDFInfo
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- CN211790738U CN211790738U CN201922119097.9U CN201922119097U CN211790738U CN 211790738 U CN211790738 U CN 211790738U CN 201922119097 U CN201922119097 U CN 201922119097U CN 211790738 U CN211790738 U CN 211790738U
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Abstract
The disclosure relates to a CVBS input/output protection circuit, a CVBS interface, a reversing image system and a vehicle. By using the NMOS tube, the grid G of the NMOS tube is connected with a fixed voltage VCC, the source S is connected with the matching resistor R in series and then is grounded, the fixed voltage is larger than the starting voltage of the NMOS tube, and then the NMOS tube is always started. And the CVBS input end (100) is connected with the drain electrode D of the NMOS tube, and the CVBS output end (200) is arranged between the source electrode of the NMOS tube and the matching resistor, so that a CVBS input signal can be input to the CVBS output end through the CVBS input end. The voltage of the matching resistor is equal to the source voltage of the NMOS tube, and the source voltage of the NMOS tube is clamped below the fixed voltage minus the starting voltage of the NMOS tube. Therefore, according to the technical scheme provided by the disclosure, the matching resistor at the inlet of the CVBS can be a resistor with smaller rated power through the ingenious integration and design of the NMOS tube and the matching resistor.
Description
Technical Field
The utility model relates to a CVBS technical field, specifically, relate to a CVBS input/output protection circuit, CVBS interface, image system and vehicle of backing a car.
Background
At present, most automobiles are equipped with a reverse image function, and most of the reverse cameras used in the automobiles are CVBS (Composite Video Broadcast Signal or Composite Video Blanking and Sync, Composite synchronous Video Broadcast Signal or Composite Video Blanking and synchronization) interfaces. According to the CVBS specification, a 75 ohm matched resistor must be placed at the inlet of the CVBS, and the CVBS signal line is usually tied to the car wiring harness and may be shorted to the 12V or 24V voltage of the car. When the short circuit is short-circuited to 12V voltage, 12^2/75 ^ 1.92 watts of power is generated on a 75-ohm resistor, and the resistor with larger rated power needs to be selected, namely at least the resistor of a 2512 package is selected. If the voltage is 24V of a commercial vehicle, 24^2/75 ^ 7.68 watts of power is generated, the power cannot be consumed by the resistor per se at all, and an additional protection circuit is needed.
Disclosure of Invention
The invention aims to provide a CVBS input and output protection circuit, a CVBS interface, a reversing image system and a vehicle, and aims to solve the problem that the rated power of a matching resistor at an inlet of the CVBS is large.
In order to achieve the above object, an embodiment of the present disclosure provides a CVBS input/output protection circuit, including an NMOS transistor and a matching resistor;
the grid electrode of the NMOS tube is connected with a fixed voltage, the source electrode of the NMOS tube is connected with the matching resistor in series and then is grounded, and the drain electrode of the NMOS tube is connected with the input end of the CVBS, wherein the fixed voltage is greater than the starting voltage of the NMOS tube;
the CVBS output end is arranged between the source electrode of the NMOS tube and the matching resistor.
Optionally, the CVBS input-output protection circuit further includes a diode;
and the anode of the diode is connected with the source electrode of the NMOS tube, and the cathode of the diode is connected with the drain electrode of the NMOS tube.
Optionally, the CVBS input-output protection circuit further includes a transient suppression diode;
the transient suppression diode is connected between the grid electrode and the source electrode of the NMOS tube in parallel.
Optionally, the CVBS input-output protection circuit further includes a capacitor;
one end of the capacitor is connected with the source electrode of the NMOS tube, and the other end of the capacitor is connected with the CVBS input end.
Optionally, the type of the capacitor is 100 nf/16V.
Optionally, the fixed voltage has a value of 3.3V.
Optionally, the matching resistance is 0603 packaged 75 ohm resistance.
The embodiment of the disclosure also provides a CVBS interface, which includes the above CVBS input/output protection circuit.
The embodiment of the disclosure further provides a car backing image system, which includes the CVBS interface.
The embodiment of the disclosure also provides a vehicle, which includes the above CVBS interface.
According to the technical scheme, the NMOS tube is used, the grid electrode of the NMOS tube is connected with a fixed voltage, the source electrode of the NMOS tube is connected with the matching resistor in series and then is grounded, the fixed voltage is larger than the starting voltage of the NMOS tube, and then the NMOS tube is always started. And the CVBS input end is connected with the drain electrode of the NMOS tube, and the CVBS output end is arranged between the source electrode of the NMOS tube and the matching resistor, so that a CVBS input signal can be input to the CVBS output end (the source electrode of the NMOS tube) through the CVBS input end (the drain electrode of the NMOS tube). The voltage of the matching resistor is equal to the source voltage of the NMOS tube, and the source voltage of the NMOS tube is clamped below a fixed voltage minus the starting voltage of the NMOS tube. For example, when the fixed voltage is 3.3V and the turn-on voltage of the NMOS transistor is about 1V, the voltage of the matching resistor is equal to the source voltage of the NMOS transistor, which is about 2.3V. The power rating of the matching resistor needs to be only greater than 2.3^2/75 ^ 0.07W when the CVBS input is shorted to a voltage of 12V or 24V. Therefore, according to the technical scheme provided by the disclosure, the matching resistor at the inlet of the CVBS can be a resistor with smaller rated power through the ingenious integration and design of the NMOS tube and the matching resistor.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a circuit diagram of a CVBS input/output protection circuit according to an embodiment of the present disclosure.
Fig. 2 is a circuit diagram of another CVBS input/output protection circuit provided in an embodiment of the present disclosure.
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
As shown in fig. 1, an embodiment of the present disclosure provides a CVBS input-output protection circuit. The CVBS input and output protection circuit comprises an NMOS tube and a matching resistor R.
The grid G of the NMOS tube is connected with a fixed voltage VCC, the source S is connected with the matching resistor R in series and then is grounded, and the drain D is connected with the CVBS input end 100. The CVBS output 200 is disposed between the source S of the NMOS transistor and the matching resistor R.
And the fixed voltage VCC is greater than the starting voltage of the NMOS tube. The starting voltage of the NMOS tube is about 1V. The fixed voltage VCC may be 1.5V, 1.8V, 3.3V, 5V, or the like, which is not limited herein.
The technical scheme that this disclosure provided, through using the NMOS pipe, will the grid G of NMOS pipe is connected with a fixed voltage VCC, source S and matching resistance R ground connection after establishing ties, and makes fixed voltage VCC be greater than the turn-on voltage of NMOS pipe makes then the NMOS pipe is opened always. And the CVBS input terminal 100 is connected to the drain D of the NMOS transistor, and the CVBS output terminal 200 is disposed between the source S of the NMOS transistor and the matching resistor R, so that a CVBS input signal can be input to the CVBS output terminal 200 (the source S of the NMOS transistor) through the CVBS input terminal 100 (the drain D of the NMOS transistor). The voltage of the matching resistor R is equal to the source S voltage of the NMOS tube, and the source S voltage of the NMOS tube is clamped below the fixed voltage VCC minus the starting voltage of the NMOS tube. For example, when the fixed voltage VCC is 3.3V and the turn-on voltage of the NMOS transistor is about 1V, the voltage of the matching resistor R is equal to the source voltage S of the NMOS transistor and is about 2.3V. The power rating of the matching resistor R only needs to be greater than 2.3^2/75 ^ 0.07W when the CVBS input 100 is shorted to a voltage of 12V or 24V. Therefore, according to the technical scheme provided by the disclosure, the matching resistor R at the inlet of the CVBS can be a resistor with smaller rated power by skillfully integrating and designing the NMOS tube and the matching resistor R.
As shown in fig. 2, optionally, the CVBS input/output protection circuit further includes a diode VD. The anode of the diode VD is connected with the source S of the NMOS tube, and the cathode of the diode VD is connected with the drain D of the NMOS tube.
By providing the diode VD, an extra current path can be provided to protect the NMOS transistor from breakdown. When a large instantaneous reverse current is generated in the circuit, the current can be led out through the diode VD, and the NMOS tube is prevented from being broken down.
Optionally, the CVBS input-output protection circuit further includes a transient suppression diode TVS. The transient suppression diode TVS is connected in parallel between the grid G and the source S of the NMOS tube.
By arranging the transient suppression diode TVS, an extra current path can be provided to protect the NMOS transistor from breakdown. When an inductive element such as an inductor and a relay is present in a circuit (e.g., the CVBS output 200), a large voltage is induced by a sudden change of current, which may break down the NMOS transistor and burn out the circuit. By providing the transient suppression diode TVS to provide an extra current path, the NMOS transistor can be protected from breakdown. The transient suppression diode TVS is arranged to also play a role of voltage stabilization. When the transient suppression diode TVS works in a reverse bias state, the transient suppression diode TVS is almost equivalent to an open circuit and acts like a voltage regulator tube.
Optionally, the CVBS input-output protection circuit further includes a capacitor C. One end of the capacitor C is connected with the source S of the NMOS tube, and the other end of the capacitor C is connected with the CVBS input end 100.
By arranging the capacitor C, the capacitor C can play a role of blocking direct current, and direct current signals (such as direct current signals at the input end 100 of the CVBS) on the left side of the capacitor C are prevented from causing interference to the output end 200 of the CVBS.
Optionally, the type of the capacitor C is 100 nf/16V.
That is, the capacitance of the capacitor C is 100nf, and the rated voltage is 16V. According to experience, the capacitor C of the type is suitable for a CVBS input and output protection circuit in an automobile reversing image system.
Optionally, the fixed voltage VCC has a value of 3.3V.
When the fixed voltage VCC value is 3.3V, the fixed voltage VCC can be provided by the processor, namely the grid G of the NMOS tube is connected with the processor with the working voltage of 3.3V.
Optionally, the matching resistor R is a 0603 packaged 75 ohm resistor.
When the fixed voltage VCC is 3.3V, the starting voltage of the NMOS transistor is about 1V, the voltage of the matching resistor R is equal to the source S voltage of the NMOS transistor and is equal to about 2.3V, and the rated power of the matching resistor R only needs to be larger than 2.3^2/75 ^ 0.07W. 0603 is more suitable because the resistor of the package has a rated voltage of 0.1W, which is relatively close to 0.07W. In addition, the matching resistance R may also be a 75 ohm resistance of 0805 package, 1206 package, 1210 package, 1812 package, etc. The rated power of the 75 ohm resistor of the 0805 package is 0.125W, the rated power of the 75 ohm resistor of the 1206 package is 0.25W, the rated power of the 75 ohm resistor of the 1210 package is 1/3W, and the rated power of the 75 ohm resistor of the 1812 package is 0.5W.
Based on the inventive concept, the embodiment of the present disclosure further provides a CVBS interface. The CVBS interface comprises the CVBS input and output protection circuit.
Based on the inventive concept, the embodiment of the disclosure further provides a car backing image system. The reverse image system comprises the CVBS interface.
Based on the inventive concept, the embodiment of the present disclosure further provides a vehicle. The vehicle comprises the above described CVBS interface.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various combinations that are possible in the present disclosure are not described again.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (10)
1. A CVBS input/output protection circuit is characterized by comprising an NMOS tube and a matching resistor R;
the grid G of the NMOS tube is connected with a fixed voltage VCC, the source S is grounded after being connected with the matching resistor R in series, the drain D is connected with the CVBS input end (100), and the fixed voltage VCC is larger than the starting voltage of the NMOS tube;
the CVBS output end (200) is arranged between the source electrode S of the NMOS tube and the matching resistor R.
2. The CVBS input-output protection circuit according to claim 1, further comprising a diode VD;
the anode of the diode VD is connected with the source S of the NMOS tube, and the cathode of the diode VD is connected with the drain D of the NMOS tube.
3. The CVBS input-output protection circuit according to claim 2, further comprising a transient suppression diode TVS;
the transient suppression diode TVS is connected in parallel between the grid G and the source S of the NMOS tube.
4. The CVBS input-output protection circuit according to claim 3, further comprising a capacitor C;
one end of the capacitor C is connected with the source S of the NMOS tube, and the other end of the capacitor C is connected with the CVBS input end (100).
5. The CVBS input-output protection circuit of claim 4, wherein the capacitor C is 100nf/16V in size.
6. The CVBS input-output protection circuit of any one of claims 1-5, wherein the fixed voltage VCC has a value of 3.3V.
7. The CVBS input-output protection circuit of claim 6, wherein the matching resistor R is a 0603 packaged 75 ohm resistor.
8. A CVBS interface comprising the CVBS input-output protection circuit of any one of claims 1 to 7.
9. A reverse imaging system comprising the CVBS interface of claim 8.
10. A vehicle comprising the CVBS interface of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922119097.9U CN211790738U (en) | 2019-11-29 | 2019-11-29 | CVBS input/output protection circuit, CVBS interface, reversing image system and vehicle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922119097.9U CN211790738U (en) | 2019-11-29 | 2019-11-29 | CVBS input/output protection circuit, CVBS interface, reversing image system and vehicle |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211790738U true CN211790738U (en) | 2020-10-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922119097.9U Active CN211790738U (en) | 2019-11-29 | 2019-11-29 | CVBS input/output protection circuit, CVBS interface, reversing image system and vehicle |
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| Country | Link |
|---|---|
| CN (1) | CN211790738U (en) |
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- 2019-11-29 CN CN201922119097.9U patent/CN211790738U/en active Active
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