CN211741435U - Voltage pulse anti-interference degree testing device - Google Patents
Voltage pulse anti-interference degree testing device Download PDFInfo
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- CN211741435U CN211741435U CN201922184857.4U CN201922184857U CN211741435U CN 211741435 U CN211741435 U CN 211741435U CN 201922184857 U CN201922184857 U CN 201922184857U CN 211741435 U CN211741435 U CN 211741435U
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Abstract
The utility model discloses a voltage pulse interference immunity testing arrangement for electric property test, include: the signal source access unit is connected with the superposition unit and can access two voltage signals; the superposition unit is provided with two input ends, the two input ends are respectively connected with the two voltage signals, the output end of the superposition unit is connected with verified equipment or a verified mechanism, and the superposition unit is suitable for superposing the two voltage signals to enable the two voltage signals to form voltage waveforms required by the test standard. The first voltage signal accessed by the signal source access unit is a direct current voltage signal, and the second voltage signal accessed by the signal source access unit is a pulse voltage signal. The verification mechanism is an oscilloscope and is used for detecting whether the output of the superposition unit is the voltage waveform required by the test standard. The utility model discloses can satisfy GMW3172-20189.2.5 test standard requirement to can satisfy the test power requirement of most electron class automobile parts.
Description
Technical Field
The utility model relates to an electric field especially relates to a voltage pulse interference immunity testing arrangement for electric property test.
Background
The automobile electronic parts are necessarily subjected to various reliability tests in the development stage, including an electrical performance testing part. Wherein, one electrical performance test in the GMW3172 standard of the general automobile is as follows: pulse superposition voltage (GMW3172-20189.2.5) for verifying immunity of automotive electronics components to voltage pulses present on the battery power supply within normal operating voltage ranges. No dedicated equipment is currently available on the market to perform this test.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to provide a voltage pulse interference immunity testing arrangement that can satisfy GMW3172-20189.2.5 standard for electric property test uses.
In order to solve the technical problem, the utility model provides a voltage pulse interference immunity testing arrangement, include:
the signal source access unit SSU is connected with the superposition unit SU and can access two voltage signals;
and the superposition unit SU is provided with two input ends, the two input ends are respectively connected with the two voltage signals, the output end of the superposition unit SU is connected with verified equipment or a verified mechanism, and the superposition unit SU is suitable for superposing the two voltage signals to enable the two voltage signals to form voltage waveforms required by the test standard.
Optionally, the voltage pulse immunity testing apparatus is further improved, the first voltage signal accessed by the signal source access unit SSU is a direct current voltage signal, and the second voltage signal accessed is a pulse voltage signal.
Optionally, the voltage pulse anti-interference degree testing device is further improved, and the verification mechanism is an oscilloscope and is used for detecting whether the output of the superposition unit SU is a voltage waveform required by a test standard.
Optionally, the apparatus for testing the interference immunity of voltage pulses is further improved, and the superimposing unit includes:
an operational amplifier O, the output end Oout of which is used as the output end SUout of the superposition unit SU, and the first reference end V + and the second reference end V-of which are connected to ground;
a first resistor R1 having a first terminal serving as the second sub-terminal IN1-2 of the first input IN1 of the summing unit SU and a second terminal connected to the first input Oin1 of the operational amplifier O;
a second resistor R2, having a first terminal connected to the first input terminal Oin1 of the operational amplifier and serving as the first sub-terminal IN1-1 of the first input terminal IN1 of the summing unit SU, and a second terminal connected to the output terminal Oout of the operational amplifier;
a third resistor R3, having a first end connected to the second input IN2 of the superimposing unit SU and connected to ground, and a second end connected to the output of the operational amplifier Oout;
the first end of the fourth resistor R4 is connected to the first end of the third resistor R3, and the second end thereof is connected to the second input terminal Oin2 of the operational amplifier O.
Optionally, the voltage pulse immunity testing device is further improved, and the resistance value of the first resistor R1 ranges from 1K ohm to 20K ohm. Preferably, the first resistor R1 has a value of 10K ohms.
Optionally, the voltage pulse immunity testing device is further improved, and the resistance value of the second resistor R2 ranges from 1K ohm to 20K ohm. Preferably, the second resistor R2 has a value of 10K ohms.
Optionally, the voltage pulse immunity testing device is further improved, and the resistance value of the third resistor R3 ranges from 1K ohm to 20K ohm. Preferably, the third resistor R3 has a value of 10K ohms.
Optionally, the voltage pulse immunity testing device is further improved, and the resistance value of the fourth resistor R4 ranges from 1 ohm to 200 ohms. Preferably, the fourth resistor R4 has a resistance of 100 ohms.
The utility model discloses a use as follows:
the direct-current voltage signal source is accessed to a first path of the signal source access unit SSU, and the pulse voltage signal source is accessed to a second path of the signal source access unit SSU. The direct voltage signal of the first path of the signal source connection unit SSU is connected to the first sub-terminal IN1-1 and the second sub-terminal IN1-2 of the first input IN1 of the superimposing unit SU, respectively. The second path pulse voltage signal of the signal source access unit SSU is connected to the second input IN2 of the superimposing unit SU. And the superposition unit SU modulates the direct-current voltage signal by using the pulse voltage signal to form a voltage waveform meeting the test standard requirement of GMW 3172-20189.2.5. Connecting the output end of the superposition unit SU with an oscilloscope, verifying whether the voltage waveform meets the requirement, if not, adjusting the input pulse voltage signal to input the superposition unit SU again until the voltage waveform meets GMW3172-2018
9.2.5 test standard requirements. Then, the oscilloscope is disconnected, and the verified equipment is connected with the output end of the superposition unit SU to execute verification test on the verified equipment. The utility model discloses a predetermine pulse voltage signal modulation DC voltage, insert the stack circuit when two signal sources, can export stable voltage waveform, can accomplish full-automatic test. The utility model discloses the maximum current of output can reach 5A, can satisfy GMW3172-20189.2.5 test standard requirement to can satisfy the test power requirement of most electron class automobile parts.
Drawings
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings:
fig. 1 is a schematic structural diagram of a practical embodiment of the voltage pulse anti-interference testing apparatus of the present invention.
Fig. 2 is a schematic structural diagram of a possible embodiment of the stacking unit of the present invention.
Description of the reference numerals
Signal source access unit SSU
Two voltage signals SSU1 and SSU2
Superposition unit SU
Oscilloscope 0S
Verified device VD
First to fourth resistors R1 to R4
Operational amplifier O
Operational amplifier output terminal Oout
SUout of the output terminal of the superposition unit
Operational amplifier first input terminal Oin1
Second input terminal Oin2 of operational amplifier
First reference end V + of operational amplifier
Second reference terminal V-
First input IN1 of the superimposing unit
First sub-terminal IN1-1 of first input terminal of superimposing unit
Second input IN2 of the superimposing unit
Second sub-terminal IN1-2 of the second input terminal of the superimposing unit
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure of the present invention. The utility model discloses can also implement or use through different embodiment, each item detail in this specification can also be used based on different viewpoints, carries out various decorations or changes under the general design thought that does not deviate from the utility model. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers (e.g., "between … …" and "directly between … …", "adjacent to … …" and "directly adjacent to … …", "on … …" and "directly on … …", etc.) should be interpreted in the same manner.
As shown in fig. 1, the utility model provides a voltage pulse interference immunity testing arrangement a feasible embodiment, include:
the signal source access unit SSU is connected with the superposition unit SU and can access two voltage signals SSU1 and SSU 2;
and the superposition unit SU is provided with two input ends, the two input ends are respectively connected with the two voltage signals SSU1 and SSU2, the output end of the superposition unit SU is connected with the verified device VD or the verified mechanism, and the superposition unit SU is suitable for superposing the two voltage signals to enable the two voltage signals to form voltage waveforms required by the test standard.
The first voltage signal SSU1 accessed by the signal source access unit SSU is a dc voltage signal, and the accessed second voltage signal SSU2 is a pulse voltage signal. The verification mechanism is an oscilloscope OS and is used for detecting whether the output of the superimposing unit SU is a voltage waveform required by a test standard.
Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
Spatially relative terms, such as "below … …," "above … …," "below," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's spatial relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As shown in fig. 2, a possible embodiment of the stacking unit of the present invention includes:
an operational amplifier O, the output end Oout of which is used as the output end SUout of the superposition unit SU, and the first reference end V + and the second reference end V-of which are connected to ground;
a first resistor R1 having a first terminal serving as the second sub-terminal IN1-2 of the first input IN1 of the summing unit SU and a second terminal connected to the first input Oin1 of the operational amplifier O;
a second resistor R2, having a first terminal connected to the first input terminal Oin1 of the operational amplifier and serving as the first sub-terminal IN1-1 of the first input terminal IN1 of the summing unit SU, and a second terminal connected to the output terminal Oout of the operational amplifier;
a third resistor R3, having a first end connected to the second input IN2 of the superimposing unit SU and connected to ground, and a second end connected to the output of the operational amplifier Oout;
the first end of the fourth resistor R4 is connected to the first end of the third resistor R3, and the second end thereof is connected to the second input terminal Oin2 of the operational amplifier O.
Wherein the resistance value of the first resistor R1 ranges from 1K ohm to 20K ohm. Preferably, the first resistor R1 has a value of 10K ohms.
The resistance of the second resistor R2 ranges from 1K ohm to 20K ohm. Preferably, the second resistor R2 has a value of 10K ohms.
The third resistor R3 has a resistance value in the range of 1K ohm-20K ohm. Preferably, the third resistor R3 has a value of 10K ohms.
The fourth resistor R4 has a resistance value in the range of 1 ohm-200 ohms. Preferably, the fourth resistor R4 has a resistance of 100 ohms.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these should not be construed as limitations of the present invention. Numerous variations and modifications can be made by those skilled in the art without departing from the principles of the invention, which should also be considered as within the scope of the invention.
Claims (12)
1. The utility model provides a voltage pulse interference immunity testing arrangement which characterized in that includes:
a signal source access unit (SSU) which is connected with the Superposition Unit (SU) and can access two voltage signals;
and the Superposition Unit (SU) is provided with two input ends, the two input ends are respectively connected with the two voltage signals, the output end of the superposition unit is connected with verified equipment or a verified mechanism, and the superposition unit is suitable for superposing the two voltage signals to enable the two voltage signals to form voltage waveforms required by the test standard.
2. The voltage pulse immunity test apparatus of claim 1, wherein: the first voltage signal accessed by the signal source access unit (SSU) is a direct current voltage signal, and the second voltage signal accessed by the signal source access unit (SSU) is a pulse voltage signal.
3. The voltage pulse immunity test apparatus of claim 1, wherein: the verification mechanism is an oscilloscope and is used for detecting whether the output of the Superposition Unit (SU) is a voltage waveform required by a test standard.
4. The voltage pulse immunity test apparatus of claim 2, wherein: the superimposing unit includes:
an operational amplifier (O) having an output (Oout) as the output (SUout) of the Superposition Unit (SU), and a first reference terminal (V +) and a second reference terminal (V-) connected to ground;
a first resistor (R1) having a first terminal serving as the second sub-terminal (IN1-2) of the first input terminal (IN1) of the Superimposing Unit (SU) and a second terminal connected to the first input terminal (Oin1) of the operational amplifier (O);
a second resistor (R2) having a first terminal connected to the first input terminal (Oin1) of the operational amplifier and serving as a first sub-terminal (IN1-1) of the first input terminal (IN1) of the Superimposing Unit (SU), and a second terminal connected to the output terminal (Oout) of the operational amplifier;
a third resistor (R3) having a first terminal connected IN parallel to the second input terminal (IN2) of the Superimposing Unit (SU) and a second terminal connected to the output terminal (Oout) of the operational amplifier;
and a fourth resistor (R4) having a first terminal connected to the first terminal of the third resistor (R3) and a second terminal connected to the second input terminal (Oin2) of the operational amplifier (O).
5. The voltage pulse immunity test apparatus of claim 4, wherein: the first resistor (R1) has a resistance value in the range of 1K ohm-20K ohm.
6. The voltage pulse immunity test apparatus of claim 5, wherein: the first resistor (R1) has a value of 10K ohms.
7. The voltage pulse immunity test apparatus of claim 4, wherein: the second resistor (R2) has a resistance value in the range of 1K ohm-20K ohm.
8. The voltage pulse immunity test apparatus of claim 7, wherein: the second resistor (R2) has a value of 10K ohms.
9. The voltage pulse immunity test apparatus of claim 4, wherein: the third resistor (R3) has a resistance value in the range of 1K ohm-20K ohm.
10. The voltage pulse immunity test apparatus of claim 9, wherein: the third resistor (R3) has a value of 10K ohms.
11. The voltage pulse immunity test apparatus of claim 4, wherein: the fourth resistor (R4) has a resistance value in the range of 1 ohm-200 ohms.
12. The voltage pulse immunity test apparatus of claim 11, wherein: the fourth resistor (R4) has a resistance of 100 ohms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922184857.4U CN211741435U (en) | 2019-12-09 | 2019-12-09 | Voltage pulse anti-interference degree testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922184857.4U CN211741435U (en) | 2019-12-09 | 2019-12-09 | Voltage pulse anti-interference degree testing device |
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| Publication Number | Publication Date |
|---|---|
| CN211741435U true CN211741435U (en) | 2020-10-23 |
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| CN201922184857.4U Active CN211741435U (en) | 2019-12-09 | 2019-12-09 | Voltage pulse anti-interference degree testing device |
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