CN211718733U - Enhanced general radar data acquisition unit - Google Patents
Enhanced general radar data acquisition unit Download PDFInfo
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- CN211718733U CN211718733U CN202020225779.8U CN202020225779U CN211718733U CN 211718733 U CN211718733 U CN 211718733U CN 202020225779 U CN202020225779 U CN 202020225779U CN 211718733 U CN211718733 U CN 211718733U
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Abstract
The utility model discloses an enhanced general radar data collector, which comprises a FPGA chip, an ARM chip, a high-speed radar signal sampling interface and a low-speed analog signal sampling interface; data interaction is realized between the FPGA chip and the ARM chip through a double-port RAM; the high-speed radar signal sampling interface comprises a single-ended interface, an input conditioning circuit and an 80M high-speed AD. The high-speed radar signal sampling interface can sample intermediate frequency signals, positive video signals or negative video signals within the range of 80M and above sampling rate. The low-speed analog signal sampling interface is used for sampling a 120KHz low-speed ADC (analog to digital converter), can collect voltage signals and current signals with adjustable ranges, and comprises a sampling chip, a capacitor, nine welding jumping points, ten welding jumping points, eleven welding jumping points and a sampling signal terminal. When this application is integrated FPGA chip and ARM chip, can dock signals and the control interface of multiple sensor equipment such as radar, meteorological hydrology, accomplish data integration and unified control.
Description
Technical Field
The invention relates to a radar data acquisition device, in particular to an enhanced universal radar data acquisition device.
Background
The existing radar data collector usually only has an FPGA chip or only an ARM chip. When only the FPGA is used as a core chip, data acquisition can be carried out in parallel at a high speed, but complex floating point operation or control and display functions are lacked, and the FPGA is not good at completing the functions. On the contrary, if only the ARM is used as a core chip, rich functions can be realized, but the acquisition of high-speed parallel sensor data such as radar and the like cannot be realized. Therefore, the FPGA chip and the ARM chip are organically combined, and the method has important significance.
In addition, in various supervisory systems such as ship navigation, volunteer ship-borne detection equipment, shore-based radar monitoring stations and the like, access and comprehensive processing of data of one or more sensors such as radar, meteorological hydrology, positioning and time service and the like are generally required to be realized, and part of equipment also needs to be controllable. The existing sensor equipment such as radar and meteorological hydrology has various brands and models, equipment which needs to be accessed under different application occasions is not identical, the development and customization of the supervision system are too strong, and a large amount of manpower and cost investment are often needed.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide an enhanced general radar data collector, which integrates an FPGA chip and an ARM chip and simultaneously can interface signals and control interfaces of various sensor devices such as radar and meteorological hydrology to complete data integration and unified control.
In order to solve the technical problems, the invention adopts the technical scheme that:
an enhanced general radar data collector comprises an FPGA chip, an ARM chip and a high-speed radar signal sampling interface.
And data interaction between the FPGA chip and the ARM chip is realized through the double-port RAM. The FPGA chip is used for processing high-speed parallel radar signals, and the ARM chip is used for processing collected sensor signals and fusing the radar signals processed by the FPGA.
The high-speed radar signal sampling interface is arranged on the FPGA chip and comprises a single-ended interface, an input conditioning circuit and an 80M high-speed AD. The output end of the 80M high-speed AD is connected with the FPGA chip, and the input end of the 80M high-speed AD is connected with the differential interface.
The output end of the input conditioning circuit is connected with the differential interface through a welding jumping point five and a welding jumping point six. And one path of an input positive end of the input conditioning circuit is connected with the single-end interface through a welding jumping point I, and the other path of the input positive end of the input conditioning circuit is grounded through a welding jumping point III. One path of the input negative end of the input conditioning circuit is connected with the single-end interface through a welding jumping point two, and the other path of the input conditioning circuit is grounded through a welding jumping point four.
And selectively welding corresponding resistors and resistance values at a first welding jump point, a second welding jump point, a third welding jump point, a fourth welding jump point, a fifth welding jump point and a sixth welding jump point according to requirements, thereby realizing the acquisition of the intermediate frequency signals and the video signals.
And when the acquired high-speed radar signal is an intermediate-frequency signal, disconnecting the welding trip point five and the welding trip point six. When the collected high-speed radar signal is a positive video signal, 0 ohm resistors are welded at the first welding jump point, the fourth welding jump point, the fifth welding jump point and the sixth welding jump point, the second welding jump point is disconnected, and 50 ohm-ground resistors are welded at the third welding jump point. When the acquired high-speed radar signal is a negative video signal, the first welding jump point is disconnected, 0 ohm resistors are welded at the second welding jump point, the third welding jump point, the fifth welding jump point and the sixth welding jump point, and 50 ohm-to-ground resistors are welded at the four welding jump points.
The low-speed analog signal sampling interface is connected with the FPGA chip and used for acquiring adjustable voltage signals and current signals. The low-speed analog signal sampling interface comprises a sampling chip, a capacitor, a welding trip point nine, a welding trip point ten, a welding trip point eleven and a sampling signal terminal. The sampling signal terminal is connected with the input end of the sampling chip through a welding jumping point nine, and the output end of the sampling chip is grounded through a welding jumping point eleven. And two ends of the capacitor are respectively connected with the input end and the output end of the sampling chip. One end of the welding jumping point ten is connected with the input end of the sampling chip, and the other end of the welding jumping point ten is grounded. And selectively welding corresponding resistors and resistance values at the nine welding jump points, the ten welding jump points and the eleven welding jump points according to requirements, and realizing signal acquisition of different voltages and different currents.
When the collected low-speed analog signal is a voltage signal, a 0 ohm resistor is welded at eleven welding jump points, resistors with different resistance values are selected for voltage division at nine welding jump points and ten welding jump points according to the voltage, the voltage signal is reduced to be within a range of 3.3V, and the adjustable input voltage range is achieved. When the collected low-speed analog signal is a current signal, 0 ohm resistors are welded at the welding jump point nine and the welding jump point eleven, and resistors with corresponding resistance values are selected according to the current magnitude at the welding jump point ten, so that the product of the sampling current and the resistors is controlled within the range of 3.3V, and the adjustable sampling current range is realized.
The system also comprises a GPIO interface connected with the ARM or FPGA chip and used for acquiring digital signals of the meteorological hydrological sensor; the GPIO interface comprises a digital input/output driving chip, a welding trip point seven and a welding trip point eight; the digital input/output driving chip is provided with an external interface, an internal interface and a power supply pin; the internal interface is connected with an ARM or FPGA chip, and the CMOS level is always kept; the acquisition of a digital signal CMOS level or a TTL level of the meteorological hydrological sensor is realized through an external interface; one path of the power supply pin is connected with +5V voltage through a welding jumping point seven, and the other path of the power supply pin is connected with +3.3V voltage through a welding jumping point eight; when the collected signal is at TTL level, a welding jump point seven is used for welding a 0 ohm resistor, and a welding jump point eight is disconnected; when the collected signal is at the CMOS level, the welding trip point seven is disconnected, and the welding trip point eight is welded with a 0 ohm resistor.
The model number of the digital input and output driving chip is 74HC 04.
The FPGA chip and the ARM chip are both provided with universal serial bus interfaces.
The FPGA chip and the ARM chip are both provided with Ethernet ports.
The invention has the following beneficial effects:
1. the application selects the processor architecture combining the FPGA chip and the ARM chip, and has the advantages of the FPGA chip and the ARM chip.
2. The high-speed radar signal sampling interface, the low-speed analog signal sampling interface, the GPIO interface and the universal serial bus interface are arranged, almost all sensor interfaces can be included, and universality is achieved. Various interfaces are designed into one or more interfaces, so that data access of various sensors can be completed by one collector, complex monitoring system sensors are integrated and simplified, rich application scenes and working modes are considered, the realization difficulty of the system is greatly reduced under the conditions of ship navigation, volunteer ship detection and the like, the cost is reduced, and the efficiency is improved.
Drawings
Fig. 1 shows the utility model relates to a general radar data collection station's of enhancement mode frame schematic diagram.
Fig. 2 shows a circuit diagram of a high-speed radar signal sampling interface.
Fig. 3 shows a circuit diagram of the GPIO interface.
Fig. 4 shows a circuit diagram of a low speed analog signal sampling interface.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific preferred embodiments.
In the description of the present invention, it is to be understood that the terms "left side", "right side", "upper part", "lower part", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and that "first", "second", etc., do not represent an important degree of the component parts, and thus are not to be construed as limiting the present invention. The specific dimensions used in the present embodiment are only for illustrating the technical solution, and do not limit the protection scope of the present invention.
As shown in fig. 1, an enhanced general radar data collector includes an FPGA chip, an ARM chip, a high-speed radar signal sampling interface, a low-speed analog signal sampling interface, a GPIO interface, and a universal serial bus interface.
The FPGA chip is used for processing high-speed parallel radar signals, and the model is XC6SLX45 preferably.
The ARM chip is used for processing acquired sensor signals and fusing radar signals processed by the FPGA, and preferably selects a TM4C1294NCPDT (TM 4C1294 NCPDT) and ARM integrated linux operating system to enable integrated sensor system information to be visualized.
The FPGA chip and the ARM chip realize data interaction through the double-port RAM. The dual-port RAM function is mainly realized through the configuration of an IP core of the FPGA chip, and the dual-port RAM function is connected with the ARM chip through 12-bit address buses (AF ADDRB 0-11) and 16-bit data buses (AF DOUB 0-15). ARM and FPGA connection CONTROL pins (AF CONTROL 0-15, 16-bit coding) can be used for ARM input data in true dual-port RAM, and can also be used for ARM and FPGA communication or CONTROL in pseudo dual-port RAM.
The high-speed radar signal sampling interface is arranged on an FPGA chip, namely '80M analog video x 1' in figure 1, and can sample intermediate-frequency radar signals and video signals within the range of 80M and above sampling rate. The intermediate frequency signal is a differential signal, and the video signal is a single-ended signal; the video signal is divided into positive and negative signals, and positive signals and negative signals can be sampled.
As shown in fig. 2, the high-speed radar signal sampling interface includes a single-ended interface, an input conditioning circuit, and an 80M high-speed AD. The output end of the 80M high-speed AD is connected with the FPGA chip, and the input end of the 80M high-speed AD is connected with the differential interface.
The output end of the input conditioning circuit is connected with the differential interface through a welding jumping point five and a welding jumping point six. And one path of an input positive end of the input conditioning circuit is connected with the single-end interface through a welding jumping point I, and the other path of the input positive end of the input conditioning circuit is grounded through a welding jumping point III. One path of the input negative end of the input conditioning circuit is connected with the single-end interface through a welding jumping point two, and the other path of the input conditioning circuit is grounded through a welding jumping point four.
And selectively welding corresponding resistors and resistance values at a first welding jump point, a second welding jump point, a third welding jump point, a fourth welding jump point, a fifth welding jump point and a sixth welding jump point according to requirements, thereby realizing the acquisition of the intermediate frequency signals and the video signals.
As shown in fig. 2, the resistances for welding at weld jump one, weld jump two, weld jump three, weld jump four, weld jump five, and weld jump six are numbered R1, R2, R3, R4, R5, and R6, respectively.
When the acquired high-speed radar signal is an intermediate-frequency signal, the welding jump point five and the welding jump point six are disconnected, namely R5 and R6 do not weld. At this point, the input conditioning circuit is isolated and differential signals are input to the AIN _ P and AIN _ N terminals through the differential interface.
When the collected high-speed radar signal is a positive video signal, 0 ohm resistors are welded at the first welding jump point, the fourth welding jump point, the fifth welding jump point and the sixth welding jump point, the second welding jump point is disconnected, and 50 ohm-ground resistors are welded at the third welding jump point. That is, R2 is not welded, R1= R4= R5= R6=0 Ω, and R3=50 Ω.
When the acquired high-speed radar signal is a negative video signal, the first welding jump point is disconnected, 0 ohm resistors are welded at the second welding jump point, the third welding jump point, the fifth welding jump point and the sixth welding jump point, and 50 ohm-to-ground resistors are welded at the four welding jump points. That is, R1 is not welded, R2= R3= R5= R6=0 Ω, and R4=50 Ω.
The low-speed analog signal sampling interface is used for a 120KHz low-speed ADC and can collect adjustable voltage signals and current signals. The low-speed analog signal sampling interface is preferably arranged on the FPGA chip, and can also be arranged on the FPGA chip and the ARM chip simultaneously.
As shown in fig. 4, the low-speed analog signal sampling interface includes a sampling chip, a capacitor C1, a bonding pad nine, a bonding pad ten, a bonding pad eleven, and a sampling signal terminal. The sampling signal terminal is connected with the input end of the sampling chip through a welding jumping point nine, and the output end of the sampling chip is grounded through a welding jumping point eleven. And two ends of the capacitor are respectively connected with the input end and the output end of the sampling chip. One end of the welding jumping point ten is connected with the input end of the sampling chip, and the other end of the welding jumping point ten is grounded.
And selectively welding corresponding resistors and resistance values at the nine welding jump points, the ten welding jump points and the eleven welding jump points according to requirements, and realizing signal acquisition of different voltages and different currents.
As shown in fig. 4, the resistors welded at weld jump nine, weld jump ten, and weld jump eleven are respectively numbered R9, R10, and R11.
When the collected low-speed analog signal is a voltage signal, a 0 ohm resistor R11 is welded at the eleven welding jump point, resistors with different resistance values are selected according to the voltage for voltage division (namely the resistance values of R9 and R10 are changed) at the nine welding jump point and the ten welding jump point, the voltage signal is reduced to be within the range of 3.3V, and the adjustable input voltage range is realized.
When the collected low-speed analog signal is a current signal, 0 ohm resistance is welded at the welding jump point nine and the welding jump point eleven, namely R9= R11=0 Ω. And at the welding jump point ten, selecting a resistor R10 with a corresponding resistance value according to the current magnitude, and controlling the product of the sampling current and the resistor within a range of 3.3V to realize adjustable sampling current range.
And the GPIO interface, namely a general digital signal input/output interface, is used for acquiring digital signals of sensors for meteorological hydrology and the like.
As shown in fig. 3, the GPIO interface includes a digital input/output driver chip, a solder bump seven, and a solder bump eight.
The digital input/output driver chip is preferably 74HC04 in model number, and has an external interface, an internal interface and power supply pins.
The internal interface realizes the connection with an ARM or FPGA chip and always keeps the CMOS level.
The acquisition of a digital signal CMOS level or a TTL level of the meteorological hydrological sensor is realized through an external interface; one path of the power supply pin is connected with +5V voltage through a welding jumping point seven, and the other path of the power supply pin is connected with +3.3V voltage through a welding jumping point eight.
As shown in FIG. 3, the resistances at weld jump seven and weld jump eight are numbered R7 and R8, respectively.
When the collected signal is TTL level, the welding jump point seven is welded with a 0 ohm resistor R7, and the welding jump point eight is disconnected, namely R8
No welding is performed. When the collected signal is at the CMOS level, the welding jump point seven is disconnected from the R7 and is not welded, and the welding jump point eight is welded with a 0 ohm resistor R8.
Further, the universal serial bus interface is converted into a universal IO differential interface through an SN65HVD251 by using a CAN bus interface. Adopt ADM3485EAR to realize RS422, RSA85 are compatible.
Furthermore, both the FPGA chip and the ARM chip are provided with Ethernet ports, so that high-speed network communication can be realized.
As shown in fig. 1, the ARM chip further has an ARM peripheral circuit such as an SD card, DDR and NAND memory. The enhanced general radar data acquisition unit further comprises auxiliary circuits such as power management, a switch, an LED, a buzzer, JTAG (joint test action group), reserved pins and the like.
The above detailed description describes the preferred embodiments of the present invention, but the present invention is not limited to the details of the above embodiments, and the technical idea of the present invention can be within the scope of the present invention to perform various equivalent transformations, which all belong to the protection scope of the present invention.
Claims (8)
1. An enhanced universal radar data collector is characterized in that: the system comprises an FPGA chip, an ARM chip and a high-speed radar signal sampling interface;
data interaction is realized between the FPGA chip and the ARM chip through a double-port RAM; the system comprises an FPGA chip, an ARM chip and a sensor chip, wherein the FPGA chip is used for processing high-speed parallel radar signals, and the ARM chip is used for processing collected sensor signals and fusing the radar signals processed by the FPGA;
the high-speed radar signal sampling interface is arranged on the FPGA chip and comprises a single-ended interface, an input conditioning circuit and an 80M high-speed AD; the output end of the 80M high-speed AD is connected with the FPGA chip, and the input end of the 80M high-speed AD is connected with the differential interface;
the output end of the input conditioning circuit is connected with the differential interface through a welding jumping point V and a welding jumping point VI; one path of an input positive end of the input conditioning circuit is connected with the single-end interface through a welding jumping point I, and the other path of the input positive end of the input conditioning circuit is grounded through a welding jumping point III; one path of the input negative end of the input conditioning circuit is connected with the single-end interface through a welding jumping point II, and the other path of the input conditioning circuit is grounded through a welding jumping point IV;
and selectively welding corresponding resistors and resistance values at a first welding jump point, a second welding jump point, a third welding jump point, a fourth welding jump point, a fifth welding jump point and a sixth welding jump point according to requirements, thereby realizing the acquisition of the intermediate frequency signals and the video signals.
2. The enhanced universal radar data collector of claim 1, wherein: when the acquired high-speed radar signal is an intermediate-frequency signal, disconnecting the welding trip point five and the welding trip point six; when the acquired high-speed radar signal is a positive video signal, welding 0 ohm resistors are welded at a welding skip point I, a welding skip point IV, a welding skip point V and a welding skip point VI, a welding skip point II is disconnected, and a welding 50 ohm-to-ground resistor is welded at a welding skip point III; when the acquired high-speed radar signal is a negative video signal, the first welding jump point is disconnected, 0 ohm resistors are welded at the second welding jump point, the third welding jump point, the fifth welding jump point and the sixth welding jump point, and 50 ohm-to-ground resistors are welded at the four welding jump points.
3. The enhanced universal radar data collector of claim 1, wherein: the low-speed analog signal sampling interface is connected with the FPGA chip and is used for acquiring adjustable voltage signals and current signals; the low-speed analog signal sampling interface comprises a sampling chip, a capacitor, a welding trip point nine, a welding trip point ten, a welding trip point eleven and a sampling signal terminal; the sampling signal terminal is connected with the input end of the sampling chip through a welding jumping point nine, and the output end of the sampling chip is grounded through a welding jumping point eleven; two ends of the capacitor are respectively connected with the input end and the output end of the sampling chip; one end of the welding jumping point ten is connected with the input end of the sampling chip, and the other end of the welding jumping point ten is grounded; and selectively welding corresponding resistors and resistance values at the nine welding jump points, the ten welding jump points and the eleven welding jump points according to requirements, and realizing signal acquisition of different voltages and different currents.
4. The enhanced universal radar data collector of claim 3, wherein: when the collected low-speed analog signal is a voltage signal, welding 0 ohm resistors at eleven welding jump points, selecting resistors with different resistance values according to the voltage for voltage division at nine welding jump points and ten welding jump points, and reducing the voltage signal to be within a range of 3.3V to realize the adjustability of the input voltage range; when the collected low-speed analog signal is a current signal, 0 ohm resistors are welded at the welding jump point nine and the welding jump point eleven, and resistors with corresponding resistance values are selected according to the current magnitude at the welding jump point ten, so that the product of the sampling current and the resistors is controlled within the range of 3.3V, and the adjustable sampling current range is realized.
5. The enhanced universal radar data collector of claim 1, wherein: the system also comprises a GPIO interface connected with the ARM or FPGA chip and used for acquiring digital signals of the meteorological hydrological sensor; the GPIO interface comprises a digital input/output driving chip, a welding trip point seven and a welding trip point eight; the digital input/output driving chip is provided with an external interface, an internal interface and a power supply pin; the internal interface is connected with an ARM or FPGA chip, and the CMOS level is always kept; the acquisition of a digital signal CMOS level or a TTL level of the meteorological hydrological sensor is realized through an external interface; one path of the power supply pin is connected with +5V voltage through a welding jumping point seven, and the other path of the power supply pin is connected with +3.3V voltage through a welding jumping point eight; when the collected signal is at TTL level, a welding jump point seven is used for welding a 0 ohm resistor, and a welding jump point eight is disconnected; when the collected signal is at the CMOS level, the welding trip point seven is disconnected, and the welding trip point eight is welded with a 0 ohm resistor.
6. The enhanced universal radar data collector of claim 5, wherein: the model number of the digital input and output driving chip is 74HC 04.
7. The enhanced universal radar data collector of claim 1, wherein: the FPGA chip and the ARM chip are both provided with universal serial bus interfaces.
8. The enhanced universal radar data collector of claim 1, wherein: the FPGA chip and the ARM chip are both provided with Ethernet ports.
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| CN202020225779.8U CN211718733U (en) | 2020-02-28 | 2020-02-28 | Enhanced general radar data acquisition unit |
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Address after: 211153 No.32 Changqing street, Jiangning Development Zone, Nanjing City, Jiangsu Province Patentee after: China Shipbuilding Pengli (Nanjing) Atmospheric and Ocean Information System Co.,Ltd. Patentee after: CSSC Pengli (Nanjing) Technology Group Co.,Ltd. Address before: 211153 No.32 Changqing street, Jiangning Development Zone, Nanjing City, Jiangsu Province Patentee before: CSIC PRIDE (NANJING) ATMOSPHERE MARINE INFORMATION SYSTEM Co.,Ltd. Patentee before: CSIC NANJING PRIDE TECHNOLOGY GROUP CO.,LTD. |
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