CN211702000U - MCU drives high-power circuit - Google Patents

Abstract

The utility model relates to the technical field of single chip microcomputers, and discloses an MCU (microprogrammed control unit) driving high-power circuit, which comprises an MCU and a special function register PWMOS (power supply voltage MOS), wherein the special function register PWMOS is positioned inside the MCU, and the special function register PWMOS is used for driving the MCU to drive the high-power circuit; the utility model provides a solve the problem that MCU chip design cost increases that MCU drive high power circuit exists at present.

Description

MCU drives high-power circuit

Technical Field

The utility model relates to a singlechip technical field, concretely relates to MCU drives high-power circuit.

Background

The Pulse Width Modulation (PWM) waveform driving capability of the MCU is limited (about 50mA at most), and the MCU cannot drive a large current MOS transistor, and is limited in application. In order to increase the driving capability, the conventional solution needs to add a transistor, thereby increasing the design cost of the MCU.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defects of the prior art, the utility model aims to provide a MCU drive high-power circuit, solve the problem of the increase MCU design cost that present solution exists.

In order to achieve the above purpose, the utility model adopts the technical scheme that: the special function register PWMOS is positioned in the MCU, and the special function register PWMOS is used for enabling the MCU to drive the high-power circuit.

Further, the special function register PWMOS has two bits.

Further, the configuration of the special function register PWMOS includes:

synthesizing four PWM0 outputs of the MCU into one PWM0 output so that the MCU drives a 200mA NMOS tube;

synthesizing four PWM0 outputs of the MCU into two PWM0 outputs so that the MCU drives a 100mA NMOS tube;

and combining the three PWM0 outputs and the one PWM3 output of the MCU into one PWM0 output and one PWM3 output, so that the MCU drives a 150mA NMOS tube.

Furthermore, the special function register PWMOS includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, a connection point between a gate of the first PMOS transistor and a gate of the first NMOS transistor is connected to a clock terminal of the MCU, a substrate of the first PMOS transistor is connected to a source of the first PMOS transistor and then connected to VDD, a connection point between a drain of the first PMOS transistor and a drain of the first NMOS transistor is connected to a connection point between a gate of the second PMOS transistor and a gate of the second NMOS transistor, a substrate of the first NMOS transistor is connected to a source of the first NMOS transistor and then connected to VSS, a substrate of the second PMOS transistor is connected to a source of the second PMOS transistor and then connected to VDD, a connection point between a drain of the second PMOS transistor and a drain of the second NMOS transistor is opened, and a substrate of the second NMOS transistor is connected to a source of the second NMOS transistor and then connected to VSS.

Furthermore, the special function register PWMOS further includes a third PMOS transistor and a third NMOS transistor, the substrate of the third PMOS transistor is connected to VDD after being connected to the source electrode of the third PMOS transistor, the connection point between the gate electrode of the third PMOS transistor and the gate electrode of the third NMOS transistor is connected to the reset terminal of the MCU, the connection point between the drain electrode of the third PMOS transistor and the drain electrode of the third NMOS transistor is open, and the substrate of the third NMOS transistor is connected to VSS after being connected to the source electrode of the third NMOS transistor.

Further, the special function register PWMOS further includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, and an eighteenth PMOS transistor, and a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor; the connection point of the grid electrode of the fourth PMOS tube and the grid electrode of the fifth NMOS tube is connected with the data input end of the MCU, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the substrate of the fifth PMOS tube is connected with the substrate of the fourth PMOS tube and then is connected with VDD, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the substrate of the fourth NMOS tube is connected with the substrate of the fifth NMOS tube and then is connected with VSS, the connection point of the drain electrode of the fifth PMOS tube and the drain electrode of the fourth NMOS tube is respectively connected with the connection point of the drain electrode of the fifteenth PMOS tube and the drain electrode of the fourteenth NMOS tube and the connection point of the grid electrode of the seventh PMOS tube and the grid electrode of the sixth NMOS tube, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh NMOS tube, the substrate of the seventh PMOS tube is connected with the substrate of the sixth PMOS tube and then is connected, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the drain electrode of the sixth NMOS transistor is connected with the drain electrode of the seventh PMOS transistor, the connection point of the drain electrode of the seventh PMOS transistor and the drain electrode of the seventh NMOS transistor is also connected with the connection point of the gate electrode of the fourteenth PMOS transistor and the gate electrode of the fifteenth NMOS transistor and the connection point of the gate electrode of the eighth PMOS transistor and the gate electrode of the ninth NMOS transistor, respectively, the connection point of the substrate of the sixth NMOS transistor and the source electrode of the sixth NMOS transistor is connected with the connection point of the substrate of the seventh NMOS transistor and the source electrode of the seventh NMOS transistor and then connected with VSS, the connection point of the substrate of the fifteenth PMOS transistor and the substrate of the fourteenth PMOS transistor is connected with the source electrode of the fourteenth PMOS transistor and then connected with VDD, the connection point of the substrate of the fourteenth NMOS transistor and the substrate of the fifteenth NMOS transistor is connected with the source electrode of the fifteenth NMOS transistor and then connected with VSS, a substrate of the ninth PMOS transistor is connected with a source electrode of the eighth PMOS transistor and then connected with VDD, connection points where a drain electrode of the ninth PMOS transistor is connected with a drain electrode of the eighth NMOS transistor are respectively connected with a connection point of a drain electrode of the seventeenth PMOS transistor and a drain electrode of the sixteenth NMOS transistor and a connection point of a gate electrode of the eleventh PMOS transistor and a gate electrode of the tenth NMOS transistor, a gate electrode of the tenth PMOS transistor is connected with a gate electrode of the eleventh NMOS transistor, a connection point where a substrate of the eleventh PMOS transistor is connected with a substrate of the tenth PMOS transistor is connected with VDD, a connection point where a drain electrode of the eleventh PMOS transistor and a drain electrode of the eleventh NMOS transistor are connected with a drain electrode of the tenth NMOS transistor, a connection point where a substrate of the tenth NMOS transistor and a source electrode of the tenth NMOS transistor are connected with VSS, the connection point of the drain electrode of the eleventh PMOS tube and the drain electrode of the eleventh NMOS tube is also respectively connected with the connection point of the grid electrode of the sixteenth PMOS tube and the grid electrode of the seventeenth NMOS tube, the connection point of the grid electrode of the twelfth PMOS tube and the grid electrode of the twelfth NMOS tube and the connection point of the grid electrode of the eighteenth PMOS tube and the grid electrode of the eighteenth NMOS tube, the connection point of the substrate of the seventeenth PMOS tube and the substrate of the sixteenth PMOS tube is connected with the source electrode of the seventeenth PMOS tube and then connected with VDD, the connection point of the substrate of the sixteenth NMOS tube and the substrate of the seventeenth NMOS tube is connected with the source electrode of the seventeenth NMOS tube and then connected with VSS, the substrate of the twelfth PMOS tube is connected with the source electrode of the twelfth PMOS tube and then connected with VDD, and the connection point of the drain electrode of the twelfth PMOS tube and the connection point of the drain electrode of the thirteenth PMOS tube is connected with the connection point of the grid electrode of the thirteenth PMOS tube and the grid, the substrate of the twelfth NMOS tube is connected with the source electrode of the twelfth NMOS tube and then connected with VSS, the substrate of the thirteenth PMOS tube is connected with the source electrode of the thirteenth PMOS tube and then connected with VDD, the connection point of the drain electrode of the thirteenth PMOS tube and the drain electrode of the thirteenth NMOS tube is connected with the data output end of the MCU, the substrate of the thirteenth NMOS tube is connected with the source electrode of the thirteenth NMOS tube and then connected with VSS, the substrate of the eighteenth PMOS tube is connected with the source electrode of the eighteenth PMOS tube and then connected with VDD, the connection point of the drain electrode of the eighteenth PMOS tube and the drain electrode of the eighteenth NMOS tube is connected with the data inverting output end of the MCU, and the substrate of the eighteenth NMOS tube is connected with the source electrode of the eighteenth NMOS tube and then connected with VSS.

Further, the first PMOS tube and the second PMOS tube are depletion type, and the first NMOS tube and the second NMOS tube are depletion type.

Further, the third PMOS transistor is depletion type, and the third NMOS transistor is depletion type.

Further, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, and the eighteenth PMOS transistor are depletion type.

Further, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor are depletion type.

Compared with the prior art, the beneficial effects of the utility model reside in that, the utility model provides a pair of MCU drive high power circuit, through the development and open corresponding special function register PWMOS and dispose MCU's PWM 0's combination output mode, special function register PWMOS adopts the circuit system structure of PMOS pipe + NMOS pipe to the problem of the increase MCU design cost that current solution exists has been solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic diagram of MCU pin output of an MCU driving high power circuit provided by an embodiment of the present invention.

Fig. 2 is a circuit diagram of output synthesis of the MCU-driven high-power circuit according to an embodiment of the present invention.

Fig. 3 is a diagram of two output circuits for output synthesis of the MCU-driven high-power circuit provided by the embodiment of the present invention.

Fig. 4 is a diagram of another output combining two output circuits of the MCU-driven high-power circuit provided by the embodiment of the present invention.

Fig. 5 is a schematic diagram of a special function register PWMOS circuit for driving a high-power circuit by an MCU according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The same or similar reference numerals in the drawings of the present embodiment correspond to the same or similar components; in the description of the present invention, it should be understood that if there are the terms "upper", "lower", "left", "right", etc. indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of the description, but it is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore the terms describing the positional relationship in the drawings are only for illustrative purposes and are not to be construed as limitations of the present patent, and those skilled in the art can understand the specific meanings of the terms according to specific situations.

The technical solution of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 2 to 5, the present invention provides a preferred embodiment.

The MCU driving high-power circuit provided by the embodiment comprises the MCU and the special function register PWMOS, wherein the special function register PWMOS is positioned in the MCU, and the special function register PWMOS is used for enabling the MCU to drive the high-power circuit.

According to the MCU driving high-power circuit provided by the technical scheme, the combined output mode of the PWM0 of the MCU is configured by developing and opening the corresponding special function register PWMOS, and the special function register PWMOS adopts a circuit system structure of a PMOS tube and an NMOS tube, so that the problem of increasing the design cost of the MCU in the existing solution is solved.

The pin output of the MCU is shown in FIG. 1, pin 8 outputs PWM0, pin 7 outputs PWM0 or PWM1, pin 6 outputs PWM0 or PWM2, and pin 5 outputs PWM0 or PWM 3; PWM0, PWM1, PWM2, and PWM3 may each output 50mA of current.

As an embodiment of the present invention, the special function register PWMOS is two: PWMOS [1:0] configures the combined output of PWM0, the configuration description is as follows:

the first embodiment is as follows: the MCU drives a 200 mANNMOS tube; referring to fig. 2, a pin 8 output PWM0, a pin 7 output PWM0, a pin 6 output PWM0, and a pin 5 output PWM0 of the MCU are configured as 2' b01, and PWMOS [1:0] combines PWM0 output from pin 8, PWM0 output from pin 7, PWM0 output from pin 6, and PWM0 output from pin 5 of the MCU into a PWM0, so that the output current of the PWM0 reaches 200mA, thereby driving a 200mA NMOS transistor.

Example two: the MCU drives a 150 mANNMOS tube; with reference to fig. 3, the configuration PWMOS is 2' b11, and PWMOS [1:0] combines PWM0 output from pin 8, PWM0 output from pin 7, PWM0 output from pin 6, and PWM3 output from pin 5 of the MCU into one PWM0 and one PWM3, so that the output current of the PWM0 reaches 150mA, and the 150mA NMOS transistor is driven.

Example three: the MCU drives a 100 mANNMOS tube; referring to fig. 4, a pin 8 output PWM0, a pin 7 output PWM0, a pin 6 output PWM0, and a pin 5 output PWM0 of the MCU are configured as 2' b10, and PWMOS [1:0] combines PWM0 output from pin 8, PWM0 output from pin 7, PWM0 output from pin 6, and PWM0 output from pin 5 of the MCU into two PWM0 paths, and each output current of each PWM0 has a bit of 100mA, thereby realizing driving a 100 NMOS mA transistor respectively.

As an embodiment of the present invention, referring to fig. 5, the special function register PWMOS includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1 and a second NMOS transistor NM2, a connection point of a gate of the first PMOS transistor PM1 and a gate of the first NMOS transistor NM1 is connected to a clock terminal CLK of the MCU, a substrate of the first PMOS transistor PM1 is connected to a source of the first PMOS transistor PM1 and then connected to VDD, a connection point of a drain of the first PMOS transistor PM1 and a drain of the first NMOS transistor NM1 is connected to a connection point of a gate of the second PMOS transistor PM2 and a gate of the second NMOS transistor NM2, a substrate of the first NMOS transistor NM1 is connected to a source of the first NMOS transistor NM1 and then connected to VSS, a substrate of the second PMOS transistor PM2 is connected to a source of the second PMOS transistor PM2 and then connected to a connection point of a drain of the second PMOS transistor PM2 and a drain of the second NMOS transistor NM2, and a connection point of the drain of the second NMOS transistor NM2 is connected to a source of the second NMOS transistor NM2 and connected to the second NMOS transistor NM 2.

Specifically, the special function register PWMOS further includes a third PMOS transistor PM3 and a third NMOS transistor NM3, the substrate of the third PMOS transistor PM3 is connected to the source of the third PMOS transistor PM3 and then connected to VDD, the connection point of the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 is connected to the reset terminal of the MCU, the connection point of the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 is open, and the substrate of the third NMOS transistor NM3 is connected to the source of the third NMOS transistor NM3 and then connected to VSS.

Specifically, the special function register PWMOS further includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, a thirteenth PMOS transistor PM13, a fourteenth PMOS transistor PM13, a fifteenth PMOS transistor PM13, a sixteenth PMOS transistor PM13, a seventeenth PMOS transistor PM13, and an eighteenth PMOS transistor PM13, a fourth NMOS transistor NM13, a fifth NMOS transistor NM13, a sixth NMOS transistor NM13, a seventh NMOS transistor NM13, an eighth NMOS transistor NM13, a ninth NMOS transistor NM13, a tenth NMOS transistor NM13, an eleventh NMOS transistor 13, a twelfth NMOS transistor PM13, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor PM13, a fifteenth NMOS 13, a seventeenth NMOS 13, and an eighteenth NMOS 13; a connection point of a gate of the fourth PMOS transistor PM4 and a gate of the fifth NMOS transistor NM5 is connected to the data input terminal D of the MCU, a drain of the fourth PMOS transistor PM4 is connected to a source of the fifth PMOS transistor PM5, a substrate of the fifth PMOS transistor PM5 and a substrate of the fourth PMOS transistor PM4 are connected to VDD, a source of the fourth NMOS transistor NM4 and a drain of the fifth NMOS transistor NM5, a substrate of the fourth NMOS transistor NM4 and a substrate of the fifth NMOS transistor NM8 are connected to VSS, a connection point of a drain of the fifth PMOS transistor PM5 and a drain of the fourth NMOS transistor NM4 is connected to a connection point of a drain of the fifteenth PMOS transistor PM15 and a drain of the fourteenth NMOS transistor NM14, and a connection point of a gate of the seventh PMOS transistor PM7 and a gate of the sixth NMOS transistor NM6, a gate of the sixth PMOS transistor PM6 and a gate of the seventh PMOS transistor PM7 are connected to a drain of the seventh PMOS transistor PM7, a drain of the seventh PMOS transistor PM7 and a drain of the sixth PMOS transistor PM 585735 and a drain of the sixth PMOS transistor PM6, the drain of the sixth NMOS transistor NM6 and the drain of the seventh PMOS transistor PM7 are connected to the drain of the seventh NMOS transistor NM7, the connection point of the drain of the seventh PMOS transistor PM7 and the drain of the seventh NMOS transistor NM7 is also connected to the connection point of the gate of the fourteenth PMOS transistor PM14 and the gate of the fifteenth NMOS transistor NM15 and the connection point of the gate of the eighth PMOS transistor PM8 and the gate of the ninth NMOS transistor NM9, respectively, the connection point of the substrate of the sixth NMOS transistor NM6 and the source of the sixth NMOS transistor NM6 is connected to the connection point of the substrate of the seventh NMOS transistor NM7 and the source of the seventh NMOS transistor NM7 and then to VSS, the connection point of the substrate of the fifteenth PMOS transistor PM15 and the substrate of the fourteenth PMOS transistor PM14 is connected to the source of the fourteenth PMOS transistor PM14 and then to the source of the fourteenth PMOS transistor PM14, the connection point of the substrate of the fourteenth NMOS transistor NM14 and the substrate of the fifteenth transistor NM15 is connected to the source of the fifteenth PMOS transistor PM 4642 and the source of the ninth NMOS 8 and VDD is connected to the ninth NMOS transistor PM 4642 and then to the source of the ninth transistor VDD, the connection point of the drain of the ninth PMOS transistor PM9 and the drain of the eighth NMOS transistor NM8 is connected to the connection point of the drain of the seventeenth PMOS transistor PM17 and the drain of the sixteenth NMOS transistor NM16, and the connection point of the gate of the eleventh PMOS transistor PM11 and the gate of the tenth NMOS transistor NM10, the gate of the tenth PMOS transistor PM10 is connected to the gate of the eleventh NMOS transistor NM11, the connection point of the substrate of the eleventh PMOS transistor PM11 and the substrate of the tenth PMOS transistor PM10 is connected to the source of the tenth PMOS transistor PM10 and then to VDD, the connection point of the drain of the eleventh PMOS transistor PM11 and the drain of the eleventh NMOS transistor NM11 is connected to the drain of the tenth NMOS transistor NM10, the connection point of the substrate of the tenth NMOS transistor NM10 and the source of the tenth NMOS transistor NM10 is connected to the connection point of the substrate of the eleventh NMOS 11 and the drain of the eleventh NMOS transistor NM 4642 and the drain of the eleventh NMOS 11 are connected to the connection point of the drain of the seventeenth PMOS transistor PM16 and the drain of the seventeenth NMOS transistor PM11, and then to the connection point of the drain of the seventeenth NMOS transistor PM, A connection point of a gate of a twelfth PMOS tube PM12 and a gate of a twelfth NMOS and a connection point of a gate of an eighteenth PMOS tube PM18 and a gate of an eighteenth NMOS tube NM18, a connection point of a substrate of a seventeenth PMOS tube PM17 and a substrate of a sixteenth PMOS tube PM16 and a source of a seventeenth PMOS tube PM17 are connected and then VDD, a connection point of a substrate of a sixteenth NMOS tube NM16 and a substrate of a seventeenth NMOS tube NM17 and a source of a seventeenth NMOS tube NM17 are connected and then VSS, a connection point of a substrate of a twelfth PMOS tube PM12 and a source of a twelfth NMOS tube NM12 and then VDD, a connection point of a drain of a twelfth PMOS tube PM12 and a drain of a twelfth NMOS tube NM8 and a connection point NM 356 and a gate of a thirteenth PMOS tube NM3 are connected, a drain of a substrate of the twelfth PMOS tube PM12 and a source of the twelfth NMOS tube PM12 and then VSS, a drain of the thirteenth PMOS tube PM13 and a drain of the thirteenth PMOS tube PM 4642 are connected and a drain of the MCU 13 and the thirteenth PMOS tube PM13 are connected and a drain of the thirteenth NMOS tube PM, the substrate of the thirteenth NMOS transistor NM13 is connected with the source electrode of the thirteenth NMOS transistor NM13 and then connected with VSS, the substrate of the eighteenth PMOS transistor PM18 is connected with the source electrode of the eighteenth PMOS transistor PM18 and then connected with VDD, the connection point of the drain electrode of the eighteenth PMOS transistor PM18 and the drain electrode of the eighteenth NMOS transistor NM18 is connected with the data inverting output end QB of the MCU, and the substrate of the eighteenth NMOS transistor NM18 is connected with the source electrode of the eighteenth NMOS transistor NM18 and then connected with VSS.

Preferably, the first PMOS transistor PM1 and the second PMOS transistor PM2 are depletion type, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are depletion type.

Preferably, the third PMOS transistor PM3 is depletion type, and the third NMOS transistor NM3 is depletion type.

Preferably, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, the sixteenth PMOS transistor PM16, the seventeenth PMOS transistor PM17, and the eighteenth PMOS transistor PM18 are depletion type.

Preferably, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, the tenth NMOS transistor NM10, the eleventh NMOS transistor NM11, the twelfth NMOS transistor NM12, the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, the fifteenth NMOS transistor NM15, the sixteenth NMOS transistor NM16, the seventeenth NMOS transistor NM17, and the eighteenth NMOS transistor NM18 are depletion type.

The embodiments of the present invention have been described in detail, but the invention is not limited to the embodiments, and those skilled in the art can make many equivalent modifications or substitutions without departing from the spirit of the present invention, and the equivalent modifications or substitutions are included in the scope of protection defined by the claims of the present application.

Claims (9)

1. The MCU-driven high-power circuit is characterized by comprising an MCU and a special function register PWMOS, wherein the special function register PWMOS is positioned in the MCU, and the special function register PWMOS is used for enabling the MCU to drive the high-power circuit.

2. An MCU-driven high-power circuit according to claim 1, characterized in that the special function register PWMOS is two-bit;

the configuration of the special function register PWMOS includes:

synthesizing four PWM0 outputs of the MCU into one PWM0 output so that the MCU drives a 200mA NMOS tube;

synthesizing four PWM0 outputs of the MCU into two PWM0 outputs so that the MCU drives a 100mA NMOS tube;

and combining the three PWM0 outputs and the one PWM3 output of the MCU into one PWM0 output and one PWM3 output, so that the MCU drives a 150mA NMOS tube.

3. An MCU driven high power circuit according to claim 1 or 2, the special function register PWMOS comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, the connection point of the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube is connected with the clock end of the MCU, the substrate of the first PMOS tube is connected with the source electrode of the first PMOS tube and then is connected with VDD, the connection point of the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is connected with the connection point of the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube, the substrate of the first NMOS tube is connected with the source electrode of the first NMOS tube and then connected with VSS, the substrate of the second PMOS tube is connected with the source electrode of the second PMOS tube and then is connected with VDD, the connection point of the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube is open-circuit, and the substrate of the second NMOS tube is connected with the source electrode of the second NMOS tube and then connected with VSS.

4. The MCU-driven high-power circuit according to claim 3, wherein the special function register PWMOS further comprises a third PMOS transistor and a third NMOS transistor, a substrate of the third PMOS transistor is connected with a source electrode of the third PMOS transistor and then connected with VDD, a connection point of a gate electrode of the third PMOS transistor and a gate electrode of the third NMOS transistor is connected with a reset end of the MCU, a connection point of a drain electrode of the third PMOS transistor and a drain electrode of the third NMOS transistor is opened, and a substrate of the third NMOS transistor is connected with a source electrode of the third NMOS transistor and then connected with VSS.

5. The MCU-driven high-power circuit according to claim 4, wherein the special function register PWMOS further comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, and an eighteenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor; the connection point of the grid electrode of the fourth PMOS tube and the grid electrode of the fifth NMOS tube is connected with the data input end of the MCU, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the substrate of the fifth PMOS tube is connected with the substrate of the fourth PMOS tube and then is connected with VDD, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the substrate of the fourth NMOS tube is connected with the substrate of the fifth NMOS tube and then is connected with VSS, the connection point of the drain electrode of the fifth PMOS tube and the drain electrode of the fourth NMOS tube is respectively connected with the connection point of the drain electrode of the fifteenth PMOS tube and the drain electrode of the fourteenth NMOS tube and the connection point of the grid electrode of the seventh PMOS tube and the grid electrode of the sixth NMOS tube, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh NMOS tube, the substrate of the seventh PMOS tube is connected with the substrate of the sixth PMOS tube and then is connected, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the drain electrode of the sixth NMOS transistor is connected with the drain electrode of the seventh PMOS transistor, the connection point of the drain electrode of the seventh PMOS transistor and the drain electrode of the seventh NMOS transistor is also connected with the connection point of the gate electrode of the fourteenth PMOS transistor and the gate electrode of the fifteenth NMOS transistor and the connection point of the gate electrode of the eighth PMOS transistor and the gate electrode of the ninth NMOS transistor respectively, the connection point of the substrate of the sixth NMOS transistor and the source electrode of the sixth NMOS transistor is connected with the connection point of the substrate of the seventh NMOS transistor and the source electrode of the seventh NMOS transistor and then connected with VSS, the connection point of the substrate of the fifteenth PMOS transistor and the substrate of the fourteenth PMOS transistor is connected with the source electrode of the fourteenth PMOS transistor and then connected with VDD, the connection point of the substrate of the fourteenth NMOS transistor and the substrate of the fifteenth NMOS transistor is connected with the source electrode of the fifteenth NMOS transistor and then connected with VSS, a substrate of the ninth PMOS transistor is connected with a source electrode of the eighth PMOS transistor and then connected with VDD, connection points where a drain electrode of the ninth PMOS transistor is connected with a drain electrode of the eighth NMOS transistor are respectively connected with a connection point of a drain electrode of the seventeenth PMOS transistor and a drain electrode of the sixteenth NMOS transistor and a connection point of a gate electrode of the eleventh PMOS transistor and a gate electrode of the tenth NMOS transistor, a gate electrode of the tenth PMOS transistor is connected with a gate electrode of the eleventh NMOS transistor, a connection point where a substrate of the eleventh PMOS transistor is connected with a substrate of the tenth PMOS transistor is connected with VDD, a connection point where a drain electrode of the eleventh PMOS transistor and a drain electrode of the eleventh NMOS transistor are connected with a drain electrode of the tenth NMOS transistor, a connection point where a substrate of the tenth NMOS transistor and a source electrode of the tenth NMOS transistor are connected with VSS, the connection point of the drain electrode of the eleventh PMOS tube and the drain electrode of the eleventh NMOS tube is also respectively connected with the connection point of the grid electrode of the sixteenth PMOS tube and the grid electrode of the seventeenth NMOS tube, the connection point of the grid electrode of the twelfth PMOS tube and the grid electrode of the twelfth NMOS tube and the connection point of the grid electrode of the eighteenth PMOS tube and the grid electrode of the eighteenth NMOS tube, the connection point of the substrate of the seventeenth PMOS tube and the substrate of the sixteenth PMOS tube is connected with the source electrode of the seventeenth PMOS tube and then connected with VDD, the connection point of the substrate of the sixteenth NMOS tube and the substrate of the seventeenth NMOS tube is connected with the source electrode of the seventeenth NMOS tube and then connected with VSS, the substrate of the twelfth PMOS tube is connected with the source electrode of the twelfth PMOS tube and then connected with VDD, and the connection point of the drain electrode of the twelfth PMOS tube and the connection point of the drain electrode of the thirteenth PMOS tube is connected with the connection point of the grid electrode of the thirteenth PMOS tube and the grid, the substrate of the twelfth NMOS tube is connected with the source electrode of the twelfth NMOS tube and then connected with VSS, the substrate of the thirteenth PMOS tube is connected with the source electrode of the thirteenth PMOS tube and then connected with VDD, the connection point of the drain electrode of the thirteenth PMOS tube and the drain electrode of the thirteenth NMOS tube is connected with the data output end of the MCU, the substrate of the thirteenth NMOS tube is connected with the source electrode of the thirteenth NMOS tube and then connected with VSS, the substrate of the eighteenth PMOS tube is connected with the source electrode of the eighteenth PMOS tube and then connected with VDD, the connection point of the drain electrode of the eighteenth PMOS tube and the drain electrode of the eighteenth NMOS tube is connected with the data inverting output end of the MCU, and the substrate of the eighteenth NMOS tube is connected with the source electrode of the eighteenth NMOS tube and then connected with VSS.

6. The MCU-driven high-power circuit according to claim 3, wherein the first PMOS transistor and the second PMOS transistor are depletion type transistors, and the first NMOS transistor and the second NMOS transistor are depletion type transistors.

7. The MCU-driven high-power circuit according to claim 4, wherein the third PMOS transistor is depletion-mode, and the third NMOS transistor is depletion-mode.

8. The MCU-driven high-power circuit according to claim 5, wherein the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, and the eighteenth PMOS transistor are depletion type.

9. The MCU-driven high-power circuit according to claim 5, wherein the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor are depletion type.

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