CN211700261U - Wafer level RDL metal line structure - Google Patents
Wafer level RDL metal line structure Download PDFInfo
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- CN211700261U CN211700261U CN202020847866.7U CN202020847866U CN211700261U CN 211700261 U CN211700261 U CN 211700261U CN 202020847866 U CN202020847866 U CN 202020847866U CN 211700261 U CN211700261 U CN 211700261U
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Abstract
The utility model discloses a wafer level RDL metal line structure, this structure includes: the first metal layer, the second metal layer and the third metal layer are arranged on different horizontal planes, and the third metal layer comprises a first transmission layer and a second transmission layer which are arranged side by side; the first transmission layer is connected with the second metal layer through the first conductive column; the second transmission layer is connected with the first metal layer through the second conductive column; the second metal layer and the first metal layer form a capacitor structure. Through implementing the utility model discloses, set up three-dimensional electric capacity structure, can utilize the far end of decoupling capacitance suppression static line to crosstalk. The mutual inductance between the adjacent transmission lines is larger than the mutual capacitance at the same time; by compensating the coupling capacitance between the transmission lines to match the mutual inductance, the far-end crosstalk between the transmission lines can be reduced. Meanwhile, the RDL metal line structure can reduce crosstalk among transmission lines under the condition of not changing the density of the transmission lines.
Description
Technical Field
The utility model relates to a wafer packaging technology field, concretely relates to wafer level RDL metal wire structure.
Background
Crosstalk is one of four types of signal integrity issues. It means that unwanted signals are passed from one net to an adjacent net. There is crosstalk between any pair of nets. How to reduce crosstalk in high-frequency wiring is an important index of package design. Crosstalk on two adjacent transmission lines can be represented by fig. 1, and when a fast rising/falling signal drives a dynamic signal line (active line), voltage noise is measured across a static line (Quiet line) adjacent to the dynamic signal line. The noise voltage forms measured at two ends of the static line are obviously different, in order to distinguish the two ends, one End near the source End can be called as a near End, one End far away from the source End can be called as a far End, and the far End voltage is the crosstalk coefficient FEXT (far End crosstalk) of the far End.
The spacing between each line should be made as large as possible, as design constraints allow, to reduce cross talk between transmission lines and to reduce electromagnetic field coupling. However, in wafer level packaging, i.e. under the limited shape and packaging size, the density of the transmission lines is greatly increased, the line width and line distance indexes are further reduced, and how to reduce the crosstalk between the transmission lines is called as a problem to be solved.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a wafer level RDL metal line structure to solve the technical problem of crosstalk between transmission lines caused by wafer level packaging in the prior art.
The utility model provides a technical scheme as follows:
the embodiment of the utility model provides a first aspect provides a wafer level RDL metal line structure, include: the first metal layer, the second metal layer and the third metal layer are arranged on different horizontal planes, and the third metal layer comprises a first transmission layer and a second transmission layer which are arranged side by side; the first transmission layer and the second metal layer are connected through a first conductive column; the second transmission layer is connected with the first metal layer through a second conductive column; the second metal layer and the first metal layer form a capacitor structure.
Further, the first transmission layer includes a static line, and the second transmission layer includes an active line.
Further, the first conductive pillar and/or the second conductive pillar are TSV structures.
Further, the first transfer layer and the second transfer layer are disposed on the same horizontal plane.
Further, the first metal layer, the second metal layer or the third metal layer is formed by adopting an electroplating process.
Further, an insulating medium is filled between the second metal layer and the first metal layer.
The embodiment of the utility model provides a second aspect provides a wafer level RDL metal wire preparation method, including following step: etching the substrate on which the first insulating layer is deposited to form a first groove; filling a metal material in the first groove to form a first metal layer; forming a second insulating layer on the first metal layer and the first insulating layer, and etching the second insulating layer to form a second groove and a third groove; filling a metal material in the second groove and the third groove to form a second metal layer and a part of second conductive column, wherein the part of second conductive column is in contact with the first metal layer, an insulating layer is arranged between the second metal layer and the first metal layer, and the second metal layer and the first metal layer form a capacitor structure; forming a third insulating layer on the second metal layer and a part of the first conductive column, and etching the third insulating layer to form a fourth groove and a fifth groove; and filling a metal material on the fourth groove, the fifth groove and the third insulating layer to form a first conductive column, a residual part of a second conductive column and a third metal layer, wherein the first conductive column is in contact with the second metal layer, and the third metal layer comprises a first transmission layer and a second transmission layer which are arranged side by side.
Further, after filling a metal material in the first groove to form a first metal layer, the method further includes: removing redundant metal materials on the first insulating layer by adopting a grinding process; and/or after filling a metal material in the second groove and the third groove to form a second metal layer and a part of the second conductive pillar, the method further includes: and removing the redundant metal material on the second insulating layer by adopting a grinding process.
Furthermore, the first metal layer, the second metal layer and the third metal layer are formed by adopting an electroplating process.
Further, before etching the second insulating layer to form a second groove and a third groove, the method further includes: and thinning the second insulating layer.
The utility model discloses technical scheme has following advantage:
the embodiment of the utility model provides a wafer level RDL metal wire structure and preparation method thereof through set up three-dimensional electric capacity structure in RDL wiring layer, can utilize the far end of decoupling capacitance suppression static line to crosstalk. The mutual inductance between the adjacent transmission lines is larger than the mutual capacitance at the same time; by compensating the coupling capacitance between the transmission lines to match the mutual inductance, the far-end crosstalk between the transmission lines can be reduced. The embodiment of the utility model provides a wafer level RDL metal line structure and preparation method thereof forms three-dimensional electric capacity structure through first metal level, second metal level and the third metal level that sets up to be located different horizontal planes in RDL wiring layer, and consequently, this RDL metal line structure need not change original interconnection and walks the wiring overall arrangement to can reduce the crosstalk between the transmission line under the condition that does not change transmission line density, simplified the design.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of signal crosstalk in the prior art;
fig. 2 is a schematic structural diagram of a wafer level RDL metal line structure according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a wafer level RDL metal line according to an embodiment of the present invention;
fig. 4 to 9 are schematic diagrams of a wafer level RDL metal line structure obtained by the method for manufacturing a wafer level RDL metal line according to the embodiment of the present invention;
fig. 10 is a flow chart of a method for fabricating a wafer level RDL metal line according to another embodiment of the present invention.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.
The embodiment of the utility model provides a wafer level RDL metal line structure, as shown in FIG. 2, this RDL metal line structure includes: the first metal layer 10, the second metal layer 20 and the third metal layer are arranged on different levels, and the third metal layer comprises a first transmission layer 31 and a second transmission layer 32 which are arranged side by side; the first transmission layer 31 and the second metal layer 20 are connected by the first conductive pillar 41; the second transmission layer 32 and the first metal layer 10 are connected by a second conductive pillar 42; the second metal layer 20 and the first metal layer 10 constitute a capacitor structure.
The embodiment of the utility model provides a wafer level RDL metal wire structure through set up three-dimensional electric capacity structure in RDL wiring layer, can utilize the far end of decoupling capacitance suppression static line to crosstalk. The mutual inductance between the adjacent transmission lines is larger than the mutual capacitance at the same time; by compensating the coupling capacitance between the transmission lines to match the mutual inductance, the far-end crosstalk between the transmission lines can be reduced. The embodiment of the utility model provides a wafer level RDL metal line structure forms three-dimensional electric capacity structure through first metal level, second metal level and the third metal level that sets up to be located different horizontal planes in RDL wiring layer, consequently, this RDL metal line structure need not change original interconnection and walks the wiring overall arrangement to can reduce the crosstalk between the transmission line under the condition that does not change transmission line density, simplified the design.
In an embodiment, the first transmission layer in the third metal layer may be a static line, the second transmission layer may be an active line, the two transmission layers are arranged in parallel, and a distance between the two transmission layers may be set according to a specific package structure. In an actual manufacturing process, in order to simplify the manufacturing process, the first transfer layer and the second transfer layer may be disposed on the same horizontal plane.
In an embodiment, the first conductive pillars and/or the second conductive pillars may be formed by a TSV process. To simplify the process, the first metal layer, the second metal layer, or the third metal layer may be formed simultaneously with the first conductive pillars and/or the second conductive pillars. Specifically, during the preparation, a PVD (Physical Vapor Deposition) plating process may be selected to form the first conductive pillar, the second conductive pillar, the first metal layer, the second metal layer, or the third metal layer.
In one embodiment, as shown in fig. 2, the first metal layer and the second metal layer may be formed by etching the insulating layer and depositing a metal material, and thus, an insulating medium 50 may be between the first metal layer and the second metal layer as the upper and lower electrodes of the capacitor structure.
The embodiment of the utility model provides a still provide a wafer level RDL metal wire preparation method, as shown in FIG. 3, this RDL metal wire preparation method includes the following step:
step S101: etching is carried out on the substrate 101 deposited with the first insulating layer 102 to form a first groove 103; specifically, an insulating layer may be first deposited on the substrate 101, and then the first insulating layer 102 is etched by using an etching process to form the first groove 103. Optionally, the first insulating layer 102 may be made of silicon dioxide, or may be made of other materials, which is not limited by the present invention. The structure after step S101 is shown in fig. 4.
Step S102: filling a metal material in the first groove 103 to form a first metal layer 10; specifically, a PVD plating process may be used to deposit a metal material in the first groove 103 to form the first metal layer 10, and a CMP (Chemical Mechanical Polishing) grinding process may be used to remove the metal material formed on the first insulating layer 102 during the process. The structure after step S102 is shown in fig. 5.
Step S103: forming a second insulating layer 104 on the first metal layer 10 and the first insulating layer 102, and etching the second insulating layer 104 to form a second groove 105 and a third groove 106; specifically, the second insulating layer 104 may be formed on the first metal layer 10 and the first insulating layer 102; meanwhile, in order to facilitate the subsequent etching process, the formed second insulating layer 104 may be thinned by a CMP process. The second insulating layer 104 may be etched to form a second groove 105 and a third groove 106, where a portion of the first metal layer may be exposed for the etched third groove, so that a portion of the first conductive pillar formed subsequently may contact the first metal layer, and thus electrical connection may be achieved. The structure after step S103 is shown in fig. 6.
Step S104: and filling a metal material in the second groove 105 and the third groove 106 to form a second metal layer 20 and a part of the second conductive pillar 107, wherein the part of the second conductive pillar 107 is in contact with the first metal layer 10, an insulating layer is arranged between the second metal layer 20 and the first metal layer 10, and the second metal layer 20 and the first metal layer 10 form a capacitor structure. Specifically, the second metal layer 20 and a portion of the second conductive pillar 107 may be formed using a PVD plating process. After the second metal layer 20 and a portion of the second conductive pillars 107 are formed, a CMP (chemical mechanical Polishing) grinding process may be used to remove the metal material formed on the second insulating layer 104 in the process. The structure after step S104 is shown in fig. 7.
Step S105: forming a third insulating layer 108 on the second metal layer 20 and a part of the second conductive pillar 107, and etching the third insulating layer 108 to form a fourth groove 109 and a fifth groove 110; the fifth groove 110 and the third groove 106 may have the same size, so that the remaining portion of the second conductive pillar 111 formed in the fifth groove 110 subsequently and the portion of the second conductive pillar 107 may constitute the second conductive pillar 42. For the fourth recess 109, a portion of the second metal layer may be exposed by etching. The structure after step S105 is shown in fig. 8.
Step S106: depositing a metal material on the fourth groove 109, the fifth groove 110 and the third insulating layer 108 to form a first conductive pillar 41, a remaining portion of a second conductive pillar 111 and a third metal layer, where the first conductive pillar 41 contacts the second metal layer 20, the third metal layer includes a first transmission layer 31 and a second transmission layer 32 that are arranged side by side, the first transmission layer 31 is electrically connected to the second metal layer 20 through the first conductive pillar 41, and the second transmission layer 32 is connected to the first metal layer 10 through the second conductive pillar 42. Wherein, two transmission layers parallel arrangement side by side, the interval between two transmission layers can set up according to specific packaging structure. The structure after step S106 is shown in fig. 9.
The embodiment of the utility model provides a wafer level RDL metal wire preparation method through set up three-dimensional capacitor structure in RDL wiring layer, can utilize the far end of decoupling capacitance suppression static line to crosstalk. The mutual inductance between the adjacent transmission lines is larger than the mutual capacitance at the same time; by compensating the coupling capacitance between the transmission lines to match the mutual inductance, the far-end crosstalk between the transmission lines can be reduced. The embodiment of the utility model provides a wafer level RDL metal wire preparation method forms three-dimensional electric capacity structure through first metal level, second metal level and the third metal level that sets up to be located different horizontal planes in the RDL wiring layer, consequently, this RDL metal wire preparation method need not change original interconnection and walks the wiring overall arrangement to can reduce the crosstalk between the transmission line under the condition that does not change transmission line density, simplified the design.
In one embodiment, as shown in fig. 10, the method for manufacturing the wafer level RDL metal line may include the following steps:
step S201: an insulating layer is formed on a substrate.
Step S202: and etching the insulating layer to form a groove.
Step S203: and forming a first metal layer in the groove by adopting a PVD (physical vapor deposition) electroplating process.
Step S204: and depositing an insulating layer on the first metal layer and thinning.
Step S205: and etching the thinned insulating layer to form a groove.
Step S206: and forming part of the second conductive posts in the grooves by adopting a PVD (physical vapor deposition) electroplating process.
Step S207: and depositing an insulating layer on part of the second conductive posts and thinning.
Step S208: and etching the thinned insulating layer to form two grooves.
Step S209: and forming partial second conductive columns and partial second metal layers in the two grooves by adopting a PVD (physical vapor deposition) electroplating process.
Step S210: and forming an insulating layer on part of the second conductive pillar and the second metal layer.
Step S211: and etching the insulating layer to form two grooves.
Step S212: and forming a first conductive column, the rest part of the second conductive column and a third metal layer on the two grooves and the insulating layer by adopting a PVD (physical vapor deposition) electroplating process.
Although the present invention has been described in detail with respect to the exemplary embodiments and the advantages thereof, those skilled in the art will appreciate that various changes, substitutions and alterations can be made to the embodiments without departing from the spirit of the invention and the scope of the invention as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while maintaining the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (6)
1. A wafer level RDL metal line structure, comprising: a first metal layer, a second metal layer and a third metal layer arranged on different horizontal planes,
the third metal layer comprises a first transmission layer and a second transmission layer which are arranged side by side;
the first transmission layer and the second metal layer are connected through a first conductive column;
the second transmission layer is connected with the first metal layer through a second conductive column;
the second metal layer and the first metal layer form a capacitor structure.
2. The wafer level RDL metal line structure of claim 1, wherein the first transmission layer comprises a static line and the second transmission layer comprises an active line.
3. The wafer level RDL metal line structure of claim 1, wherein the first and/or second conductive pillars are TSV structures.
4. The wafer level RDL metal line structure of claim 1, wherein the first transmission layer and the second transmission layer are disposed on a same horizontal plane.
5. The wafer level RDL metal line structure of claim 1, wherein the first, second, or third metal layer is formed using an electroplating process.
6. The wafer level RDL metal line structure of claim 1, wherein an insulating medium is filled between the second metal layer and the first metal layer.
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| CN111446222A (en) * | 2020-05-19 | 2020-07-24 | 上海先方半导体有限公司 | Wafer-level RD L metal line structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111446222A (en) * | 2020-05-19 | 2020-07-24 | 上海先方半导体有限公司 | Wafer-level RD L metal line structure and preparation method thereof |
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