CN211698937U

CN211698937U - Feedback device

Info

Publication number: CN211698937U
Application number: CN202020390718.7U
Authority: CN
Inventors: 何健标; 马晓明
Original assignee: Shenzhen Polytechnic
Current assignee: Shenzhen Polytechnic
Priority date: 2020-03-24
Filing date: 2020-03-24
Publication date: 2020-10-16
Anticipated expiration: 2030-03-24

Abstract

The utility model discloses a feedback device, which comprises a basic 4 cascade operation module; the base 4 cascade operation module comprises: the utility model discloses a rotation factor produces unit, complex multiplier, delay exchange unit, butterfly arithmetic element and output exchange unit, the butterfly arithmetic element is connected respectively to delay exchange unit, complex multiplier and output exchange unit, output exchange unit connects butterfly arithmetic element and delay exchange unit, the utility model discloses on the basis of make full use of complex multiplier, through using two delay feedback structure circuit and ingenious design data delay buffer memory passageway for the availability factor of complex adder/subtracter obtains effectively improving, and required complex adder/subtracter quantity obviously reduces, and circuit efficiency obtains showing and promotes; the problem that base 4SDF and base 4SDC structures occupy more complex adders/subtractors is effectively solved.

Description

Feedback device

Technical Field

The utility model relates to an electronic communication technical field especially relates to a feedback device.

Background

Fast discrete fourier transform (FFT)/Inverse Fast Fourier Transform (IFFT) is a fast implementation of Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) and is a commonly used technique in digital signal processing.

Because the operation processes defined by DFT and IDFT are very similar, the FFT and IFFT can adopt the same circuit structure and implementation method.

Cooley and Tukey invent an FFT algorithm, and the basic idea of FFT is to decompose an original N-point sequence into two or more shorter sequences and recombine the sequences into a DFT of the original sequence, so that the operation times of an indirect algorithm are much less than those of a direct calculation DFT, and the calculation speed of the DFT is improved.

The FFT/IFFT decomposition operation can be divided into several types, generally called radix-S algorithm, according to the number S of decomposed short sequences.

For example, the radix-2 FFT algorithm may decompose an N-point DFT operation into

2 point DFT operation process; the radix-4 FFT algorithm may decompose an N-point DFT operation into

4 points DFT operation process; the radix-8 FFT algorithm may decompose an N-point DFT operation into

8-point DFT operation process.

Theoretically, the larger the base S of the decomposition operation is, the higher the efficiency of the decomposition algorithm is, but actually, the larger S is, the more the number of complex multipliers of the DFT operation module is, and therefore, the number of complex multipliers actually required by the DFT operation module of 8 points or more is not small, and the DFT operation module of 8 points or more is rarely used in engineering, and the present FFT/IFFT processor basically uses the decomposition algorithm of base 2 or base 4.

Current hardware implementation architectures for FFT processors include recursive architectures, pipelined architectures, and fully parallel architectures.

The recursion structure is also called as a shared memory structure, occupies the least hardware resources, has only one operation processing unit, but needs longer operation time, cannot continuously process FFT calculation requests and is only suitable for occasions needing FFT calculation occasionally; the pipeline structure adopts a multi-stage operation unit, the previous stage operation unit can calculate the next FFT without waiting for the completion of FFT operation after sending the result into the next stage operation unit, and the pipeline structure can continuously calculate the non-overlapping N-point FFT of the data before and after the data is processed; for the continuous FFT calculation of the overlapped front and back data, only a full parallel structure can be adopted, each stage of operation of the structure is provided with a corresponding operation unit aiming at the point number N, each stage of operation time delay can be as low as a single system clock period, the continuous calculation of any N-point FFT can be realized, and the occupied hardware resource is huge.

In practical application, the occasion of continuous calculation of arbitrary N-point FFT is very few, so that the pipeline design of FFT processor is the most common.

The pipeline structure of the FFT processor mainly comprises 3 types: a Single-path Delay adapter (SDC), a Multi-path Delay adapter (MDC), and a Single-path Delay Feedback adapter (SDF).

Correspondingly, the FFT processor pipeline structure adopting the radix-2 algorithm comprises three structures of R2SDC, R2SDF, R2MDC and the like; the FFT processor pipeline structure adopting the radix-4 algorithm comprises three structures of R4SDC, R4SDF, R4MDC and the like.

Since the radix-2 SDC (R2SDC) structure has no advantage over the R2SDF in radix-2 butterfly decomposition operations, the radix-2 FFT processor mainly employs radix-2 MDC (R2MDC) and radix-2 SDF (R2SDF) structures. The base 2MDC and base 2SDF structures have the characteristics of simple control and easy realization, and occupied circuit resources are not different, wherein the base 2SDF structure needs a little less memory, and the calculation time delay of the base 2MDC structure is shorter.

However, the common disadvantage of the radix-2 MDC and radix-2 SDF architectures is that the utilization of complex multipliers is low (only 50%), and thus the number of complex multipliers required for the entire FFT processor is large.

Because the FFT/IFFT operation is composed of complex multiplication and complex addition/subtraction, the multiplication is far more complex than the addition/subtraction, so the circuit scale of the FFT processor is mainly determined by the complex multiplier, and the main drawback of the base 2MDC and base 2SDF structures is that the complex multiplier has a low utilization rate, which results in large circuit resource occupation.

The radix-4 MDC (R4MDC) structure is the simplest of three pipeline implementation structures of the radix-4 decomposition algorithm, but the disadvantage is also very obvious, that is, the 4-way delay adapter structure needs an independent complex multiplier, a butterfly arithmetic unit bf (butterfly) and a storage unit, and the utilization rate of these hardware circuit units is low (only 25%), so that the FFT processor adopting the R4MDC structure needs more hardware circuit units than the radix-2 MDC and radix-2 SDF structures, and is a low-efficiency single-channel FFT processor implementation structure.

The radix-4 SDF (R4SDF) architecture is a relatively efficient FFT processor implementation, since serial data streams can fully use complex multipliers, which makes the complex multiplier utilization (75%) efficient, and the complex multipliers required by the whole FFT processor are half of those of R2MDC and R2SDF architectures; the memory space required by the R4SDF structure is comparable to that of the R2SDF, one third less than that of the R2MDC structure; the biggest drawback of R4SDF is that the number of complex adders required is large, 2 times the number of complex adders required for R2 SDF.

Compared with the deficiency of the R4SDF structure, the R4SDC structure can effectively reduce (62.5%) the number of complex adders, and the number of complex multipliers required is also consistent with that of the R4SDF structure, but the memory capacity required by the R4SDC structure is increased (100%) compared with that of the R4SDF structure, and the control logic circuit of the R4SDC structure is very complex and is relatively difficult to implement.

Accordingly, the prior art is yet to be improved and developed.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in, to the above-mentioned defect of prior art, provide a feedback device, aim at solving basic 4SDF and basic 4SDC structure among the current FFT IFFT treater and occupy the problem of more plural number adder/subtracter.

The utility model provides a technical scheme that technical problem adopted as follows:

a feedback apparatus, wherein the apparatus comprises a base 4 cascade operation module; the base 4 cascade operation module comprises: a twiddle factor generating unit, a complex multiplier, a delay switching unit, a butterfly operation unit and an output switching unit; the complex multiplier is respectively connected with the twiddle factor generation unit and the delay switching unit, the delay switching unit is respectively connected with the butterfly operation unit, the complex multiplier and the output switching unit, and the output switching unit is connected with the butterfly operation unit and the delay switching unit;

the twiddle factor generating unit is used for generating twiddle factors required by the base 4 cascade operation module;

the complex multiplier is used for calculating the product of serial input data and the corresponding twiddle factor and transmitting the calculated output data to the delay exchange unit;

the delay switching unit is used for delaying the output data obtained by the calculation of the complex multiplier and the feedback data output by the output switching unit for a preset time, adjusting the sequence of the output data and then respectively transmitting the output data to the butterfly operation unit and the output switching unit;

the butterfly operation unit is used for performing butterfly operation on the output data of the delay switching unit and transmitting an operation result to the output switching unit;

and the output switching unit selects data from the operation result of the butterfly operation unit and the data transmitted by the delay switching unit to output and feed back to the delay switching unit.

Further, the feedback apparatus, wherein the delay switching unit includes a first data selector, a second data selector, a third data selector, a first data delay, a second data delay, and a third data delay;

the first data selector is respectively connected with the complex multiplier, the output switching unit, the first data delayer and the second data delayer;

the second data selector is respectively connected with the complex multiplier, the third data delayer and the butterfly operation unit;

the third data selector is respectively connected with the second data delayer, the output switching unit and the third data delayer;

the first data delayer is respectively connected with the first data selector and the butterfly operation unit;

the second data delayer is respectively connected with the output switching unit, the first data selector and the third data selector;

the third data delayer is respectively connected with the second data selector, the third data selector and the output switching unit;

the first data selector is used for selecting data from the output data of the complex multiplier, the output switching unit or the second data delayer and transmitting the data to the first data delayer;

the second data selector is used for selecting data from the output data of the complex multiplier or the third data delayer and outputting the selected data to the butterfly arithmetic unit;

the third data selector is used for selecting data from the output data of the second data delayer or the output switching unit to be transmitted to a third data delayer;

the first data delayer is used for delaying the data selected by the first data selector by a first effective clock period and transmitting the data to the butterfly operation unit;

the second data delayer is used for delaying the output data of the output switching unit by a second effective clock period and transmitting the delayed output data to the first data selector and the third data selector;

and the third data delayer is used for delaying the data selected by the third data selector by a third effective clock period and transmitting the data to the second data selector and the output switching unit.

Further, the feedback apparatus, wherein the delay switching unit further includes a delay switching state controller;

the delayed switching state controller is used for respectively controlling the first data selector, the second data selector and the third data selector to select corresponding input data at different moments according to a preset switching control instruction.

Further, the feedback apparatus described above, wherein the butterfly operation unit includes a complex adder and a complex subtractor;

the complex adders are used for respectively carrying out time-sharing addition operation on input data and then transmitting the input data to the output exchange unit;

the complex subtracter is used for respectively carrying out time-sharing subtraction operation on input data and then transmitting the input data to the output exchange unit;

the complex adder is connected with the delay switching unit and the output switching unit;

the complex subtracter is connected with the delay switching unit and the output switching unit.

Further, the feedback apparatus described above, wherein the output switching unit includes a fourth data selector, a fifth data selector, and a constant multiplier;

the fourth data selector is respectively connected with the butterfly operation unit and the delay switching unit;

the fifth data selector is respectively connected with the butterfly operation unit, the constant multiplier and the delay switching unit;

the constant multiplier is respectively connected with the butterfly operation unit and the fifth data selector;

the fourth data selector is used for selecting data from the output data of the butterfly operation unit or the delay switching unit to be output as a calculation result;

the fifth data selector is used for selecting data from the output data of the butterfly operation unit or the constant multiplier and feeding the data back to the delay switching unit;

and the constant multiplier is used for performing rotation and complement operations on the real part and the imaginary part of the input data and transmitting the operation result to the fifth data selector.

Further, the feedback apparatus, wherein the output switching unit further includes an output switching state controller;

the output switching state controller is used for respectively controlling the fourth data selector and the fifth data selector to select corresponding input data at different moments according to a preset switching control instruction.

Has the advantages that: the utility model provides a feedback device, which comprises a base 4 cascade operation module; the base 4 cascade operation module comprises: a twiddle factor generating unit, a complex multiplier, a delay switching unit, a butterfly operation unit and an output switching unit; the complex multiplier is respectively connected with the twiddle factor generation unit and the delay switching unit, the delay switching unit is respectively connected with the butterfly operation unit, the complex multiplier and the output switching unit, and the output switching unit is connected with the butterfly operation unit and the delay switching unit; the utility model discloses on the basis of make full use of complex number multiplier, delay the buffer memory passageway through using two delay feedback structure circuit and ingenious design data for the availability factor of complex number adder/subtracter obtains effectively improving, and required complex number adder quantity obviously reduces, and circuit efficiency obtains showing and promotes; the problem that base 4SDF and base 4SDC structures occupy more complex adders/subtractors is effectively solved.

Drawings

Fig. 1 is a schematic diagram of an external interface of a base 4 cascade operation module in a feedback apparatus of the present invention;

fig. 2 is a schematic diagram of an internal structure of a base 4 cascade operation module in a feedback apparatus of the present invention;

fig. 3 is a schematic diagram of an external interface of a butterfly operation unit in a radix-4 cascade operation module in a feedback apparatus according to the present invention;

fig. 4 is a schematic diagram of an external interface of a delay switching unit in a base-4 cascade operation module in a feedback apparatus according to the present invention;

fig. 5 is a schematic diagram of an internal structure of a delay switching unit in a base-4 cascade operation module in a feedback apparatus according to the present invention;

fig. 6 is a schematic diagram of the operation of the delay switching unit in the base-4 cascade operation module in the feedback apparatus of the present invention;

fig. 7 is a schematic diagram of an external interface of an output switching unit in a base-4 cascade operation module in a feedback apparatus according to the present invention;

fig. 8 is a schematic diagram of an internal structure of an output switching unit in the base 4 cascade operation module in the feedback apparatus of the present invention;

fig. 9 is a schematic diagram of the operation of the output switching unit in the base 4 cascade operation module in the feedback apparatus of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The utility model relates to a Feedback device, in view of basic 4MDC in the common pipeline structure, the defect of basic 4SDC and basic 4SDC structure, the innovative Single Path double delay Feedback (Radix4Single Path-double delay Feedback, R4SP-DDF) structure of proposing basic 4 algorithm, on make full use of complex multiplier (utilization ratio 75%, the same with R4SDF and R4SDC structure), through using two delay Feedback structure circuit and ingenious design data delay buffer memory passageway, make BF2 (complex adder) availability factor improve (100%), effectively solved basic 4SDF and basic 4SDC structure and occupy more problem of complex adder/subtracter. The number of complex adders is reduced (75%) compared to the R4SDC structure, and is also reduced (33%) compared to the R4SDC structure.

In view of the above-mentioned several kinds of FFT/IFFT processor implementation structures (R4SDF/R4SDC/R4MDC) of the 4 base decomposition algorithm all have the lower defect of plural number adder utilization ratio, the utility model discloses further decompose the 4 base decomposition algorithm of FFT operation, the order:

the output sequence x (k) of the FFT/IFFT processor can be further decomposed into:

according to the decomposition process, the base 4 decomposition operation realized by the base 4 cascade operation module can be roughly decomposed into 4 addition operations (

E + G, F + J) and 4 subtractions: (

E-G, F-J), that is, the base 4 decomposition operation implemented by the base 4 cascade operation module can be decomposed into 4 addition operations, 4 subtraction operations, and 1 (-J) multiplication operation. Because the real part and the imaginary part in the circuit of the FFT/IFFT processor are separately calculated, the complex multiplier of pure imaginary number (-j) only needs to perform simple data exchange and complementary code processing; and 4 times of addition and 4 times of subtraction can be realized by calculating the complex adder/subtracter one by one in a time sharing way, so that the utilization efficiency of the complex adder/subtracter can be effectively improved (to 100%).

Referring to fig. 1, fig. 1 is a schematic diagram of an external interface of a base 4 cascade operation module in a feedback device according to the present invention.

The embodiment of the utility model provides an external interface of base 4 cascade operation module includes input interface and output interface, and wherein, input interface includes:

reset, Clock, In _ DataSync, In _ DataEna, In _ DataI, and In _ DataQ, where Reset and Clock are global Reset and global Clock signals, In _ DataI and In _ DataQ are serial input data, In _ DataI is the real part of the input data (I subsection) and In _ DataQ is the imaginary part of the input data (Q subsection); the In _ DataEna is a data enable signal, and the input In _ DataI and In _ DataQ are valid only when the In _ DataEna is valid; in _ DataSync is a frame synchronization signal, and is only valid when the first data of the data frame is input, and is invalid at other times;

the output interface includes:

out _ DataSync, Out _ DataValid, Out _ DataI, and Out _ DataQ, where Out _ DataI and Out _ DataQ are serial data outputs, Out _ DataI corresponding to the real part of the computed result (I subsection) and Out _ DataQ corresponding to the imaginary part of the computed result (Q subsection); out _ DataValid is a data output valid signal, and Out _ DataI and Out _ DataQ of the output result are valid only when Out _ DataValid is valid; out _ DataSync is a frame sync signal, and is valid only when the first data of frame data is output, and outputs an invalid level at other times.

Referring to fig. 2, the apparatus includes a base 4 cascade operation module; the base 4 cascade operation module comprises: a delay switching unit 10, a butterfly operation unit 20, an output switching unit 30, a twiddle factor generation unit 40, and a complex multiplier 50; the complex multiplier 50 is respectively connected with the twiddle factor generating unit 40 and the delay switching unit 10, the delay switching unit 10 is respectively connected with the butterfly operation unit 20, the complex multiplier 50 and the output switching unit 30, and the output switching unit 30 is connected with the butterfly operation unit 20 and the delay switching unit 10;

the twiddle factor generating unit 40 is configured to generate twiddle factors required by the base 4 cascade operation module;

the complex multiplier 50 is used for calculating the product of the serial input data and the corresponding twiddle factor, and transmitting the calculated input data to the delay switching unit 10.

The delay switching unit 10 is configured to delay the output data obtained by calculation by the complex multiplier 50 and the feedback data output by the output switching unit for a preset time, adjust the sequence of the output data, and transmit the output data to the butterfly operation unit 20 and the output switching unit 30, respectively;

the butterfly operation unit 20 is configured to perform a butterfly operation on the output data of the delay switching unit 10, and transmit an operation result to the output switching unit 30;

the output switch unit 30 selects data from the operation result of the butterfly operation unit 20 and the data transmitted by the delay switch unit 10, outputs the data, and feeds the data back to the delay switch unit 10.

In this embodiment, the twiddle factor generating unit 40 is mainly a read only memory (ROM memory) and stores twiddle factors required in the radix-4 cascade operation module

The complex multiplier 50 is used for calculating the product of the serial input data and the corresponding twiddle factor, and sending the calculated result to the delay switching unit 10, wherein the serial input data InData is a complex number, which includes a real part (In _ DataI) and an imaginary part (In _ DataQ), it should be understood that the twiddle factor generating unit 40 can also be obtained by hardware circuit calculation, and the invention is not limited thereto.

More specifically, the delay switching unit 10 is a three-input three-output switching circuit, three input channels respectively correspond to the serial input data channel (InData) of the basic 4-cascade operation module and two delay feedback data interfaces (FB + and FB-) of the output switching unit 30, and the delay switching unit 10 enables data of three input ports to be correctly switched to three output data ports through the delay switching state controller 17; the data from the a1 and a2 output ports of the delay switch unit 10 are sent to two input ports of the butterfly unit 20, and the data from the A3 output port of the delay switch unit 10 is sent to the output switch unit 30; the two data input ports of the butterfly unit 20 are both from the delay switch unit 10, and the results after completing the butterfly operation are sent to the B1 and B2 ports of the output switch unit 30; the output switch unit 30 is also a three-input three-output switch circuit, and reasonably distributes the data of 3 ports input by the delay switch unit 10 and the butterfly operation unit 20 to 3 output ports through the output switch state controller 34, the first output port of the output switch unit 30 corresponds to the output data channel (OutData) of the basic 4 cascade operation module, the other 2 output data ports (FB + and FB-) of the output switch unit 30 correspond to the double delay feedback path of the basic 4 cascade operation module, and the data of the two ports are fed back to the two input ports of the delay switch unit 10.

Further, referring to fig. 3, the butterfly unit 20 includes a complex adder 21 and a complex subtractor 22; the complex adder 21 is used for performing time-division addition operation on the input data respectively; the complex subtracter 50 is used for respectively carrying out time-sharing subtraction on input data; the complex adder 21 is connected with the delay switching unit 10 and the output switching unit 30; the complex subtractor 22 is connected to the delay switching unit 10 and the output switching unit 30.

In the present embodiment, the complex adder 21 and the complex subtractor 22 may operate in a time-division mode to improve the efficiency of use, and the output from the complex multiplier 50 may be input (calculated)

) Sometimes, the operation inputs feedback (E + G, F + J, E-G, F-J) from the complex adder 21 and the complex subtractor 22, the delay switching unit is responsible for the delay switching scheduling of the input data of the complex adder 21 and the complex subtractor 22, the output data of the complex multiplier 50 (i.e. serial input data multiplied by a twiddle factor) and the feedback data of the complex adder 21/the complex subtractor 22 are switched and scheduled on a data channel and a time sequence through the delay switching unit, and 2 paths of complex data streams are output and respectively sent to the complex adder 21/the complex subtractor 22, so that the complex adder 21/the complex subtractor 22 can perform high-speed and effective time-sharing calculation; because of the time-sharing working mode of the complex adder 21/the complex subtracter 22, the output result sometimes needs to be fed back to the delay switching unit for the next round of calculation (E, F, G, H), sometimes can be directly output as the output serial sequence (E + G, F + J) of the basic 4 cascade operation module of the current stage, sometimes needs to be fed back to the delay switching unit to be delayed as the output serial sequence (E-G, F-J) of the basic 4 cascade operation module of the current stage because the basic 4 cascade operation modules are connected by a single data path.

Referring to fig. 4 and 5, the delay switching unit 10 is a three-input three-output small-scale switching circuit, each data input/output port corresponds to one path of complex data input/output, i.e. each path of input/output includes a real part (I branch) and an imaginary part (Q branch) of data, the delay switching unit 10 includes a first data selector 11, a second data selector 12, a third data selector 13, a first data delay 14, a second data delay 15 and a third data delay 16;

the first data selector 11 is respectively connected to the complex multiplier 50, the output switching unit 30, the first data delay 14 and the second data delay 15;

the second data selector 12 is respectively connected to the complex multiplier 50, the third data delay 16 and the butterfly operation unit 20;

the third data selector 13 is respectively connected with the second data delayer 15, the output switching unit 30 and the third data delayer 16;

the first data delayer 14 is respectively connected with the first data selector 11 and the butterfly operation unit 20;

the second data delayer 15 is respectively connected with the output switching unit 30, the first data selector 11 and the third data selector 13;

the third data delayer 16 is respectively connected with the second data selector 12, the third data selector 13 and the output switching unit 30;

the first data selector 11 is used for selecting data from input data to be transmitted to a first data delayer 14;

the second data selector 12 is used for selecting corresponding data from the input data and outputting the corresponding data to the butterfly operator 20;

the third data selector 13 is used for selecting corresponding data from the input data and transmitting the corresponding data to the third data delayer 16;

the first data delay 14 is configured to delay the input data by a first valid clock period and transmit the delayed input data to the butterfly operation unit 20;

the second data delayer 15 is used for delaying the input data by a second valid clock period and transmitting the delayed input data to the first data selector 11 and the third data selector 13;

the third data delay 16 is used to delay the input data by a third valid clock period and transmit the delayed input data to the second data selector 12 and the output switching unit 30.

The first data delayer can delay the input data by M/2 valid clock cycles for outputting, the second and third data delayers can delay the input data by M/4 valid clock cycles for outputting, M2N × 2^-iM is the data cycle period of the base 4 cascade operation module, and N is the length of FFT operation. The first data selector is a three-input data selector, and the second data selector and the third data selector are two-input data selectors. The first data selector is responsible for selecting proper data from the 3-path input data for the A1 output port of the delay switching unit (connected with the butterfly operation unit 20 in the radix-4 cascade operation module). The 3-way input data of the first data selector comes from InData, FB + and FB-of the delay switching unit 10, and the three data input ports correspond to the output of the complex multiplier 50 in the radix-4 cascade operation module and the output of the butterfly operation unit 20 (through the output switching unit 30 and the 2-way feedback channel), respectively. The second data selector is responsible for selecting the appropriate data from the 2-way input data for the a2 output port of delay switch unit 10 (connected to butterfly unit 20 in the radix-4 cascade operation block). The 2-way input data of the second data selector comes from the InData data input port of the delay switching unit 10 (corresponding to the output of the complex multiplier 50 in the basic 4-cascade operation module) and the other comes from the output of the third data selector (through the second data delay unit is also needed). The third data selector is responsible for selecting the appropriate data from the 2-way input data for the a3 output port of delay switch unit 10 (the In _ C port of pass-through output switch unit 30 In the base 4 cascaded arithmetic block). The 2-way input data of the third data selector respectively corresponds to the FB + data input port (i.e. the complex adder 21 outputs the corresponding feedback channel) and the FB-data input port (i.e. the complex subtractor 22 outputs the corresponding feedback channel) of the delay switching unit 10.

Specifically, the following further explains the operation process of the delay switching unit 10 with reference to fig. 5 and 6, where the delay switching unit 10 is a complex finite state machine circuit, the operation states include 12 states in total, such as a waiting state, an enabling state a, an enabling state B, an enabling state C, a loop processing state a, a loop processing state B, a loop processing state C, a loop processing state D, an exiting state a, an exiting state B, an exiting state C, and an exiting state D, and the operation states of the three data selectors and the three data delayers of the delay switching unit 10 in different states are defined as follows:

wait state (M/2 data cycles): the first data selector, the second data selector and the third data selector are closed, and no data is output; both the second data delayer and the third data delayer have no data; the output ports A1/A2/A3 have no output; the complex adder 21/complex subtracter 22 in the base 4 cascade operation module does not work; and input ports FB + and FB-connected with the two feedback paths have no data input.

Startup state a (M/2 data cycles): the first data selector gates the data from the InData port (namely the output of the complex multiplier 50 in the base 4 cascade operation module), and the input data sequentially enters the first data delayer of the data delayer; the second data selector and the third data selector are closed; both the second data delayer and the third data delayer have no data; the output ports A1/A2/A3 have no output; the complex adder 21/complex subtracter 22 in the base 4 cascade operation module does not work; and input ports FB + and FB-connected with the two feedback paths have no data input.

Startup state B (M/4 data cycles): the second data selector gates the data from the InData port (i.e. the output of the complex multiplier 50 in the base 4 cascade operation module), and the input data is output to the A2 port through the second data selector and is sent to the addend/subtracter port of the complex adder 21/complex subtracter 22 in the base 4 cascade operation module; meanwhile, the first M/4 data of the input data entering the first data delayer in the starting state A are output one by one from the delayer and are sent to the addend/minuend port of the complex adder 21/complex subtracter 22 in the base 4 cascade operation module through the port A1; the complex adder 21 and the complex subtracter 22 calculate E/F one by one, and the E/F is calculated for M/4 times in total; the calculation result of the complex adder 21/the complex subtracter 22 is sent to the FB +/FB-port through two feedback channels, and the first data selector gates the data from the FB + port (i.e. the feedback channel corresponding to the output of the complex adder 21), the calculation result E of the complex adder 21 sequentially enters the first data delayer of the data delayer, and the calculation result F of the complex subtracter 22 sequentially enters the second data delayer; at this stage the third data selector is off, no data is output, the third data delay is no data, and the a3 port is no data output.

Startup state C (M/4 data cycles): the second data selector gates the data from the InData port (i.e. the output of the complex multiplier 50 in the base 4 cascade operation module), and the input data is output to the A2 port through the second data selector and is sent to the addend/subtracter port of the complex adder 21/complex subtracter 22 in the base 4 cascade operation module; meanwhile, the last M/4 data of the input data entering the first data delayer in the starting state A are also output one by one from the delayer and are sent to the addend/minuend port of the complex adder 21/complex subtracter 22 in the base 4 cascade operation module through the port A1; the complex adder 21 and the complex subtracter 22 calculate G/H one by one, and the total time is M/4; the calculation result of the complex adder 21/complex subtracter 22 is sent to the FB +/FB-port through the output switching unit 30 and two feedback channels, and at the same time, the third data selector gates the data from the FB + port (i.e. the feedback channel corresponding to the output of the complex adder 21), the calculation result G of the complex adder 21 sequentially enters the third data delayer, and the calculation result H of the complex subtracter 22 sequentially enters the second data delayer after being converted into J through the output switching unit 30; meanwhile, the first data selector gates the port connected with the second data delayer, F which enters the data delayer in the starting state B is output from the second data delayer at the moment, the data enters the first data delayer through the first data selector in sequence, and the A3 port has no data output.

Loop processing state a (M/4 data cycles): the data E entering the first data delayer from the starting state B or the circular processing state C are output to the port A1 one by one and are sent to the addend/minded port of the complex adder 21/complex subtracter 22; the second data selector gates the port connected with the second data delayer, and the starting state C or the cycle processing state D enters the G of the third data delayer, and then the G is output from the third data delayer and is sent to the addend/subtracter port of the complex adder 21/the complex subtracter 22 through the second data selector and the A2 output port; the complex adder 21/the complex subtracter 22 calculates (E + G)/(E-G) one by one, and the total is calculated for M/4 times; the result (E + G) of the complex adder 21 is sent to the next-stage base-4 cascade operation module by the output switching unit 30 as the output of the base-4 cascade operation module, and the result (E-G) of the complex subtracter 22 is sent to the FB-port of the delay switching unit through the feedback channel and enters the second data delayer in turn; the data of the input port FB + connected with the feedback channel is not gated and can be directly discarded; meanwhile, the data J entering the second data delayer in the starting state C or the circulating processing state D are sequentially output, at the moment, the third data selector gates a port connected with the data delayer (M/4), and the J sequentially enters the third data delayer; meanwhile, the input data of the next cycle is input from the InData port in sequence, the first data selector gates the data of the InData port at the moment, and the input data of the next cycle starts to enter the first data delayer; the output data from the a3 port is discarded by the output switching unit 30.

Loop processing state B (M/4 data cycles): the data F entering the first data delayer in the starting state C or the circular processing state D are output to the port A1 one by one and are sent to the addend/minded port of the complex adder 21/complex subtracter 22; the second data selector gates the port connected to the third data delay, and the J of the cyclic processing state a entering the third data delay is outputted from the third data delay and is sent to the addend/subtracter port of the complex adder 21/complex subtracter 22 through the second data selector and a2 output port; the complex adder 21/the complex subtracter 22 calculates (F + J)/(F-J) one by one, and the total is calculated for M/4 times; the result (F + J) of the complex adder 21 is sent to the next-stage base 4 cascade operation module by the output switching unit 30 as the output of the base 4 cascade operation module of this stage, and the result (F-J) of the complex subtracter 22 is sent to the FB-port of the delay switching unit through the feedback path and enters the second data delayer in turn; the data of the input port FB + connected with the feedback path are not gated and can be directly discarded; meanwhile, the data (E-G) entering the second data delayer in the cyclic processing state A are sequentially output, and at the moment, the third data selector gates the port connected with the second data delayer, and the data (E-G) sequentially enter the third data delayer; meanwhile, the input data of the next cycle is input from the InData port in sequence, the first data selector gates the data of the InData port at the moment, and the input data of the next cycle starts to enter the first data delayer; the output data from the a3 port is discarded by the output switching unit 30.

Loop processing state C (M/4 data cycles): the data (next cycle) of the loop processing state A and the loop processing state B entering the first data delayer in turn are output to the port A1 one by one and are sent to the addend/minded port of the complex adder 21/complex subtracter 22; meanwhile, the second data selector gates the data (also the data of the next cycle) from the InData port, and the input data is output to the A2 port through the second data selector and is sent to the addend/subtracter port of the complex adder 21/complex subtracter 22 in the base 4 cascade operation module; the complex adder 21 and the complex subtracter 22 calculate the E/F of the next cycle one by one, and the E/F is calculated for M/4 times in total; the calculation result of the complex adder 21/the complex subtracter 22 is sent to the FB +/FB-port through two feedback channels, meanwhile, the first data selector gates the data from the FB + port, the calculation result (of the next cycle) E of the complex adder 21 sequentially enters the first data delayer, and the calculation result (of the next cycle) F of the complex subtracter 22 sequentially enters the second data delayer; the third data selector gates a port connected with the second data delayer, and data (currently circulating) (F-J) entering the second data delayer in the circulating processing state B are sequentially output and enter the third data delayer through the third data selector; meanwhile, the data (currently circulating) (E-G) In the loop processing state B entering the third data delay is sequentially output, sent to the In _ C port of the output switching unit 30 through the a3 port, and sent to the next-stage radix-4 cascade operation module by the output switching unit 30 as the output of the current-stage radix-4 cascade operation module.

Loop processing state D (M/4 data cycles): the data (next cycle) of the first data delayer of the data delayer sequentially entering the loop processing state A and the loop processing state B are output to the port A1 one by one and are sent to the addend/minuend port of the complex adder 21/the complex subtracter 22; meanwhile, the second data selector gates the data (also the data of the next cycle) from the InData port, and the input data is output to the A2 port through the second data selector and is sent to the addend/subtracter port of the complex adder 21/complex subtracter 22 in the base 4 cascade operation module; the complex adder 21 and the complex subtracter 22 calculate the G/H of the next cycle one by one, and the total time is M/4; the calculation result of the complex adder 21/the complex subtracter 22 is sent to the FB +/FB-port through two feedback channels, and at the same time, the third data selector gates the data from the FB + port (i.e. the feedback channel corresponding to the output of the complex adder 21), the calculation result (of the next cycle) G of the complex adder 21 sequentially enters the third data delayer, and the calculation result (of the next cycle) H of the complex subtracter 22 is converted into J by the output switching unit 30 and then sequentially enters the second data delayer; meanwhile, the first data selector gates a port connected with the second data delayer, and F (of the next cycle) of the cycle processing state C entering the second data delayer is output from the second data delayer and sequentially enters the first data delayer through the first data selector; meanwhile, the data (currently circulating) (F-J) In the loop processing state C entering the third data delay is sequentially output, sent to the In _ C port of the output switching unit 30 through the a3 port, and sent to the next-stage radix-4 cascade operation module by the output switching unit 30 as the output of the current-stage radix-4 cascade operation module.

Exit State A (M/4 data cycles): the data E entering the first data delayer of the data delayer in the loop processing state C are output to the port A1 one by one and are sent to the addend/minded port of the complex adder 21/complex subtracter 22; the second data selector gates the port connected to the third data delay, and G, when the loop processing state D enters the third data delay, is output from the third data delay and is sent to the addend/subtracter port of the complex adder 21/complex subtracter 22 through the second data selector and a2 output port; the complex adder 21/the complex subtracter 22 calculates (E + G)/(E-G) one by one, and the total is calculated for M/4 times; the result (E + G) of the complex adder 21 is sent to the next-stage base-4 cascade operation module by the output switching unit 30 as the output of the base-4 cascade operation module, and the result (E-G) of the complex subtracter 22 is sent to the FB-port of the delay switching unit through the feedback channel and enters the second data delayer in turn; the data of the input port FB + connected with the feedback channel is not gated and can be directly discarded; meanwhile, the data J entering the second data delayer in the cyclic processing state D are sequentially output, at the moment, the third data selector gates the port connected with the second data delayer, and the J sequentially enters the third data delayer; meanwhile, the first data selector is closed, and no input data enters the first data delayer; the output data from the a3 port is discarded by the output switching unit 30.

Exit processing state B (M/4 data cycles): the data F entering the first data delayer in the loop processing state D are output to the port A1 one by one and are sent to the addend/minded port of the complex adder 21/complex subtracter 22; the second data selector gates the port connected with the third data delayer, and the J exiting from the state A and entering the third data delayer is output from the third data delayer and is sent to the addend/subtracter port of the complex adder 21/the complex subtracter 22 through the second data selector and an output port A2; the complex adder 21/the complex subtracter 22 calculates (F + J)/(F-J) one by one, and the total is calculated for M/4 times; the result (F + J) of the complex adder 21 is sent to the next-stage base 4 cascade operation module by the output switching unit 30 as the output of the base 4 cascade operation module of this stage, and the result (F-J) of the complex subtracter 22 is sent to the FB-port of the delay switching unit 10 through the feedback channel and enters the second data delayer in turn; the data of the input port FB + connected with the feedback channel is not gated and can be directly discarded; meanwhile, the data (E-G) entering the second data delayer from the state A are sequentially output, and at the moment, the third data selector gates the port connected with the second data delayer, and the data (E-G) sequentially enters the third data delayer; meanwhile, the first data selector is closed, and no data enters the first data delayer; the output data from the a3 port is discarded by the output switching unit 30.

Exit processing state C (M/4 data cycles): the first data delayer has no data output; the second data selector is closed; the complex adder 21/complex subtracter 22 stops working; the first data selector is closed; the third data selector gates a port connected with the second data delayer, data (F-J) entering the second data delayer from the state B are sequentially output, and enter the third data delayer through the third data selector; meanwhile, the data (E-G) entering the third data delay device In the exit state B are sequentially output, sent to the In _ C port of the output switching unit 30 through the a3 port, and sent to the next-stage base-4 cascade operation module by the output switching unit 30 as the output of the current-stage base-4 cascade operation module.

Exit processing state D (M/4 data cycles): the first data delayer has no data output; the second data selector is closed; the complex adder 21/complex subtracter 22 stops working; the third data selector is closed; the first data selector is closed; the data (F-J) entering the third data Delay (M/4) In the exit state C is sequentially output, sent to the In _ C port of the output switching unit 30 through the a3 port, and sent to the next-stage radix-4 cascade operation module as the output of the current-stage radix-4 cascade operation module by the output switching unit 30.

It should be noted that the operating state jump control of the delay switching unit 10 is performed by the delay switching state controller 17, wherein the delay switching state controller 17 controls the first data selector 11, the second data selector 12, and the third data selector 13 to select corresponding input data at different times according to a preset switching control instruction. Specifically, the transitions between 12 states are shown in FIG. 6: before no FFT calculation data (including the intermediate calculation result) is input, the delay switching unit 10 stays in a waiting state, when new frame data is received, the delay switching unit 10 jumps from the waiting state to a starting state A, then jumps to a starting state B and a starting state C in sequence, and the starting state completes the filling of all data delayers inside the delay switching unit 10; then, sequentially jumping to a cycle processing state A, a cycle processing state B, a cycle processing state C and a cycle processing state D, wherein M data of one cycle can be processed by traversing four states of cycle processing each time; when the loop processing state D is finished each time, the delay switching state controller detects whether the current frame data is not calculated or whether the next frame data is processed, and if so, the delay switching state controller jumps to the loop processing state A to continue working; otherwise, jumping to exit state A, traversing exit state B and exit state C in sequence, completing the data processing of the last cycle of the current frame, and finally jumping back to the waiting state to wait for the input of the next frame of calculation data. Since the number of data processed by 11 operating states, such as the startup state a, the startup state B, the startup state C, the loop processing state a, the loop processing state B, the loop processing state C, the loop processing state D, the exit state a, the exit state B, the exit state C, and the exit state D, is fixed, the delay swap state controller 17 can be implemented by a counter and a simple logic determination circuit.

Referring to fig. 7 and 8, the output switching unit 30 is a three-input three-output small-scale switching circuit, each data input/output port corresponds to one path of complex data input/output, i.e. each path of input/output includes a real part (I branch) and an imaginary part (Q branch) of data, the output switching unit 30 includes a fourth data selector 31, a fifth data selector 32 and a constant multiplier 33;

the fourth data selector 31 is respectively connected with the butterfly operation unit 20 and the delay switching unit 10;

the fifth data selector 32 is connected to the butterfly operation unit 20, the constant multiplier 33, and the delay switching unit 10, respectively;

the constant multiplier 33 is connected to the butterfly operation unit 20 and the fifth data selector 32;

the fourth data selector 31 is configured to select data from the output data of the butterfly operation unit 20 or the delay switching unit 10 as a calculation result to be output;

the fifth data selector 32 is configured to select data from the output data of the butterfly operation unit 20 or the constant multiplier 33 and feed the data back to the delay switching unit 10;

the constant multiplier 33 is configured to rotate and complement the real part and the imaginary part of the input data, and transmit the operation result to the fifth data selector 32.

In the present embodiment, the output switch unit 30 has 3 input ports In _ A/In _ B/In _ C and 3 output ports Out _ Data/FB +/FB-; the input port In _ A/In _ B is connected with the output end of the complex adder 21/complex subtracter 22 of the base 4 cascade operation module, and the In _ C port is connected with the output port A3 of the delay switching unit 10; the output port Out _ Data is directly used as a Data output port of the base 4 cascade operation module, and the output port FB +/FB-is interconnected with the input port FB +/FB-of the delay switching unit 10 through a 2-path feedback path.

Further, the entire switching unit is composed of a fourth data selector/fifth data selector and a constant multiplier (-j); the fourth data selector and the fifth data selector are two input data selectors, the fourth data selector selects proper data from the In _ A port or the In _ C port to be sent to the output port OutData, and the fifth data selector selects proper data from the In _ B port or the output port of the constant multiplier (-j) to be sent to the output port FB-; the constant multiplier (-J) converts the data H inputted from the In _ B terminal into J (J ═ hx (-J)). The constant multiplier (-j) does not need any hardware multiplier, and only needs to rotate and complement the real part (I branch) and the imaginary part (Q branch) of the input complex data.

Specifically, the following further explains the working process of the output switching unit 30 with reference to fig. 8 and 9, where the output switching unit 30 is a finite state machine circuit, the working state includes 4 states, such as a shutdown state, a calculation output state, a feedback output state a, and a feedback output state B, and in different states, the working states of the two data selectors and the constant multiplier of the output switching unit 30 are defined as follows:

and (3) closing state: in the current state, the fourth data selector and the fifth data selector are turned off, the OutData port outputs no data, the FB-port outputs no data, and the data delay switching unit 10 output by the FB + port automatically discards the data.

Calculating an output state: the state corresponds to the time when an adder/subtracter of the base 4 cascade operation module calculates (E + G)/(E-G) and (F + J)/(F-J) (the total time is calculated for M/2 times), a fourth data selector gates data (E + G) and (F + J) of an In _ A port, and the data (E + G) and the data (F + J) are output through an OutData port and serve as the output of the base 4 cascade operation module of the current stage to be sent to the next base 4 cascade operation module of the next stage; meanwhile, the fifth data selector gates the data (E-G) and (F-J) of the In _ B port, the data (E-G) and (F-J) are sent to the FB-input port of the delay switching unit 10 through the FB-port and the feedback path, and the data (E-G) and (F-J) are buffered and wait for output In the delay switching unit 10; at this time, the data (E + G) and (F + J) of the In _ a port are also sent to the FB + input port of the delay switching unit 10 through the FB + port and the feedback path, but the delay switching unit 10 automatically discards the data.

Feedback output state a: the state is calculated for M/4 times In total, the fourth data selector gates the In _ C port, data (E-G) of the previous cycle buffered In the delay switching unit 10 is output through the OutData port and is sent to the next-stage base 4 cascade operation module as the output of the current-stage base 4 cascade operation module; meanwhile, the fifth data selector gates the data F of the In _ B port, and sends the data F to the FB-input port of the delay switching unit 10 through the FB-port and the feedback path, and the data F is buffered In the delay switching unit 10 to wait for the next calculation; at this time, the data E of the In _ a port is also sent to the FB + input port of the delay switching unit 10 through the FB + port and the feedback path, and the data E is buffered In the delay switching unit 10 to wait for the next calculation.

Feedback output state B: the state is calculated for M/4 times In total, the fourth data selector gates the In _ C port, data (F-J) of the previous cycle buffered In the delay switching unit 10 is output through the OutData port and is sent to the next-stage base 4 cascade operation module as the output of the current-stage base 4 cascade operation module; meanwhile, the calculation result H of the subtractor of the base 4 cascade operation module is sent to the input port In _ B, the constant multiplier (-J) converts H into J output (J ═ hx (-J)), the fifth data selector gates the output data J of the constant multiplier (-J), and sends the data J to the FB-input port of the delay switching unit 10 through the FB-port and the feedback path, and the data J is buffered In the delay switching unit 10 to wait for the next calculation; at this time, the data G from the In _ a port is also sent to the FB + input port of the delay switching unit 10 through the FB + port and the feedback path, and the data G will be buffered In the delay switching unit 10 for the next calculation.

It should be noted that the output switching state controller 34 is responsible for controlling the working state jump of the output switching unit 30, wherein the output switching state controller 34 controls the fourth data selector 31 and the fifth data selector 32 to select corresponding input data at different times according to a preset switching control instruction. Specifically, the transitions between 4 states are shown in FIG. 9: when the adder/subtractor of the base 4 cascade operation module does not input data to the output switching unit 30, the output switching unit 30 stays in the closed state, when new frame data is input, the output switching unit 30 jumps from the closed state to the calculation output state, then jumps to the feedback output state a and the feedback output state B in sequence, and the calculation output state/the feedback output state a/the feedback output state B can output M data of one cycle each time the data is traversed; when the feedback output state B is close to the end each time, the output switching state controller can detect whether the current frame data is not completely output or the next frame data is processed, and if so, the output switching state controller jumps to the calculation output state to continue working; otherwise, jumping back to the off state and waiting for the input of the next frame data. Since the number of data processed by each of the 3 operating states, such as the calculation output state, the feedback output state a, the feedback output state B, etc., is fixed, the output switching state controller can be implemented by a counter and a simple logic judgment circuit.

To sum up, the utility model provides a feedback device, which comprises a base 4 cascade operation module; the base 4 cascade operation module comprises: a twiddle factor generating unit, a complex multiplier, a delay switching unit, a butterfly operation unit and an output switching unit; the complex multiplier is respectively connected with the twiddle factor generation unit and the delay switching unit, the delay switching unit is respectively connected with the butterfly operation unit, the complex multiplier and the output switching unit, and the output switching unit is connected with the butterfly operation unit and the delay switching unit; the utility model discloses on the basis of make full use of complex number multiplier, delay the buffer memory passageway through using two delay feedback structure circuit and ingenious design data for the availability factor of complex number adder/subtracter obtains effectively improving, and required complex number adder quantity obviously reduces, and circuit efficiency obtains showing and promotes; the problem that base 4SDF and base 4SDC structures occupy more complex adders/subtractors is effectively solved.

It is to be understood that the invention is not limited to the above-described embodiments, and that modifications and variations may be made by those skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims

1. A feedback apparatus, comprising a base 4 cascade operation module; the base 4 cascade operation module comprises: a twiddle factor generating unit, a complex multiplier, a delay switching unit, a butterfly operation unit and an output switching unit; the complex multiplier is respectively connected with the twiddle factor generation unit and the delay switching unit, the delay switching unit is respectively connected with the butterfly operation unit, the complex multiplier and the output switching unit, and the output switching unit is connected with the butterfly operation unit and the delay switching unit;

2. The feedback apparatus of claim 1, wherein the delay switching unit comprises a first data selector, a second data selector, a third data selector, a first data delayer, a second data delayer, and a third data delayer;

3. The feedback apparatus of claim 2, wherein the delay switching unit further comprises a delay switching state controller;

4. The feedback apparatus according to claim 1, wherein the butterfly unit comprises a complex adder and a complex subtractor;

5. The feedback apparatus according to claim 1, wherein the output switching unit includes a fourth data selector, a fifth data selector, and a constant multiplier;

6. The feedback apparatus of claim 5, wherein the output switching unit further comprises an output switching state controller;