CN211656125U - Inverter circuit capable of adjusting rising and falling time of output signal in real time - Google Patents

Abstract

The utility model provides a but phase inverter circuit of real-time regulation output signal rise fall time, the grid and the drain electrode of first PMOS pipe, the grid of second PMOS pipe all connects current input port I2, the drain electrode of second PMOS pipe connects the grid of third NMOS pipe, the grid and the drain electrode of third PMOS pipe all connect the drain electrode of second NMOS pipe, the grid of fourth PMOS pipe connects the drain electrode of second NMOS pipe, the drain electrode of fourth PMOS pipe connects the source electrode of fifth PMOS pipe, the grid and the drain electrode of first NMOS pipe, the grid of second NMOS pipe all connects current input port I1, the drain electrode of third NMOS pipe connects the drain electrode of second PMOS pipe, the grid of fourth NMOS pipe connects the drain electrode of second PMOS pipe, the fifth PMOS pipe, the grid of fifth NMOS pipe connects input port A, the source electrode of fifth NMOS pipe connects the drain electrode of fourth NMOS pipe, the fifth PMOS pipe, the drain electrode of fifth NMOS pipe connects output port Y, first PMOS pipe, the second PMOS pipe, the third PMOS pipe, the grid of fifth NMOS pipe, The source electrodes of the fourth PMOS tube are all connected with a power supply VCC, and the source electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are grounded.

Description

Inverter circuit capable of adjusting rising and falling time of output signal in real time

Technical Field

The invention relates to a phase inverter circuit capable of adjusting rising and falling time of an output signal in real time, which is applied to an analog circuit and a digital-analog interface circuit needing to dynamically adjust the rising and falling slopes of a potential in real time and belongs to the field of chip design.

Background

In chip design, no matter digital signal technology or digital-analog mixed signal technology, the inverter is widely applied to logic control circuits due to simple structure and single function. The conventional inverter has a two-transistor structure, and once the design performance is solidified, the level transition curve cannot be adjusted, so that the conventional inverter cannot be applied to an application requiring dynamic adjustment of the rise time and the fall time.

As shown in fig. 1, the circuit of the conventional inverter is composed of a PMOS transistor PM1 and an NMOS transistor NM1, wherein the gate of the PMOS transistor PM1 is connected to the input port a, the source is connected to the power port VCC, and the drain is connected to the output port Y; the gate of the NMOS transistor NM1 is connected to the input port a, the source is connected to the ground GND, and the drain is connected to the output port Y. If the input signal A is a rail-to-rail voltage, PM1 and NM1 are alternately in the saturation region.

For the PMOS transistor PM1, when it is in saturation region, the current flowing is:

wherein mu_pDenotes the mobility of the carrier holes of the PMOS tube, c_oxThe unit area of the gate oxide layer capacitance of the PMOS tube is shown,

denotes the aspect ratio, V, of PM1_GSPRepresents the difference in the gate-source voltages of PM1, which is the supply voltage, V, when PM1 is in saturation_THPRepresenting the threshold voltage of the PMOS transistor. For the NMOS transistor NM1, when it is in the saturation region, the current flowing through it is:

wherein mu_nDenotes the mobility of the carrier holes of the NMOS tube, c_oxThe gate oxide capacitance of the unit area of the NMOS tube is expressed,

represents the width-to-length ratio, V, of NM1_GSNRepresents the voltage difference between the gate and the source of NM1, which is the power supply voltage, V, when NM1 is in saturation_THNRepresenting the threshold voltage of the NMOS transistor. In the above two formulae, μ_n、c_ox、V_THNThe values of (a) are provided by the process manufacturer and the remaining parameters are designed by the designer. When I is_PM1And I_NM1When the input voltage is equal, the threshold voltage of the inverter can be calculated on the premise that the voltage is known, and when the input voltage is higher or lower than the threshold voltage, the output voltage of the inverter is inverted.

Now, assuming that the output end of the conventional inverter is a capacitor load and the capacitance value is C, the working process of the inverter is actually the process of charging and discharging the capacitor. Assuming constant charging and discharging currents of PM1 and NM1 to capacitor C, when PM1 is in saturation region and NM1 is in cutoff region, current charges capacitor through PM1, and the charging current is I_PM1The charging time is as follows:

when NM1 is in saturation region and PM1 is in cut-off region, current discharges the capacitor through NM1, the discharge current is I_NM1The discharge time is as follows:

where Vcc is the supply voltage. If the charging current I_PM1And discharge current I_NM1The rise time and fall time of the output signals are equal. For the two-transistor inverter, once the aspect ratio is fixed, the charging current and the discharging current are also fixed under the premise that the working voltage is not changed, that is, the rising time and the falling time of the output signal are also fixedThe interval is also fixed.

Disclosure of Invention

The design is provided aiming at the fixed rising time and falling time of the output signal of the traditional inverter and is suitable for the application occasions of the variable rising time and falling time of the output signal.

The utility model discloses a realize like this:

the utility model provides a phase inverter circuit capable of adjusting rising and falling time of output signals in real time, which comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first PMOS transistor PM1 and a second PMOS transistor PM2 form a first mirror image current mirror, a third PMOS transistor PM3 and a fourth PMOS transistor PM4 form a second mirror image current mirror, a third NMOS transistor NM1 and a second NMOS transistor NM2 form a third mirror image current mirror, a third NMOS transistor NM3 and a fourth NMOS transistor NM4 form a fourth mirror image current mirror, a fifth PMOS transistor PM5 and a fifth NMOS transistor NM5 form a fifth mirror image current mirror, a first PMOS transistor NM VCC 5 and a second PMOS 5 are connected with a source electrode of the PMOS 5, a PMOS electrode 5 and a PMOS electrode 5, a PMOS electrode 5 of the PMOS transistor PM5 is connected with a power supply of the PMOS transistor PM5, the drain of the second PMOS transistor PM2 is connected to the gate of the third NMOS transistor NM3, the gate of the third PMOS transistor PM3 and the drain of the third PMOS transistor PM3 are both connected to the drain of the second NMOS transistor NM2, the source of the third PMOS transistor PM3 is connected to the power VCC, the gate of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor NM2, the source of the fourth PMOS transistor PM4 is connected to the power VCC, the drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5, the gate of the fifth PMOS transistor PM5 is connected to the input port A, the drain of the fifth PMOS transistor PM5 is connected to the output port Y, the gate of the first NMOS transistor NM1 and the drain of the first NMOS transistor NM1 are connected to the current input port I1, the source of the first NMOS transistor NM1 is connected to the ground, the gate of the second NMOS transistor NM2 is connected to the current input port I1, the source of the second NMOS transistor NM 36 2, the drain of the third PMOS transistor NM3 is connected to the drain of the second NMOS transistor NM2, the drain of the fourth PMOS 363672 is connected to the drain of the fourth NMOS transistor PM 3636, the gate of the fifth NMOS transistor NM5 is connected to the input port a, the source of the fifth NMOS transistor NM5 is connected to the drain of the fourth NMOS transistor NM4, and the drain of the fifth NMOS transistor NM5 is connected to the output port Y.

The utility model discloses following beneficial effect has:

the utility model provides a but phase inverter circuit of real-time regulation output signal rise decline time is applied to analog circuit and digital analog interface circuit that needs real-time dynamic adjustment output signal rise decline slope, through the size of adjusting input current, realizes the accurate control to the level transition slope, compares in the phase inverter of the fixed level transition slope of tradition, and the invention can realize the accurate control of fixed level transition slope and variable level transition slope in a flexible way, can greatly improve the flexibility of circuit.

Drawings

FIG. 1 is a circuit diagram of a conventional two-transistor inverter;

fig. 2 is a schematic diagram of a phase inverter circuit capable of adjusting the rise and fall time of an output signal in real time according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a circuit simulation provided by an embodiment of the present invention.

Description of reference numerals: PM is PMOS tube; NM — NMOS tube; i1 — external input current; i2 — external input current; a- -external port of the circuit; y- -external port of the circuit; VCC — power supply; GND- -ground.

Detailed Description

The following detailed description of the invention will be made with reference to fig. 2.

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

As shown in fig. 2, an embodiment of the present invention provides an inverter circuit capable of adjusting rising and falling time of an output signal in real time, which is disposed on a carrier electronic device, and is applied to an analog circuit and a digital-analog interface circuit that require real-time dynamic adjustment of a rising and falling slope of a potential, the inverter circuit includes first to fifth NMOS transistors NM1 to NM5, first to fifth PMOS transistors PM1 to PM5, and input ports I1, I2, a and an output port Y, which are connected to an external input control signal, the output port Y is connected to control input ports I1 and I2, where PM1 and PM2 form a first mirror current mirror, PM3 and PM4 form a second mirror current mirror, NM1 and NM2 form a third mirror current mirror, NM3 and NM4 form a fourth mirror current mirror, and PM5 and NM5 form an inverter. The grid and the drain of the first PMOS pipe PM1 are connected with the input port I2, and the source is connected with a power supply VCC; the grid electrode of the second PMOS tube PM2 is connected with the input port I2, the source electrode is connected with the power supply VCC, and the drain electrode is connected with the grid electrode of the third NMOS tube NM 3; the grid and the drain of the third PMOS tube PM3 are connected with the drain of the second NMOS tube NM2, and the source is connected with a power supply VCC; the grid electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the second NMOS tube NM2, the source electrode is connected with the power supply VCC, and the drain electrode is connected with the source electrode of the fifth PMOS tube PM 5; the grid electrode of the fifth PMOS tube PM5 is connected with the input port A, the source electrode is connected with the drain electrode of the fourth PMOS tube PM4, and the drain electrode is connected with the output port Y; the grid and the drain of the first NMOS transistor NM1 are connected with the input port I1, and the source is grounded; the grid electrode of the second NMOS tube NM2 is connected with the input port I1, the drain electrode is connected with the grid electrode of the third PMOS tube PM3, and the source electrode is grounded; the grid and the drain of the third NMOS tube NM3 are connected with the drain of the second PMOS tube PM2, and the source is grounded; the grid electrode of the fourth NMOS tube NM4 is connected with the drain electrode of the second PMOS tube PM2, and the source electrode is grounded; the gate of the fifth NMOS transistor NM5 is connected to the input port a, the source is connected to the drain of the fourth NMOS transistor NM4, and the drain is connected to the output port Y. The input ports I1 and I2 are connected with external input current, the input port A is connected with an external input control signal, and the output port Y is used for outputting the control signal.

Suppose the first mirror current sources PM1 and PM2 have the same MOS transistor length L1 and width W, respectively_PM1And W_PM2And is and

assume that the second mirror current sources PM3 and PM4 have the same MOS transistor length L2 and width W, respectively_PM3And W_PM4And is and

suppose the third mirror current sources NM1 and NM2 have the same MOS transistor length L3 and width W, respectively_NM1And W_NM2And is and

suppose the fourth mirror current sources NM3 and NM4 have the same MOS transistor length L4 and width W, respectively_NM3And W_NM4And is and

if the input signal A is rail-to-rail voltage, PM5 and NM5 are alternately in saturation region, and according to the mirror current principle, if PM5 is in saturation state and NM5 is in cut-off state, the current flowing through PM5 is I_PM5＝m₂m₃I₁If PM5 is in the off state and NM5 is in the saturation state, the current flowing through NM5 is I_NM5＝m₁m₄I₂Still assuming that the output port Y is connected to a capacitive load with a capacitance value C, and assuming that the charging and discharging currents of PM5 and NM5 to the capacitor C are constant, when PM5 is in a saturation region and NM5 is in a cutoff region, the current charges the capacitor through PM5, and the charging current is I_PM5The charging time is as follows:

when NM5 is in saturation region and PM5 is in cut-off region, current discharges the capacitor through NM5, the discharge current is I_NM5The discharge time is as follows:

where Vcc is the supply voltage and I1 and I2 are the magnitudes of the input currents, respectively. After the current is designed, m 1-m 4 are fixed, at this time, the rising time Tr and the falling time Tf of the output signal Y can be adjusted by changing the magnitudes of the input currents I1 and I2, and if I1 and I2 are fixed, the rising time and the falling time of the output signal are also fixed.

As shown in fig. 3, the current flowing through NM1 is I1, the current flowing through PM1 is I2, and when I1 and I2 are set to different current values, the output signal Y has different rise times Tr and fall times Tf for the same input signal a.

The utility model discloses a mirror current's mode becomes adjustable with the fixed charge-discharge current of traditional phase inverter, through the size of adjusting input current, realizes the accurate control to the level transition slope, compares in the phase inverter of the fixed level transition slope of tradition, the utility model discloses can realize the accurate control of fixed level transition slope and variable level transition slope in a flexible way, can greatly improve circuit's flexibility.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (1)

1. An inverter circuit capable of adjusting rise and fall times of an output signal in real time, comprising: the NMOS transistor device comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM4, a first PMOS transistor PM4, a second PMOS transistor PM4, a third PMOS transistor PM4, a fourth PMOS transistor PM4 and a fifth PMOS transistor PM4, wherein the first PMOS transistor PM4 and the second PMOS transistor PM4 form a first mirror current mirror, the third PMOS transistor PM4 and the fourth PMOS transistor PM4 form a second mirror current mirror, the first NMOS transistor NM4 and the second NMOS transistor NM4 form a third mirror current mirror, the third NMOS transistor NM4 and the fourth PMOS transistor NM4 form a fourth mirror current mirror, the fifth PMOS transistor PM4 and the fifth PMOS transistor PM4 form an inverter, the grid of the first PMOS transistor PM4 and the drain of the first PMOS transistor NM4 are connected with the drain of the first NMOS transistor NM4, the drain of the first PMOS transistor NM4 is connected with the drain of the PMOS transistor NM4, the drain of the second PMOS transistor PM4 is connected with the drain of the second PMOS transistor PM4, the drain of the PMOS transistor PM4 is connected with the drain of the PMOS transistor PM4, the drain of the PMOS transistor PM 36, the source of the third PMOS transistor PM3 is connected to a power source VCC, the gate of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor NM2, the source of the fourth PMOS transistor PM4 is connected to the power source VCC, the drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5, the gate of the fifth PMOS transistor PM5 is connected to the input port a, the drain of the fifth PMOS transistor PM5 is connected to the output port Y, the gate of the first NMOS transistor NM1 and the drain of the first NMOS transistor NM1 are connected to the current input port I1, the source of the first NMOS transistor NM1 is grounded, the gate of the second NMOS transistor NM2 is connected to the current input port I1, the source of the second NMOS transistor NM2 is grounded, the drain of the third NMOS transistor NM3 is connected to the drain of the second PMOS transistor PM2, the source of the third NMOS transistor NM3 is grounded, the gate of the fourth NMOS transistor 4 is connected to the drain of the second PMOS transistor PM2, the source NM4, the drain of the fifth NMOS transistor NM5 is connected to the drain of the NMOS 368658, the drain of the NMOS transistor NM 368672, and the drain of the fifth NMOS 368658 is connected to the.

Images